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DDR auto configuration and better memory support. 

1. DDR auto configuration can work correctly now.
 2. Four DIMM and up to 4G memory support.
 3. Register memory can work in 375 MHz.

FIXME: Occasionally DDR auto detection will fail.

Target: Bonito3adawning

Thanks: This patch is mainly finished by Chen Xinke <chenxinke@ict.ac.cn>
master
SUN Zhi 14 years ago
committed by LIU Qi
parent
d39d784f38
commit
1bcb33898c
8 changed files with 2940 additions and 1552 deletions
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  1. 351
      Targets/Bonito3adawning/Bonito/ddr2_config.S
  2. 585
      Targets/Bonito3adawning/Bonito/i2c.S
  3. 38
      Targets/Bonito3adawning/Bonito/i2c_firewall.S
  4. 965
      Targets/Bonito3adawning/Bonito/loongson3A_ddr2_param.S
  5. 7
      Targets/Bonito3adawning/Bonito/loongson3A_ddr3_param.S
  6. 1640
      Targets/Bonito3adawning/Bonito/loongson3_ddr2_config.S
  7. 890
      Targets/Bonito3adawning/Bonito/start.S
  8. 16
      sys/arch/mips/include/newtest/mydebug.S

351
Targets/Bonito3adawning/Bonito/ddr2_config.S
View File

@ -0,0 +1,351 @@
/**********************************
changed by cxk
a0: input, Memory Controller config register base
**********************************/
#define REG_ADDRESS 0x0
#define CONFIG_BASE 0x900000000ff00000
.global ddr2_config
.ent ddr2_config
.set noreorder
.set mips3
ddr2_config:
#ifdef AUTO_DDR_CONFIG
GET_SDRAM_TYPE
dli t1, 0x2
beq t1, a1, 2f
nop
dli t1, 0x3
beq t1, a1, 3f
nop
//not DDR2 and not DDR3, errors
b ddr2_config_end
nop
2: //DDR2
GET_DIMM_TYPE
bnez a1, 1f
nop
//UDIMM
dla a2, ddr2_reg_data
b 4f
nop
1: //RDIMM
dla a2, ddr2_RDIMM_reg_data
b 4f
nop
3: //DDR3
GET_DIMM_TYPE
bnez a1, 1f
nop
//UDIMM
dla a2, ddr3_reg_data
b 4f
nop
1: //RDIMM
dla a2, ddr3_RDIMM_reg_data
b 4f
nop
4:
#else
//mandatory set the param segment here
dla a2, ddr2_reg_data
#endif
daddu a2, a2, s0
li t1, 152
daddiu v0, a0, 0x0
reg_write:
ld a1, 0x0(a2)
sd a1, REG_ADDRESS(v0)
subu t1, t1, 0x1
addiu a2, a2, 0x8
bne t1, $0, reg_write
daddiu v0, v0, 0x10
#ifdef AUTO_DDR_CONFIG
//set v0 to MC configure register base
daddiu v0, a0, 0x0
//rewrite eight_bank_mode
ld a2, 0x10(v0)
dli a1, 0xffffff00ffffffff
and a2, a2, a1
GET_EIGHT_BANK
dsll a1, a1, EIGHT_BANK_MODE_OFFSET
or a2, a2, a1
sd a2, 0x10(v0)
//rewrite column_size and addr_pins
ld a2, 0x50(v0)
dli a1, 0xffffffff00ff00ff
and a2, a2, a1
GET_ROW_SIZE
dsll a1, a1, ADDR_PINS_OFFSET
or a2, a2, a1
GET_COL_SIZE
dsll a1, a1, COLUMN_SIZE_OFFSET
or a2, a2, a1
sd a2, 0x50(v0)
//rewrite cs_map
ld a2, 0x70(v0)
dli a1, 0xffffffffff00ffff
and a2, a2, a1
GET_MC_CS_MAP
dsll a1, a1, CS_MAP_OFFSET
or a2, a2, a1
sd a2, 0x70(v0)
//rewrite ECC control ctrl_raw
//not finished now
#endif
#ifdef MY_DEBUG_DDR //debug
/* store the a0,ra */
move t8, a0
move t1, ra
PRINTSTR("\r\nChange some parameters of MC0:");
1:
PRINTSTR("\r\nPlease input the register number you want to change!!!(0:jump out.1~0x97): ");
li t6, 0x00
bal inputaddress #input value stored in v0
nop
move t5, v0 #store v0 to t5
beqz t5, 2f #if input 0,jump out
nop
dsll t5, t5, 4 #t5 is the offset relative to a0
daddu t5, t5, t8
PRINTSTR("\r\nPlease input the data-hex: ");
li t6, 0x00
bal inputaddress #input value stored in v0
nop
sd v0, 0x0(t5) #v0 is the input value
b 1b
nop
2:
/* recover the a0,ra */
move a0, t8
move ra, t1
#endif
############start##########
/***** set start to 1,start to initialize SDRAM *****/
daddiu v0, a0, 0x30
dli a2, 0x0000010000000000
ld a1, 0x0(v0)
or a1, a1, a2
sd a1, 0x0(v0)
daddiu v0, a0, 0x960 //wait initialization complete
1:
ld a1, 0x0(v0)
andi a1, a1, 0x100
beqz a1, 1b
nop
//seems no need to do the following step
/** delay some time **/
dli a2, 0xfff
1:
bnez a2, 1b
daddiu a2, a2, -1
nop
daddiu v0, a0, 0x40 //write SDRAM mode register
dli a2, 0x0000000001000000
ld a1, 0x0(v0)
or a1, a1, a2
sd a1, 0x0(v0)
nop
sync
/** delay some time **/
dli a2, 0xfff
1:
bnez a2, 1b
daddiu a2, a2, -1
nop
###############################
ddr2_config_end:
jr ra
nop
.end ddr2_config
.global ddr2_config_mc1
.ent ddr2_config_mc1
.set noreorder
.set mips3
ddr2_config_mc1:
#ifdef AUTO_DDR_CONFIG
GET_SDRAM_TYPE
dli t1, 0x2
beq t1, a1, 2f
nop
dli t1, 0x3
beq t1, a1, 3f
nop
//not DDR2 and not DDR3, errors
b ddr2_config_mc1_end
nop
2: //DDR2
GET_DIMM_TYPE
bnez a1, 1f
nop
//UDIMM
dla a2, ddr2_reg_data_mc1
b 4f
nop
1: //RDIMM
dla a2, ddr2_RDIMM_reg_data_mc1
b 4f
nop
3: //DDR3
GET_DIMM_TYPE
bnez a1, 1f
nop
//UDIMM
dla a2, ddr3_reg_data_mc1
b 4f
nop
1: //RDIMM
dla a2, ddr3_RDIMM_reg_data_mc1
b 4f
nop
4:
#else
//mandatory set the param segment here
dla a2, ddr2_RDIMM_reg_data_mc1
#endif
daddu a2, a2, s0
li t1, 152
daddiu v0, a0, 0x0
reg_write_mc1:
ld a1, 0x0(a2)
sd a1, REG_ADDRESS(v0)
subu t1, t1, 0x1
addiu a2, a2, 0x8
bne t1, $0, reg_write_mc1
daddiu v0, v0, 0x10
#ifdef AUTO_DDR_CONFIG
//set v0 to MC configure register base
daddiu v0, a0, 0x0
//rewrite eight_bank_mode
ld a2, 0x10(v0)
dli a1, 0xffffff00ffffffff
and a2, a2, a1
GET_EIGHT_BANK
dsll a1, a1, EIGHT_BANK_MODE_OFFSET
or a2, a2, a1
sd a2, 0x10(v0)
//rewrite column_size and addr_pins
ld a2, 0x50(v0)
dli a1, 0xffffffff00ff00ff
and a2, a2, a1
GET_ROW_SIZE
dsll a1, a1, ADDR_PINS_OFFSET
or a2, a2, a1
GET_COL_SIZE
dsll a1, a1, COLUMN_SIZE_OFFSET
or a2, a2, a1
sd a2, 0x50(v0)
//rewrite cs_map
ld a2, 0x70(v0)
dli a1, 0xffffffffff00ffff
and a2, a2, a1
GET_MC_CS_MAP
dsll a1, a1, CS_MAP_OFFSET
or a2, a2, a1
sd a2, 0x70(v0)
//rewrite ECC control ctrl_raw
//not finished now
#endif
#ifdef MY_DEBUG_DDR //debug
/* store the a0,ra */
move t8, a0
move t1, ra
PRINTSTR("\r\nChange some parameters of MC1:");
1:
PRINTSTR("\r\nPlease input the register number you want to change!!!(0:jump out.1~0x97): ");
li t6, 0x00
bal inputaddress #input value stored in v0
nop
move t5, v0 #store v0 to t5
beqz t5, 2f #if input 0,jump out
nop
dsll t5, t5, 4 #t5 is the offset relative to a0
daddu t5, t5, t8
PRINTSTR("\r\nPlease input the data-hex: ");
li t6, 0x00
bal inputaddress #input value stored in v0
nop
sd v0, 0x0(t5) #v0 is the input value
b 1b
nop
2:
/* recover the a0,ra */
move a0, t8
move ra, t1
#endif
############start##########
/***** set start to 1,start to initialize SDRAM *****/
daddiu v0, a0, 0x30
dli a2, 0x0000010000000000
ld a1, 0x0(v0)
or a1, a1, a2
sd a1, 0x0(v0)
daddiu v0, a0, 0x960 //wait initialization complete
1:
ld a1, 0x0(v0)
andi a1, a1, 0x100
beqz a1, 1b
nop
//seems no need to do the following step
/** delay some time **/
dli a2, 0xfff
1:
bnez a2, 1b
daddiu a2, a2, -1
nop
daddiu v0, a0, 0x40 //write SDRAM mode register
dli a2, 0x0000000001000000
ld a1, 0x0(v0)
or a1, a1, a2
sd a1, 0x0(v0)
nop
sync
/** delay some time **/
dli a2, 0xfff
1:
bnez a2, 1b
daddiu a2, a2, -1
nop
###############################
ddr2_config_mc1_end:
jr ra
nop
.end ddr2_config_mc1
.rdata
.align 5
.global ddr2_reg_data
#include "loongson3A_ddr2_param.S"
#include "loongson3A_ddr3_param.S"

585
Targets/Bonito3adawning/Bonito/i2c.S
View File

@ -1,38 +1,23 @@
/************************
function PROBE_DIMM changed by cxk on 09/26/2010
Single CHIP & USE_SB_I2C mode & DDR2 DIMM can work normal
DDR3 SDRAM need to be finished!!
************************/
#define BONITO_HTIO_BASE_VA 0x90000efdfc000000
#define CHIP1_BASE_ADDRESS 0x0000100000000000
#define CHIP2_BASE_ADDRESS 0x0000200000000000
#define CHIP3_BASE_ADDRESS 0x0000300000000000
#define SPD_NODEVICE 0xff
#define SPD_TYPEDDR2 0x8
#define SPD_TYPEDDR3 0xc
#define DDRTYPE_MASK 0x7
#define DDRPERSZ_512M 0x10
#define DDRPERSZ_1G 0x20
#define DDRPERSZ_2G 0x30
#define SPD_MEMTYPE_OFFSET 0x02
#define SPD_ROWADDR_OFFSET 0x03
#define SPD_COLADDR_OFFSET 0x04
#define SPD_DIMRANK_OFFSET 0x11
#define SPD_RKDESITY_OFFSET 0x1f
#define SPD_DDR2SIZE_512M 0x80
#define SPD_DDR2SIZE_1G 0x01
#define SPD_DDR2SIZE_2G 0x02
#define DDR2SIZE_512M_MASK 0x10
#define DDR2SIZE_1G_MASK 0x20
#define DDR2SIZE_2G_MASK 0x30
#define DDR2SIZE_MASK 0x70
#ifndef MULTI_CHIP
#ifdef USE_SB_I2C
LEAF(i2cread)
/***************
use register:
v0, v1
a0, a1
***************/
ori a0,a0,1
/* set device address */
//li v0, 0xbfd00000 + SMBUS_HOST_ADDRESS
@ -61,7 +46,6 @@ LEAF(i2cread)
sb v0, 0(v1)
lbu v0, 0(v1) #flush the write
1:
/* start */
//li v1, 0xbfd00000 + SMBUS_HOST_CONTROL
dli v1, BONITO_HTIO_BASE_VA + SMBUS_HOST_CONTROL
@ -104,293 +88,286 @@ LEAF(i2cread)
jr ra
nop
END(i2cread)
#else
#ifdef USE_GPIO_I2C
#include "i2c_firewall.S"
#endif
LEAF(PROBE_DIMM)
move a3,ra;
move s2,a0; //store a0: i2C DEVICE id
move s3,a1; //store a1: REG offset in i2c dev
li a1, 2;
bal i2cread;
nop;
beq v0,SPD_NODEVICE, out;
nop;
/* set DDR type @ s1[7:7] */
/* assumed here v0 should be 0xc or 0x8 */
//bne v0,SPD_TYPEDDR3, ddr2
andi v0,0x4;
srl v0,0x2;
sll v0,DDRTYPE_MASK ;
or s1,v0;
/* set CONTROLLER_SELECT@ s1[3:2] */
/* a1 should set to be MC0_USED or MC1_USD */
/* Firt check whether BOTH MC0 and MC1 used, if
true,set s1[3:2] = 2b'00
*/
or s1,s3;
andi t1,s1,0xc;
bne t1,0xc,10f;
nop
subu s1,0xc
#endif
10:
/* set SIZE_PER_CONTROLLE @ s1[6:4] */
/* step 1: read out number of DIMMS Ranks(CS) */
move a0, s2; //store a1: REG offset in i2c dev
li a1, 5;
bal i2cread;
nop;
andi v0,0x3; // MASK for DIMMS Ranks(CS)
move t2,v0;
/*************************
PROBE_DIMM:
function: probe the given slot(I2C device id is given in a0),
if there is no DIMM in this slot, clear SDRAM_TYPE to 0,
else read the DIMM infor from the SPD and store the infor in s1(CS_MAP at [17:16],
MEMSIZE at [11:8]).
use register:
a0,a1,a2,a3
v0, v1
t5, t6
t7: store ra
a0: input, i2c device id(don't change it).
a1: register offset of i2c device
*************************/
#if 0 //debug code, used in PROBE_DIMM, after read i2c, print v0
//debug------------
move t5, a0
move t6, v0
TTYDBG("\r\nBanks: ")
move a0, t6
bal hexserial
nop
TTYDBG("\r\n")
move a0, t5
move v0, t6
//------------debug
//Test whether i2cread will dead loop
move t5, a0
TTYDBG("\r\nIn Probe_DIMM, before i2cread!")
move a0, t5
dli a1, 0
bal i2cread
nop
move t5, a0
TTYDBG("\r\nIn Probe_DIMM, after i2cread!")
move a0, t5
#endif
LEAF(PROBE_DIMM)
move t7, ra
//bez t2,out
nop
addi t2,0x1
//read the i2c spd for learn,read data is abandon
dli a1, 0
bal i2cread
nop
/* step 2: read out DIMMS size */
move a0,s2;
li a1, 31;
bal i2cread;
nop;
bne v0,SPD_DDR2SIZE_512M, 11f;
nop;
//ori s1,DDR2SIZE_512M_MASK;
li v0, 0x20000000
b 1f;
nop;
11:
bne v0,SPD_DDR2SIZE_1G, 12f;
nop;
//ori s1,DDR2SIZE_1G_MASK;
li v0, 0x40000000
b 1f;
nop;
12:
bne v0,SPD_DDR2SIZE_2G, 1f;
nop;
//ori s1,DDR2SIZE_2G_MASK; // v0: 0x80 means 1G
li v0, 0x80000000;
//probe SDRAM type, if SDRAM type error, repeat t6 times.
dli t6, 8 //max probing times(t6)
1:
/* step 3: calculate each mem SIZE of one slot*/
beq t2,0x1,21f;
nop
sll v0,0x1
//multu v0,t2;
21:
bne v0,0x20000000, 13f
nop;
/* check whther this channel is smaller than others
if smller: remove other bits,and set DDRPERSZ_512M
else: do nothing, don't set PERSIZE_BIT
// defalut setting 512M leaset MEM size
*/
andi t1,s1,DDR2SIZE_MASK;
beqz t1,211f;
nop
bleu t1,DDR2SIZE_512M_MASK, 15f;
nop
li t1,DDR2SIZE_MASK;
not t2,t1;
and s1,t2;
211:
ori s1,DDRPERSZ_512M ;
b 15f;
nop
13:
bne v0,0x40000000, 14f
nop
/* check whther this channel is smaller than others
if smller: remove other bits,and set DDRPERSZ_1G
else: do nothing, don't set PERSIZE_BIT
*/
andi t1,s1,DDR2SIZE_MASK;
beqz t1,131f;
nop
bleu t1, DDR2SIZE_1G_MASK,15f
nop
li t1,DDR2SIZE_MASK;
not t2,t1;
and s1,t2;
131:
ori s1,DDRPERSZ_1G;
b 15f;
nop
14:/* only support 512M,1G,2G per DIMM now */
bne v0,0x80000000, 15f
nop
/* check whther this channel is smaller than others
if smller: remove other bits,and set DDRPERSZ_2G
else: do nothing, don't set PERSIZE_BIT
*/
andi t1,s1,DDR2SIZE_MASK;
beqz t1,141f;
nop
bleu t1, DDR2SIZE_2G_MASK,15f
nop
li t1,DDR2SIZE_MASK;
not t2,t1;
and s1,t2;
141:
ori s1,DDRPERSZ_2G;
15:
/* check whether MC0 or MC1 used to set CS_MAP */
bne s3, MC0_USED, 2f;
nop;
/* set DDR MC0_CS_MAP @s1[11:8] */
ori s1, 0x400 // at leaset one bit is selected
move a0,s2;
li a1, 5;
bal i2cread;
nop;
andi v0,0x1;
beq v0,0x0,16f;
nop;
ori s1,0x800;
16:
/* set DDR MC0_COL_SIZE @s1[18:16] */
move a0,s2;
li a1, 4;
bal i2cread;
nop;
li t0,14;
sub t0,v0;
sll t0,0x10;
or s1,t0;
/* set MC0_EIGHT_BANK @s1[19] */
move a0,s2;
li a1, 17;
bal i2cread;
nop;
andi v0,0x8;
srl v0,0x3;
sll v0,0x13; //MC0_EIGHT_BANK shift
or s1,v0;
/* set DDR MC0_ROW_SIZE @s1[22:20] */
move a0,s2;
li a1, 3;
bal i2cread;
nop;
li t0,15;
sub t0,v0;
sll t0,0x14;
or s1,t0;
/* set MC0_ECC bit @s1[32] */
move a0,s2;
li a1, 11;
bal i2cread;
li t0,0x2;
andi v0,0x2;
srl v0,0x1;
dsll v0,32;
//dli v0,0x100000000 // for test
or s1,v0;
/* set DIMM Type information @s1[33:33] */
move a0,s2;
li a1, 20;
bal i2cread;
nop;
andi v0,0x1; // only to check whether in Register Dual In_line memory module
dsll v0,33;
or s1,v0;
b out;
nop;
//delay some time
dli t5, 0xfff
2:
daddiu t5, t5, -1
bnez t5, 2b
nop
2: /* MC1_USED */
#if 1
daddiu t6, t6, -1
/* set DDR MC1_CS_MAP @s1[15:12] ? */
ori s1, 0x4000 // at leaset one bit is selected
move a0,s2;
li a1, 5;
bal i2cread;
nop;
andi v0,0x1;
beq v0,0x0, 26f
dli a1, 2
bal i2cread
nop
ori s1,0x8000
26:
/* set DDR MC1_COL_SIZE @s1[26:24] */
move a0,s2;
li a1, 4;
bal i2cread;
nop;
li t0,14;
sub t0,v0;
sll t0,0x18;
or s1,t0;
/* set MC1_EIGHT_BANK @s1[27] ? */
move a0,s2
li a1, 17;
bal i2cread;
nop;
andi v0,0x8;
srl v0,0x3;
sll v0,27; //MC0_EIGHT_BANK shift
or s1,v0;
/* set DDR MC1_ROW_SIZE @s1[30:28] */
move a0,s2;
li a1, 3;
bal i2cread;
nop;
li t0,15;
sub t0,v0;
sll t0,0x1c;
or s1,t0;
/* set MC1_ECC bit @s1[34] */
move a0,s2;
li a1, 11;
bal i2cread;
li t0,0x2;
andi v0,0x2;
srl v0,0x1;
dsll v0,34;
or s1,v0;
/* set DIMM Type information @s1[35:35] */
move a0,s2;
li a1, 20;
bal i2cread;
nop;
and v0,0x1;// only to check whether in Register Dual In_line memory module
dsll v0,35;
or s1,v0;
#endif
out:/* out of MC0_CS_MAP or MC1_CS_MAP */
//jr ra
jr a3
//only bit[7:0] used
andi v0, v0, 0xff
/* v0 should be 0xb or 0x8,else error DIMM type */
dli t5, 0x08
beq v0, t5, DDR2
nop
dli t5, 0x0B
beq v0, t5, DDR3
nop
//this time probe error
bnez t6, 1b
nop
3:
TTYDBG("\r\nNO DIMM in this slot.\r\n")
b ERROR_TYPE
nop
DDR2:
dli t5, 0x2
dsll t5, t5, SDRAM_TYPE_OFFSET
or s1, s1, t5
//probe DIMM_TYPE
dli a1, 20
bal i2cread
nop
//only bit[5:0] used
andi v0, v0, 0x3f
//here just recognize RDIMM and UDIMM
dli t5, 0x01
beq v0, t5, 1f
nop
dli t5, 0x02
beq v0, t5, 2f
nop
TTYDBG("\r\nERROR: DIMM type is not in support range(UDIMM or RDIMM).\r\n")
b ERROR_TYPE
nop
1: //RDIMM
dli t5, 0x1
dsll t5, t5, DIMM_TYPE_OFFSET
or s1, s1, t5
b 3f
nop
2: //UDIMM
3:
//probe DIMM ECC
dli a1, 11
bal i2cread
nop
//only bit[2:0] used
andi v0, v0, 0x07
//here just recognize ECC or not
andi t5, v0, 0x2
dsrl t5, t5, 1
dsll t5, t5, DIMM_ECC_OFFSET
or s1, s1, t5
//probe SDRAM_ROW_SIZE
dli a1, 3
bal i2cread
nop
//only bit[7:0] used
andi v0, v0, 0xff
//v0 should < 15
andi v0, v0, 0x0f
dli t5, 15
subu t5, t5, v0
dsll t5, t5, ROW_SIZE_OFFSET
or s1, s1, t5
//probe SDRAM_COL_SIZE
dli a1, 4
bal i2cread
nop
//only bit[7:0] used
andi v0, v0, 0xff
//v0 should < 14
andi v0, v0, 0x0f
dli t5, 14
subu t5, t5, v0
dsll t5, t5, COL_SIZE_OFFSET
or s1, s1, t5
//probe SDRAM BANK number
dli a1, 17
bal i2cread
nop
//bit[7:0] used
andi v0, v0, 0xff
//here just recognize 4 banks or 8 banks
dli t5, 0x08
beq v0, t5, 1f
nop
dli t5, 0x04
beq v0, t5, 2f
nop
TTYDBG("\r\nERROR: SDRAM Banks number is not in support range(4 or 8).\r\n")
b ERROR_TYPE
nop
1: //8 banks
dli t5, 0x1
dsll t5, t5, EIGHT_BANK_OFFSET
or s1, s1, t5
b 3f
nop
2: //4 banks
3:
//probe DIMM Ranks
dli a1, 5
bal i2cread
nop
//only bit[2:0] used
andi v0, v0, 0x7
//here just recognize 1 ranks or 2 ranks
dli t5, 0x0
beq v0, t5, 1f
nop
dli t5, 0x1
beq v0, t5, 2f
nop
TTYDBG("\r\nERROR: DIMM Ranks number is not in support range(1 or 2).\r\n")
b ERROR_TYPE
nop
1: //1 rank
dli t5, 0x1
b 3f
nop
2: //2 ranks
dli t5, 0x3
3:
dsll t5, t5, MC_CS_MAP_OFFSET
or s1, s1, t5
//probe DIMM Memory SIZE
dli a1, 31
bal i2cread
nop
//only bit[7:0] used
andi v0, v0, 0xff
//currently only support 1 rank >= 512M & 2 ranks <= 4G, else assume there is NO DIMM
move t5, v0
dli t6, 0xe0
and t5, t5, t6
beqz t5, 1f
nop
//1 rank<= 512M
dsrl t5, t5, 7
beqz t5, 2f //1 rank < 512M, error
nop
//1 rank = 512M, double the MEMSIZE if there are 2 ranks
GET_MC_CS_MAP
dsrl a1, a1, 1 //test the cs 1
beqz a1, 5f
nop
//double the size
dsll t5, t5, 1
5:
dsll t5, t5, DIMM_MEMSIZE_OFFSET
or s1, s1, t5
b 3f
nop
1: //1 rank >= 1G
//double the MEMSIZE if there are 2 ranks
GET_MC_CS_MAP
dsrl a1, a1, 1 //test the cs 1
beqz a1, 5f
nop
//double the size
dsll v0, v0, 1
5:
dli t5, 0x7
and t5, t5, v0
beqz t5, 2f //DIMM SIZE > 4G
nop
dsll t5, v0, 1 //MEMSIZE is 512M/unit, v0 is 1G/unit
dsll t5, t5, DIMM_MEMSIZE_OFFSET
or s1, s1, t5
b 3f
nop
2:
//1 rank < 512M or DIMM SIZE > 4G, errors(clear SDRAM_TYPE, assume there is NO DIMM in this slot)
dli t5, 0x3
dsll t5, t5, SDRAM_TYPE_OFFSET
not t5, t5
and s1, s1, t5
TTYDBG("\r\nERROR: DIMM size is not in support range(512M~4G).\r\n")
b ERROR_TYPE
nop
3:
//DDR2 probe finished
b end
nop
DDR3: //DDR3 SDRAM
dli t5, 0x3
dsll t5, t5, SDRAM_TYPE_OFFSET
or s1, s1, t5
//!!!!!!need to be completed
b end
nop
ERROR_TYPE:
//no DIMM or unrecognized DIMM in this slot
dli t5, 0x3
dsll t5, t5, SDRAM_TYPE_OFFSET
not t5, t5
and s1, s1, t5
end:
jr t7
nop
END(PROBE_DIMM)
#else
#else //Multi chips
//not checked now!!!!!!!!!!1
/****************************************************/
/* for multi-chip mode */
/****************************************************/
@ -790,4 +767,4 @@ out:/* out of MC0_CS_MAP or MC1_CS_MAP */
nop
END(PROBE_DIMM)
#endif
#endif

38
Targets/Bonito3adawning/Bonito/i2c_firewall.S
View File

@ -3,10 +3,10 @@
#define G_OUTPUT 0
#define G_INPUT 1
#define GPIO_SDA_DIR_SHIFT 2
#define GPIO_SCL_DIR_SHIFT 3
#define GPIO_SDA_DATA_SHIFT 2
#define GPIO_SCL_DATA_SHIFT 3
#define GPIO_SDA_DIR_SHIFT 1
#define GPIO_SCL_DIR_SHIFT 8
#define GPIO_SDA_DATA_SHIFT 1
#define GPIO_SCL_DATA_SHIFT 8
/*
can't use t1,t5,t6
@ -29,6 +29,12 @@ LEAF(_i2c_sleep)
END(_i2c_sleep)
/*****************************************/
/* used to set sda direction */
/* a0: 1,means set input, 0 means output */
/*****************************************/
LEAF(_sda_dir)
li t0,GPIO_DIR_HIGH
lwu t2,0(t0)
@ -50,6 +56,12 @@ LEAF(_sda_dir)
END(_sda_dir)
/*****************************************/
/* used to set scl direction */
/* a0: 1,means set input, 0 means output */
/*****************************************/
LEAF(_scl_dir)
li t0,GPIO_DIR_HIGH
lwu t2,0(t0)
@ -71,6 +83,12 @@ LEAF(_scl_dir)
END(_scl_dir)
/*****************************************/
/* used to write date to sda */
/* a0: 1,means set high, 0 means set low */
/*****************************************/
LEAF(_sda_bit)
li t0,GPIO_DATA_HIGH
lwu t2,0(t0)
@ -91,6 +109,12 @@ LEAF(_sda_bit)
nop
END(_sda_bit)
/*****************************************/
/* used to write date to scl */
/* a0: 1,means set high, 0 means set low */
/*****************************************/
LEAF(_scl_bit)
li t0,GPIO_DATA_HIGH
lwu t2,0(t0)
@ -113,9 +137,11 @@ END(_sda_bit)
LEAF(_i2c_start)
/* used to save returun PC */
move t7,ra
/* begin to set start condition */
li a0,G_OUTPUT
bal _sda_dir
nop
@ -218,8 +244,8 @@ LEAF(_i2c_send_ack)
nop
li a0,1
bal _scl_bit
nop
li a0,5
nop
li a0,5
bal _i2c_sleep
nop
li a0,0

965
Targets/Bonito3adawning/Bonito/loongson3A_ddr2_param.S
View File

@ -0,0 +1,965 @@
//param for UDIMM--------------------------------
//This is good at 250M.
ddr2_reg_data:
MC0_CTL_000 : .dword 0x0000010000000101
//000000000000000_0 concurrentap(RW) 0000000_1 bank_split_en(RW) 0000000_0 auto_refresh_mode(RW) 0000000_0 arefresh(WR) 0000000_0 ap(RW) 0000000_1 addr_cmp_en(RW) 0000000_1 active_aging(RW)
MC0_CTL_010 : .dword 0x0001000100010000
//0000000_0 fwc(WR) 0000000_0 fast_write(RW) 0000000_1 enable_quick_srefresh(RW) 0000000_1 eight_bank_mode(RW) 0000000_0 ecc_disable_w_uc_err(RW) 0000000_1 dqs_n_en(RW) 0000000_0 dll_bypass_mode(RW) 0000000_0 dlllockreg(RD)
MC0_CTL_020 : .dword 0x0100010101000000
//0000000_1 priority_en(RW) 0000000_0 power_down(RW) 0000000_1 placement_en(RW) 0000000_1 odt_add_turn_clk_en(RW) 0000000_0 no_cmd_init(RW) 0000000_0 intrptwritea(RW) 0000000_0 intrptreada(RW) 0000000_0 intrptapburst(RW)
MC0_CTL_030 : .dword 0x0001000001000000
//0000000_1 swap_port_rw_same_en(RW) 0000000_1 swap_en(RW) 0000000_0 start(RW) 0000000_0 srefresh(RW+) 0000000_1 rw_same_en(RW) 0000000_0 reg_dimm_enable(RW) 0000000_0 reduc(RW) 0000000_0 pwrup_srefresh_exit(RW)
MC0_CTL_040 : .dword 0x0102010200000100
//000000_01 rtt_0(RW) 000000_11 ctrl_raw(RW) 000000_01 axi0_w_priority(RW) 000000_01 axi0_r_priority(RW) 0000000_0 write_modereg(WR) 0000000_1 writeinterp(RW) 0000000_1 tref_enable(RW) 0000000_1 tras_lockout(RW)
MC0_CTL_050 : .dword 0x0200000004060100
//00000_000 q_fullness(RW) 00000_000 port_data_error_type(RD) 000_00000 out_of_range_type(RD) 00000_000 max_cs_reg(RD) 00000_100 column_size(RW) 0000_0101 caslat(RW) 00000_010 addr_pins(RW) 00000000
MC0_CTL_060 : .dword 0x0a05030603030003
//0000_1010 aprebit(RW) 0000_0101 wrlat(RW) 0000_0100 twtr(RW) 000_00110 twr_int(RW) 00000_011 trtp(RW) 00000_100 trrd(RW) 0000000000000_011 tcke(RW)
MC0_CTL_070 : .dword 0x0000020000030c0c
//0000_0000 max_row_reg(RD) 0000_0000 max_col_reg(RD) 0000_0000 initaref(RW) 00000000000000000000_1111 cs_map(RW) 000_01010 caslat_lin_gate(RW) 000_01010 caslat_lin(RW)
MC0_CTL_080 : .dword 0x0804020108040201
//0000_0001 odt_wr_map_cs3(RW) 0000_0010 odt_wr_map_cs2(RW) 0000_0100 odt_wr_map_cs1(RW) 0000_1000 odt_wr_map_cs0(RW) 0000_0001 odt_rd_map_cs3(RW) 0000_0010 odt_rd_map_cs2(RW) 0000_0100 odt_rd_map_cs1(RW) 0000_1000 odt_rd_map_cs0(RW)
MC0_CTL_090 : .dword 0x0000070d00000000
//000_00000 ocd_adjust_pup_cs_0(RW) 000_00000 ocd_adjust_pdn_cs_0(RW) 0000_0101 trp(RW) 000_01011 tdal(RW) 000000000000_0000 port_cmd_error_type(RD) 0000000000000000
MC0_CTL_0a0 : .dword 0x0000003f3f18050e
//00000000000000000000000000_111111 command_age_count(RW) 00_111111 age_count(RW) 000_10100 trc(RW) 000_00110 tmrd(RW) 000_10010 tfaw(RW)
MC0_CTL_0b0 : .dword 0x0000000000000000
MC0_CTL_0c0 : .dword 0x0000330612000000
//000000000000000000101100 trfc(RW) 00000101 trcd_int(RW) 00001111 tras_min(RW) 00000000 out_of_range_length(RD) 00000000 ecc_u_synd(RD) 00000000 ecc_c_synd(RD)
MC0_CTL_0d0 : .dword 0x0000000000000000
MC0_CTL_0e0 : .dword 0x0000000000000000
MC0_CTL_0f0 : .dword 0x0000000000000000
//Bit 21:16 dll_lock(RD)
MC0_CTL_100 : .dword 0x0000000000000000
//MC0_CTL_110 : .dword 0x00000000000002e0 #100M+
MC0_CTL_110 : .dword 0x00000000000005e0 #200M+
//MC0_CTL_110 : .dword 0x0000000000000900 #300M+
//MC0_CTL_110 : .dword 0x0000000000000c00 #400M
//0_000000000000000 emrs2_data_1(RW) 0_000000000000000 emrs2_data_0(RW) 000000000000000000_00110000101101 tref(RW)
MC0_CTL_120 : .dword 0xffff000000000000
//0000000000011100 axi0_en_size_lt_width_instr(RW) 00000000000000000_000000000000000 emrs2_data_3(RW) 0_000000000000000 emrs2_data_2(RW)
//MC0_CTL_130 : .dword 0x1b20000200c800c8 #100M+
MC0_CTL_130 : .dword 0x3680000200c800c8 #200M+
//MC0_CTL_130 : .dword 0x51d0000200c800c8 #300M+
//MC0_CTL_130 : .dword 0x6d30000200c800c8 #400M
//0110110101010110 tras_max(RW) 0000000000000011 tpdex(RW) 0000001000000000 tdll(RW) 0000000000000000 tcpd(RW)
MC0_CTL_140 : .dword 0x0000204000c80037
//0000000000000000 xor_check_bits(RW) 0000000000000000 version(RD) 0000001000000000 txsr(RW) 0000000000110000 txsnr(RW)
MC0_CTL_150 : .dword 0x0000000000027100
//000_0000000000000000000000000000000000000 ecc_c_addr(RD) 000000000000000000011011 tinit(RW)
MC0_CTL_160 : .dword 0x0000000000000000
//000000000000000000000000000_0000000000000000000000000000000000000 ecc_u_addr(RD)
MC0_CTL_170 : .dword 0x0000000000000000
//000000000000000000000000000_0000000000000000000000000000000000000 out_of_range_addr(RD)
MC0_CTL_180 : .dword 0x0000000000000000
//000000000000000000000000000_0000000000000000000000000000000000000 port_cmd_error_addr(RD)
MC0_CTL_190 : .dword 0x0000000000000000
//0000000000000000000000000000000000000000000000000000000000000000 ecc_c_data(RD)
MC0_CTL_1a0 : .dword 0x0000000000000000
//0000000000000000000000000000000000000000000000000000000000000000 ecc_u_data(RD)
MC0_CTL_1b0 : .dword 0x0000000000000000
//0000000000000000000000000000000000000000000000000000000000000_000 cke_delay(RW)
MC0_CTL_1c0 : .dword 0x0000000000000000
MC0_CTL_1d0 : .dword 0x0200070000000001
//0000_0010 tdfi_phy_wrlat_base(RW) 0000_0000 tdfi_phy_wrlat(RD) 000_00111 tdfi_phy_rdlat(RW) 0000_0000 tdfi_ctrlupd_min(RD) 000000000000_0000 dram_clk_disable(RW) 0000000_1 odt_alt_en(RW) 0000000_1 drive_dq_dqs(RW)
MC0_CTL_1e0 : .dword 0x0000000000000200
//00_00000000000000 tdfi_phyupd_type0(RD) 00_00000000000000 tdfi_phyupd_resp(RD) 00_00000000000000 tdfi_ctrlupd_max(RD) 000_00000 tdfi_rddata_en_base(RW) 000_00000 tdfi_rddata_en(RD)
MC0_CTL_1f0 : .dword 0x0014208000000000
MC0_CTL_200 : .dword 0x0014208000142080
MC0_CTL_210 : .dword 0x0014208000142080
MC0_CTL_220 : .dword 0x0014208000142080
MC0_CTL_230 : .dword 0x0014208000142080
MC0_CTL_240 : .dword 0x0000200000002000
MC0_CTL_250 : .dword 0x0000200000002000
MC0_CTL_260 : .dword 0x0000200000002000
MC0_CTL_270 : .dword 0x0000200000002000
MC0_CTL_280 : .dword 0x0000000000002000
MC0_CTL_290 : .dword 0x0000000000000000
//hXXXXXXX 00_00 dll_obs_reg_0_2(RW) hXXXXXXX 00_00 dll_obs_reg_0_1(RW)
MC0_CTL_2a0 : .dword 0x0000000000000000
//hXXXXXXX 00_00 dll_obs_reg_0_4(RW) hXXXXXXX 00_00 dll_obs_reg_0_3(RW)
MC0_CTL_2b0 : .dword 0x0000000000000000
//hXXXXXXX 00_00 dll_obs_reg_0_6(RW) hXXXXXXX 00_00 dll_obs_reg_0_5(RW)
MC0_CTL_2c0 : .dword 0x0000000000000000
//hXXXXXXX 00_00 dll_obs_reg_0_8(RW) hXXXXXXX 00_00 dll_obs_reg_0_7(RW)
#if 0
MC0_CTL_2d0 : .dword 0xc400484403c009b4
MC0_CTL_2e0 : .dword 0xc4004844c4004844
MC0_CTL_2f0 : .dword 0xc4004844c4004844
MC0_CTL_300 : .dword 0xc4004844c4004844
MC0_CTL_310 : .dword 0xc4004844c4004844
#endif
#if 1
MC0_CTL_2d0 : .dword 0xc300483303c009b4
MC0_CTL_2e0 : .dword 0xc3004833c3004833
MC0_CTL_2f0 : .dword 0xc3004833c3004833
MC0_CTL_300 : .dword 0xc3004833c3004833
MC0_CTL_310 : .dword 0xc3004833c3004833
#endif
MC0_CTL_320 : .dword 0x26c0000126c00001
MC0_CTL_330 : .dword 0x26c0000126c00001
MC0_CTL_340 : .dword 0x26c0000126c00001
MC0_CTL_350 : .dword 0x26c0000126c00001
MC0_CTL_360 : .dword 0x0800c00026c00001
//00000000000000001100000000000101 phy_ctrl_reg_2(RW) 00000111110000000000001100000001 phy_ctrl_reg_1_8(RD)
//--------------
MC0_CTL_370 : .dword 0x0000000000000000
MC0_CTL_380 : .dword 0x0000000000000000
MC0_CTL_390 : .dword 0x0000000000000000
MC0_CTL_3a0 : .dword 0x0000000000000000
MC0_CTL_3b0 : .dword 0x0000000000000000
MC0_CTL_3c0 : .dword 0x0000000000000000
MC0_CTL_3d0 : .dword 0x0000000000000000
MC0_CTL_3e0 : .dword 0x0000000000000000
MC0_CTL_3f0 : .dword 0x0000000000000000
MC0_CTL_400 : .dword 0x0000000000000000
MC0_CTL_410 : .dword 0x0000000000000000
MC0_CTL_420 : .dword 0x0000000000000000
MC0_CTL_430 : .dword 0x0000000000000000
MC0_CTL_440 : .dword 0x0000000000000000
MC0_CTL_450 : .dword 0x0000000000000000
MC0_CTL_460 : .dword 0x0000000000000000
MC0_CTL_470 : .dword 0x0000000000000000
MC0_CTL_480 : .dword 0x0000000000000000
MC0_CTL_490 : .dword 0x0000000000000000
MC0_CTL_4a0 : .dword 0x0000000000000000
MC0_CTL_4b0 : .dword 0x0000000000000000
MC0_CTL_4c0 : .dword 0x0000000000000000
MC0_CTL_4d0 : .dword 0x0000000000000000
MC0_CTL_4e0 : .dword 0x0000000000000000
MC0_CTL_4f0 : .dword 0x0000000000000000
MC0_CTL_500 : .dword 0x0000000000000000
MC0_CTL_510 : .dword 0x0000000000000000
MC0_CTL_520 : .dword 0x0000000000000000
MC0_CTL_530 : .dword 0x0000000000000000
MC0_CTL_540 : .dword 0x0000000000000000
MC0_CTL_550 : .dword 0x0000000000000000
MC0_CTL_560 : .dword 0x0000000000000000
MC0_CTL_570 : .dword 0x0000000000000000
MC0_CTL_580 : .dword 0x0000000000000000
MC0_CTL_590 : .dword 0x0000000000000000
MC0_CTL_5a0 : .dword 0x0000000000000000
MC0_CTL_5b0 : .dword 0x0000000000000000
MC0_CTL_5c0 : .dword 0x0000000000000000
MC0_CTL_5d0 : .dword 0x0000000000000000
MC0_CTL_5e0 : .dword 0x0000000000000000
MC0_CTL_5f0 : .dword 0x0000000000000000
MC0_CTL_600 : .dword 0x0000000000000000
MC0_CTL_610 : .dword 0x0000000000000000
MC0_CTL_620 : .dword 0x0000000000000000
MC0_CTL_630 : .dword 0x0000000000000000
MC0_CTL_640 : .dword 0x0000000000000000
MC0_CTL_650 : .dword 0x0000000000000000
MC0_CTL_660 : .dword 0x0000000000000000
MC0_CTL_670 : .dword 0x0000000000000000
MC0_CTL_680 : .dword 0x0000000000000000
MC0_CTL_690 : .dword 0x0000000000000000
MC0_CTL_6a0 : .dword 0x0000000000000000
MC0_CTL_6b0 : .dword 0x0000000000000000
MC0_CTL_6c0 : .dword 0x0000000000000000
MC0_CTL_6d0 : .dword 0x0000000000000000
MC0_CTL_6e0 : .dword 0x0000000000000000
MC0_CTL_6f0 : .dword 0x0000000000000000
MC0_CTL_700 : .dword 0x0000000000000000
//-------------
MC0_CTL_710 : .dword 0x0000000000000000
//bit 48 en_wr_leveling(RW)
MC0_CTL_720 : .dword 0x0000000000000000
//0000000_0 rdlvl_gate_req(WR) 0000000_0 rdlvl_gate_preamble_check_en(RW) 0000000_0 rdlvl_gate_en(RW) 0000000_0 rdlvl_en(RW) 0000000_0 rdlvl_begin_delay_en(RW) 00000000 00000000 0000000_0 swlvl_op_done(RD)
MC0_CTL_730 : .dword 0x0000000000000000
//0000000_0 rdlvl_offset_dir_7(RW) 0000000_0 rdlvl_offset_dir_6(RW) 0000000_0 rdlvl_offset_dir_5(RW)0000000_0 rdlvl_offset_dir_4(RW) 0000000_0 rdlvl_offset_dir_3(RW) 0000000_0 rdlvl_offset_dir_2(RW) 0000000_0 rdlvl_offset_dir_1(RW) 0000000_0 rdlvl_offset_dir_0(RW)
MC0_CTL_740 : .dword 0x0100000000000000
//000000_00 axi1_port_ordering(RW) 000000_00 axi0_port_ordering(RW) 0000000_0 wrlvl_req(WR) 0000000_0 wrlvl_interval_ct_en(RW) 0000000_0 weight_round_robin_weight_sharing(RW) 0000000_0 weight_round_robin_latency_control 0000000_0(RW) rdlvl_req 0000000_0(WR) rdlvl_offset_dir_8(RW)
MC0_CTL_750 : .dword 0x0000000101020101
//000000_01 wrlvl_cs(RW) 000000_00 sw_leveling_mode(RW) 000000_00 rdlvl_cs(RW) 000000_01 axi2_w_priority(RW) 000000_01 axi2_r_priority(RW) 000000_10 axi2_port_ordering(RW) 000000_01 axi1_w_priority(RW) 000000_01 axi1_r_priority(RW)
MC0_CTL_760 : .dword 0x0303030000020000
//0000_0011 axi0_priority2_relative_priority(RW) 0000_0011 axi0_priority1_relative_priority(RW) 0000_0011 axi0_priority0_relative_priority(RW) 0000_0000 address_mirroring(RW) 00000_000 tdfi_dram_clk_disable(RW) 00000_010 bstlen(RW) 000000_00 zq_req(WR) 000000_01 zq_on_sref_exit(RW)
MC0_CTL_770 : .dword 0x0101010202020203
//0000_0001 axi2_priority2_relative_priority(RW) 0000_0001 axi2_priority1_relative_priority(RW) 0000_0001 axi2_priority0_relative_priority(RW) 0000_0010 axi1_priority3_relative_priority(RW) 0000_0010 axi1_priority2_relative_priority(RW) 0000_0010 axi1_priority1_relative_priority(RW) 0000_0010 axi1_priority0_relative_priority(RW) 0000_0011 axi0_priority3_relative_priority(RW)
MC0_CTL_780 : .dword 0x0102000000040001
//0000_0001 tdfi_dram_clk_enable(RW) 0000_0010 tdfi_ctrl_delay(RW) 0000_0010 rdlvl_gate_dq_zero_count(RW) 0000_0100 rdlvl_dq_zero_count(RW) 0000_0000 lowpower_refresh_enable(RW) 0000_0110 dram_class(RW) 0000_1100 burst_on_fly_bit(RW) 0000_0001 axi2_priority3_relative_priority(RW)
MC0_CTL_790 : .dword 0x0000000000000000
//00_101000 wlmrd(RW) 00_011001 wldqsen(RW) 000_00000 lowpower_control(RW) 000_00000 lowpower_auto_enable(RW) 0000_1111 zqcs_chip(RW) 0000_0000 wrr_param_value_err(RD) 0000_0011 tdfi_wrlvl_dll(RW) 0000_0011 tdfi_rdlvl_dll(RW)
MC0_CTL_7a0 : .dword 0x0000000000000000
//_00000000 swlvl_resp_6(RW) _00000000 swlvl_resp_5(RW) _00000000 swlvl_resp_4 _00000000 swlvl_resp_3(RW) _00000000 swlvl_resp_2(RW) _00000000 swlvl_resp_1(RW) _00000000 swlvl_resp_0(RW) _00000000 dfi_wrlvl_max_delay(RW)
MC0_CTL_7b0 : .dword 0x0000000000000000
//_00000000 rdlvl_begin_delay_5(RW) _00000000 rdlvl_begin_delay_4(RW) _00000000 rdlvl_begin_delay_3(RW) _00000000 rdlvl_begin_delay_2(RW) _00000000 rdlvl_begin_delay_1(RW) _00000000 rdlvl_begin_delay_0(RW) _00000000 swlvl_resp_8(RW) _00000000 swlvl_resp_7(RW)
MC0_CTL_7c0 : .dword 0x0000000000000000
//_00000000 rdlvl_end_delay_4(RW) _00000000 rdlvl_end_delay_3(RW) _00000000 rdlvl_end_delay_2(RW) _00000000 rdlvl_end_delay_1(RW) _00000000 rdlvl_end_delay_0(RW) _00000000 rdlvl_begin_delay_8(RW) _00000000 rdlvl_begin_delay_7(RW) _00000000 rdlvl_begin_delay_6(RW)
MC0_CTL_7d0 : .dword 0x0000000000000000
//_00000000 rdlvl_gate_clk_adjust_3(RW) _00000000 rdlvl_gate_clk_adjust_2(RW) _00000000 rdlvl_gate_clk_adjust_1(RW) _00000000 rdlvl_gate_clk_adjust_0(RW) _00000000 rdlvl_end_delay_8(RW) _00000000 rdlvl_end_delay_7(RW) _00000000 rdlvl_end_delay_6(RW) 00000000 rdlvl_end_delay_5(RW)
MC0_CTL_7e0 : .dword 0x0000000000000000
//00000000 rdlvl_gate_delay_2(RD) 00000000 rdlvl_gate_delay_1(RD) 00000000 rdlvl_gate_delay_0(RD) 00000000 rdlvl_gate_clk_adjust_8(RW) 00000000 rdlvl_gate_clk_adjust_7(RW) 00000000 rdlvl_gate_clk_adjust_6(RW) 00000000 rdlvl_gate_clk_adjust_5(RW) 00000000 rdlvl_gate_clk_adjust_4(RW)
MC0_CTL_7f0 : .dword 0x0000000000000000
//11111111 rdlvl_max_delay(RW) 00001000 rdlvl_gate_max_delay(RW) 00000000 rdlvl_gate_delay_8(RD) 00000000 rdlvl_gate_delay_7(RD) 00000000 rdlvl_gate_delay_6(RD) 00000000 rdlvl_gate_delay_5(RD) 00000000 rdlvl_gate_delay_4(RD) 00000000 rdlvl_gate_delay_3(RD)
MC0_CTL_800 : .dword 0x0000000000000000
//00000000 rdlvl_midpoint_delay_7(RD) 00000000 rdlvl_midpoint_delay_6(RD) 00000000 rdlvl_midpoint_delay_5(RD) 00000000 rdlvl_midpoint_delay_4(RD) 00000000 rdlvl_midpoint_delay_3(RD) 00000000 rdlvl_midpoint_delay_2(RD) 00000000 rdlvl_midpoint_delay_1(RD) 00000000 rdlvl_midpoint_delay_0(RD)
MC0_CTL_810 : .dword 0x0000000000000000
//00000000 rdlvl_offset_delay_6(RW) 00000000 rdlvl_offset_delay_5(RW) 00000000 rdlvl_offset_delay_4(RW) 00000000 rdlvl_offset_delay_3(RW) 00000000 rdlvl_offset_delay_2(RW) 00000000 rdlvl_offset_delay_1(RW) 00000000 rdlvl_offset_delay_0(RW) 00000000 rdlvl_midpoint_delay_8(RD)
MC0_CTL_820 : .dword 0x0000000000000000
//00000100 tdfi_wrlvl_resplat(RW) 00000000 tdfi_wrlvl_resp(RD) 00000000 tdfi_rdlvl_rr(RW) 00001100 tdfi_rdlvl_resplat(RW) 00000000 tdfi_rdlvl_resp(RD) 01000000 refresh_per_zq(RW) 00000000 rdlvl_offset_delay_8(RW) 00000000 rdlvl_offset_delay_7(RW)
//MC0_CTL_830 : .dword 0x000000000000050a
MC0_CTL_830 : .dword 0x202020202020050a
//MC0_CTL_830 : .dword 0x1c24241c1c1c050a
//MC0_CTL_830 : .dword 0x40444b474543050a
//00000000 wrlvl_delay_5(RD) 00000000 wrlvl_delay_4(RD) 00000000 wrlvl_delay_3(RD) 00000000 wrlvl_delay_2(RD) 00000000 wrlvl_delay_1(RD) 00000000 wrlvl_delay_0(RD) 00000010 tmod(RW) 00001010 tdfi_wrlvl_ww(RW)
//MC0_CTL_840 : .dword 0x0000640064000000
MC0_CTL_840 : .dword 0x0000640064002020
//MC0_CTL_840 : .dword 0x0000640064001c1c
//MC0_CTL_840 : .dword 0x0000640064003b3c
//00000000000000_0001100100 axi1_priority_relax(RW) 000000_0001100100 axi0_priority_relax(RW) 00000000 wrlvl_delay_8(RD) 00000000 wrlvl_delay_7(RD) 00000000 wrlvl_delay_6(RD)
MC0_CTL_850 : .dword 0x0000000000000064
//000000_0000000000 out_of_range_source_id(RD) 000000_0000000000 ecc_u_id(RD) 000000_0000000000 ecc_c_id(RD) 000000_0000000000 axi2_priority_relax(RW)
MC0_CTL_860 : .dword 0x0000000000000000
//0000_000000000000 zqini(RW) 0000_000000000000 zqcs(RW) 000000_0000000000 port_data_error_id(RD) 000000_0000000000 port_cmd_error_id(RD)
MC0_CTL_870 : .dword 0x0046004600460046
//0_000000000000010 emrs1_data_3(RW) 0_000000000000010 emrs1_data_2(RW) 0_000000000000010 emrs1_data_1(RW) 0_000000000000010 emrs1_data_0(RW)
MC0_CTL_880 : .dword 0x0000000000000000
//0_000000000000010 emrs3_data_3(RW) 0_000000000000010 emrs3_data_2(RW) 0_000000000000010 emrs3_data_1(RW) 0_000000000000010 emrs3_data_0(RW)
MC0_CTL_890 : .dword 0x0a620a620a620a62
//0_000010000010000 mrs_data_3(RW) 0_000010000010000 mrs_data_2(RW) 0_000010000010000 mrs_data_1(RW) 0_000010000010000 mrs_data_0(RW)
MC0_CTL_8a0 : .dword 0x00000000001c001c
//hXXXX lowpower_internal_cnt(RW) hXXXX lowpower_external_cnt(RW) hXXXX axi2_en_size_lt_width_instr(RW) hXXXX axi1_en_size_lt_width_instr(RW)
MC0_CTL_8b0 : .dword 0x0000000000000000
//hXXXX refresh_per_rdlvl(RW) hXXXX lowpower_self_refresh_cnt(RW) hXXXX lowpower_refresh_hold(RW) hXXXX lowpower_power_down_cnt(RW)
MC0_CTL_8c0 : .dword 0x0000000000000000
//hXXXX wrlvl_interval(RW) hXXXX tdfi_wrlvl_max(RW) hXXXX tdfi_rdlvl_max(RW) hXXXX refresh_per_rdlvl_gate(RW)
MC0_CTL_8d0 : .dword 0x002faf0800000000
//h00_XXXXXXXX cke_inactive(RW) 000000_000000000000000000 wrlvl_status(RD)
MC0_CTL_8e0 : .dword 0x0000000023c34600
//h00000000_XXXXXXXX trst_pwron(RW)
//MC0_CTL_8f0 : .dword 0x0000000020242080
//MC0_CTL_8f0 : .dword 0x000000002b352180
MC0_CTL_8f0 : .dword 0x0000000030303080
//hXXXXXXX 000_0 XXXXXXXX dll_ctrl_reg_2(RW)
MC0_CTL_900 : .dword 0x0000000000000000
//h000000 00_00 X XXXXXXXX rdlvl_error_status(RW)
MC0_CTL_910 : .dword 0x0000000000000000
//hXXXXXXXX XXXXXXXX rdlvl_gate_resp_mask[63:0](RW)
MC0_CTL_920 : .dword 0x0000000000000000
//h00000000000000_XX rdlvl_gate_resp_mask[71:64](RW)
MC0_CTL_930 : .dword 0x0000000000000000
//hXXXXXXXX XXXXXXXX rdlvl_resp_mask[63:0](RW)
MC0_CTL_940 : .dword 0x0007070000050500
//0000_0000 tdfi_rdlvl_en(RW) 00000_000 w2r_samecs_delay(RW) 00000_000 w2r_diffcs_delay(RW) 00000_000 lvl_status(RD) 0000000_0 rdlvl_edge(RW) 0000_0000 cksrx(RW) 0000_0000 cksre(RW) _00000000 rdlvl_resp_mask[71:64](RW)
MC0_CTL_950 : .dword 0x0000000000000800
//hXXXXX 00_00 XXXX mask_int[17:0](RW) hXXXX txpdll(RW) 0000_0000 tdfi_wrlvl_en(RW)
MC0_CTL_960 : .dword 0x0705000000000000
//000_00101 rdlat_adj(RW) 0000_0100 wrlat_adj(RW) 0000000_0 swlvl_start(WR) 0000000_0 swlvl_load(WR) 0000000_0 swlvl_exit(WR) 000000_000000000000000000 int_status(RD)
MC0_CTL_970 : .dword 0x000000000003e805
//h00000 000_0 XXXX int_ack[16:0](WR) hXXXX dll_rst_delay(RW) hXX dll_rst_adj_dly(RW)
ddr2_reg_data_mc1:
MC1_CTL_000 : .dword 0x0000010000000101
//000000000000000_0 concurrentap(RW) 0000000_1 bank_split_en(RW) 0000000_0 auto_refresh_mode(RW) 0000000_0 arefresh(WR) 0000000_0 ap(RW) 0000000_1 addr_cmp_en(RW) 0000000_1 active_aging(RW)
MC1_CTL_010 : .dword 0x0001000100010000
//0000000_0 fwc(WR) 0000000_0 fast_write(RW) 0000000_1 enable_quick_srefresh(RW) 0000000_1 eight_bank_mode(RW) 0000000_0 ecc_disable_w_uc_err(RW) 0000000_1 dqs_n_en(RW) 0000000_0 dll_bypass_mode(RW) 0000000_0 dlllockreg(RD)
MC1_CTL_020 : .dword 0x0100010101000000
//0000000_1 priority_en(RW) 0000000_0 power_down(RW) 0000000_1 placement_en(RW) 0000000_1 odt_add_turn_clk_en(RW) 0000000_0 no_cmd_init(RW) 0000000_0 intrptwritea(RW) 0000000_0 intrptreada(RW) 0000000_0 intrptapburst(RW)
MC1_CTL_030 : .dword 0x0001000001000000
//0000000_1 swap_port_rw_same_en(RW) 0000000_1 swap_en(RW) 0000000_0 start(RW) 0000000_0 srefresh(RW+) 0000000_1 rw_same_en(RW) 0000000_0 reg_dimm_enable(RW) 0000000_0 reduc(RW) 0000000_0 pwrup_srefresh_exit(RW)
MC1_CTL_040 : .dword 0x0102010200000100
//000000_01 rtt_0(RW) 000000_11 ctrl_raw(RW) 000000_01 axi0_w_priority(RW) 000000_01 axi0_r_priority(RW) 0000000_0 write_modereg(WR) 0000000_1 writeinterp(RW) 0000000_1 tref_enable(RW) 0000000_1 tras_lockout(RW)
MC1_CTL_050 : .dword 0x0200000004060100
//00000_000 q_fullness(RW) 00000_000 port_data_error_type(RD) 000_00000 out_of_range_type(RD) 00000_000 max_cs_reg(RD) 00000_100 column_size(RW) 0000_0101 caslat(RW) 00000_010 addr_pins(RW) 00000000
MC1_CTL_060 : .dword 0x0a05030603030003
//0000_1010 aprebit(RW) 0000_0101 wrlat(RW) 0000_0100 twtr(RW) 000_00110 twr_int(RW) 00000_011 trtp(RW) 00000_100 trrd(RW) 0000000000000_011 tcke(RW)
MC1_CTL_070 : .dword 0x0000020000030c0c
//0000_0000 max_row_reg(RD) 0000_0000 max_col_reg(RD) 0000_0000 initaref(RW) 00000000000000000000_1111 cs_map(RW) 000_01010 caslat_lin_gate(RW) 000_01010 caslat_lin(RW)
MC1_CTL_080 : .dword 0x0804020108040201
//0000_0001 odt_wr_map_cs3(RW) 0000_0010 odt_wr_map_cs2(RW) 0000_0100 odt_wr_map_cs1(RW) 0000_1000 odt_wr_map_cs0(RW) 0000_0001 odt_rd_map_cs3(RW) 0000_0010 odt_rd_map_cs2(RW) 0000_0100 odt_rd_map_cs1(RW) 0000_1000 odt_rd_map_cs0(RW)
MC1_CTL_090 : .dword 0x0000070d00000000
//000_00000 ocd_adjust_pup_cs_0(RW) 000_00000 ocd_adjust_pdn_cs_0(RW) 0000_0101 trp(RW) 000_01011 tdal(RW) 000000000000_0000 port_cmd_error_type(RD) 0000000000000000
MC1_CTL_0a0 : .dword 0x0000003f3f18050e
//00000000000000000000000000_111111 command_age_count(RW) 00_111111 age_count(RW) 000_10100 trc(RW) 000_00110 tmrd(RW) 000_10010 tfaw(RW)
MC1_CTL_0b0 : .dword 0x0000000000000000
MC1_CTL_0c0 : .dword 0x0000330612000000
//000000000000000000101100 trfc(RW) 00000101 trcd_int(RW) 00001111 tras_min(RW) 00000000 out_of_range_length(RD) 00000000 ecc_u_synd(RD) 00000000 ecc_c_synd(RD)
MC1_CTL_0d0 : .dword 0x0000000000000000
MC1_CTL_0e0 : .dword 0x0000000000000000
MC1_CTL_0f0 : .dword 0x0000000000000000
//Bit 21:16 dll_lock(RD)
MC1_CTL_100 : .dword 0x0000000000000000
//MC1_CTL_110 : .dword 0x00000000000002e0 #100M+
MC1_CTL_110 : .dword 0x00000000000005e0 #200M+
//MC1_CTL_110 : .dword 0x0000000000000900 #300M+
//MC1_CTL_110 : .dword 0x0000000000000c00 #400M
//0_000000000000000 emrs2_data_1(RW) 0_000000000000000 emrs2_data_0(RW) 000000000000000000_00110000101101 tref(RW)
MC1_CTL_120 : .dword 0xffff000000000000
//0000000000011100 axi0_en_size_lt_width_instr(RW) 00000000000000000_000000000000000 emrs2_data_3(RW) 0_000000000000000 emrs2_data_2(RW)
//MC1_CTL_130 : .dword 0x1b20000200c800c8 #100M+
MC1_CTL_130 : .dword 0x3680000200c800c8 #200M+
//MC1_CTL_130 : .dword 0x51d0000200c800c8 #300M+
//MC1_CTL_130 : .dword 0x6d30000200c800c8 #400M
//0110110101010110 tras_max(RW) 0000000000000011 tpdex(RW) 0000001000000000 tdll(RW) 0000000000000000 tcpd(RW)
MC1_CTL_140 : .dword 0x0000204000c80037
//0000000000000000 xor_check_bits(RW) 0000000000000000 version(RD) 0000001000000000 txsr(RW) 0000000000110000 txsnr(RW)
MC1_CTL_150 : .dword 0x0000000000027100
//000_0000000000000000000000000000000000000 ecc_c_addr(RD) 000000000000000000011011 tinit(RW)
MC1_CTL_160 : .dword 0x0000000000000000
//000000000000000000000000000_0000000000000000000000000000000000000 ecc_u_addr(RD)
MC1_CTL_170 : .dword 0x0000000000000000
//000000000000000000000000000_0000000000000000000000000000000000000 out_of_range_addr(RD)
MC1_CTL_180 : .dword 0x0000000000000000
//000000000000000000000000000_0000000000000000000000000000000000000 port_cmd_error_addr(RD)
MC1_CTL_190 : .dword 0x0000000000000000
//0000000000000000000000000000000000000000000000000000000000000000 ecc_c_data(RD)
MC1_CTL_1a0 : .dword 0x0000000000000000
//0000000000000000000000000000000000000000000000000000000000000000 ecc_u_data(RD)
MC1_CTL_1b0 : .dword 0x0000000000000000
//0000000000000000000000000000000000000000000000000000000000000_000 cke_delay(RW)
MC1_CTL_1c0 : .dword 0x0000000000000000
MC1_CTL_1d0 : .dword 0x0200070000000001
//0000_0010 tdfi_phy_wrlat_base(RW) 0000_0000 tdfi_phy_wrlat(RD) 000_00111 tdfi_phy_rdlat(RW) 0000_0000 tdfi_ctrlupd_min(RD) 000000000000_0000 dram_clk_disable(RW) 0000000_1 odt_alt_en(RW) 0000000_1 drive_dq_dqs(RW)
MC1_CTL_1e0 : .dword 0x0000000000000200
//00_00000000000000 tdfi_phyupd_type0(RD) 00_00000000000000 tdfi_phyupd_resp(RD) 00_00000000000000 tdfi_ctrlupd_max(RD) 000_00000 tdfi_rddata_en_base(RW) 000_00000 tdfi_rddata_en(RD)
MC1_CTL_1f0 : .dword 0x0018208000000000
MC1_CTL_200 : .dword 0x0018208000182080
MC1_CTL_210 : .dword 0x0018208000182080
MC1_CTL_220 : .dword 0x0018208000182080
MC1_CTL_230 : .dword 0x0018208000182080
MC1_CTL_240 : .dword 0x0000200000002000
MC1_CTL_250 : .dword 0x0000200000002000
MC1_CTL_260 : .dword 0x0000200000002000
MC1_CTL_270 : .dword 0x0000200000002000
MC1_CTL_280 : .dword 0x0000000000002000
MC1_CTL_290 : .dword 0x0000000000000000
//hXXXXXXX 00_00 dll_obs_reg_0_2(RW) hXXXXXXX 00_00 dll_obs_reg_0_1(RW)
MC1_CTL_2a0 : .dword 0x0000000000000000
//hXXXXXXX 00_00 dll_obs_reg_0_4(RW) hXXXXXXX 00_00 dll_obs_reg_0_3(RW)
MC1_CTL_2b0 : .dword 0x0000000000000000
//hXXXXXXX 00_00 dll_obs_reg_0_6(RW) hXXXXXXX 00_00 dll_obs_reg_0_5(RW)
MC1_CTL_2c0 : .dword 0x0000000000000000
//hXXXXXXX 00_00 dll_obs_reg_0_8(RW) hXXXXXXX 00_00 dll_obs_reg_0_7(RW)
MC1_CTL_2d0 : .dword 0x1400483303c009b4
//11110100000000000011101100100111 phy_ctrl_reg_0_0(RD) 000000_00000000000000000110011101 pad_ctrl_reg_0(RW)
MC1_CTL_2e0 : .dword 0x1400483314004833
MC1_CTL_2f0 : .dword 0x1400483314004833
MC1_CTL_300 : .dword 0x1400483314004833
MC1_CTL_310 : .dword 0x1400483314004833
MC1_CTL_320 : .dword 0x26c0000126c00001
MC1_CTL_330 : .dword 0x26c0000126c00001
MC1_CTL_340 : .dword 0x26c0000126c00001
MC1_CTL_350 : .dword 0x26c0000126c00001
MC1_CTL_360 : .dword 0x0800e00026c00001
//00000000000000001100000000000101 phy_ctrl_reg_2(RW) 00000111110000000000001100000001 phy_ctrl_reg_1_8(RD)
//--------------
MC1_CTL_370 : .dword 0x0000000000000000
MC1_CTL_380 : .dword 0x0000000000000000
MC1_CTL_390 : .dword 0x0000000000000000
MC1_CTL_3a0 : .dword 0x0000000000000000
MC1_CTL_3b0 : .dword 0x0000000000000000
MC1_CTL_3c0 : .dword 0x0000000000000000
MC1_CTL_3d0 : .dword 0x0000000000000000
MC1_CTL_3e0 : .dword 0x0000000000000000
MC1_CTL_3f0 : .dword 0x0000000000000000
MC1_CTL_400 : .dword 0x0000000000000000
MC1_CTL_410 : .dword 0x0000000000000000
MC1_CTL_420 : .dword 0x0000000000000000
MC1_CTL_430 : .dword 0x0000000000000000
MC1_CTL_440 : .dword 0x0000000000000000
MC1_CTL_450 : .dword 0x0000000000000000
MC1_CTL_460 : .dword 0x0000000000000000
MC1_CTL_470 : .dword 0x0000000000000000
MC1_CTL_480 : .dword 0x0000000000000000
MC1_CTL_490 : .dword 0x0000000000000000
MC1_CTL_4a0 : .dword 0x0000000000000000
MC1_CTL_4b0 : .dword 0x0000000000000000
MC1_CTL_4c0 : .dword 0x0000000000000000
MC1_CTL_4d0 : .dword 0x0000000000000000
MC1_CTL_4e0 : .dword 0x0000000000000000
MC1_CTL_4f0 : .dword 0x0000000000000000
MC1_CTL_500 : .dword 0x0000000000000000
MC1_CTL_510 : .dword 0x0000000000000000
MC1_CTL_520 : .dword 0x0000000000000000
MC1_CTL_530 : .dword 0x0000000000000000
MC1_CTL_540 : .dword 0x0000000000000000
MC1_CTL_550 : .dword 0x0000000000000000
MC1_CTL_560 : .dword 0x0000000000000000
MC1_CTL_570 : .dword 0x0000000000000000
MC1_CTL_580 : .dword 0x0000000000000000
MC1_CTL_590 : .dword 0x0000000000000000
MC1_CTL_5a0 : .dword 0x0000000000000000
MC1_CTL_5b0 : .dword 0x0000000000000000
MC1_CTL_5c0 : .dword 0x0000000000000000
MC1_CTL_5d0 : .dword 0x0000000000000000
MC1_CTL_5e0 : .dword 0x0000000000000000
MC1_CTL_5f0 : .dword 0x0000000000000000
MC1_CTL_600 : .dword 0x0000000000000000
MC1_CTL_610 : .dword 0x0000000000000000
MC1_CTL_620 : .dword 0x0000000000000000
MC1_CTL_630 : .dword 0x0000000000000000
MC1_CTL_640 : .dword 0x0000000000000000
MC1_CTL_650 : .dword 0x0000000000000000
MC1_CTL_660 : .dword 0x0000000000000000
MC1_CTL_670 : .dword 0x0000000000000000
MC1_CTL_680 : .dword 0x0000000000000000
MC1_CTL_690 : .dword 0x0000000000000000
MC1_CTL_6a0 : .dword 0x0000000000000000
MC1_CTL_6b0 : .dword 0x0000000000000000
MC1_CTL_6c0 : .dword 0x0000000000000000
MC1_CTL_6d0 : .dword 0x0000000000000000
MC1_CTL_6e0 : .dword 0x0000000000000000
MC1_CTL_6f0 : .dword 0x0000000000000000
MC1_CTL_700 : .dword 0x0000000000000000
//-------------
MC1_CTL_710 : .dword 0x0000000000000000
//bit 48 en_wr_leveling(RW)
MC1_CTL_720 : .dword 0x0000000000000000
//0000000_0 rdlvl_gate_req(WR) 0000000_0 rdlvl_gate_preamble_check_en(RW) 0000000_0 rdlvl_gate_en(RW) 0000000_0 rdlvl_en(RW) 0000000_0 rdlvl_begin_delay_en(RW) 00000000 00000000 0000000_0 swlvl_op_done(RD)
MC1_CTL_730 : .dword 0x0000000000000000
//0000000_0 rdlvl_offset_dir_7(RW) 0000000_0 rdlvl_offset_dir_6(RW) 0000000_0 rdlvl_offset_dir_5(RW)0000000_0 rdlvl_offset_dir_4(RW) 0000000_0 rdlvl_offset_dir_3(RW) 0000000_0 rdlvl_offset_dir_2(RW) 0000000_0 rdlvl_offset_dir_1(RW) 0000000_0 rdlvl_offset_dir_0(RW)
MC1_CTL_740 : .dword 0x0100000000000000
//000000_00 axi1_port_ordering(RW) 000000_00 axi0_port_ordering(RW) 0000000_0 wrlvl_req(WR) 0000000_0 wrlvl_interval_ct_en(RW) 0000000_0 weight_round_robin_weight_sharing(RW) 0000000_0 weight_round_robin_latency_control 0000000_0(RW) rdlvl_req 0000000_0(WR) rdlvl_offset_dir_8(RW)
MC1_CTL_750 : .dword 0x0000000101020101
//000000_01 wrlvl_cs(RW) 000000_00 sw_leveling_mode(RW) 000000_00 rdlvl_cs(RW) 000000_01 axi2_w_priority(RW) 000000_01 axi2_r_priority(RW) 000000_10 axi2_port_ordering(RW) 000000_01 axi1_w_priority(RW) 000000_01 axi1_r_priority(RW)
MC1_CTL_760 : .dword 0x0303030000020000
//0000_0011 axi0_priority2_relative_priority(RW) 0000_0011 axi0_priority1_relative_priority(RW) 0000_0011 axi0_priority0_relative_priority(RW) 0000_0000 address_mirroring(RW) 00000_000 tdfi_dram_clk_disable(RW) 00000_010 bstlen(RW) 000000_00 zq_req(WR) 000000_01 zq_on_sref_exit(RW)
MC1_CTL_770 : .dword 0x0101010202020203
//0000_0001 axi2_priority2_relative_priority(RW) 0000_0001 axi2_priority1_relative_priority(RW) 0000_0001 axi2_priority0_relative_priority(RW) 0000_0010 axi1_priority3_relative_priority(RW) 0000_0010 axi1_priority2_relative_priority(RW) 0000_0010 axi1_priority1_relative_priority(RW) 0000_0010 axi1_priority0_relative_priority(RW) 0000_0011 axi0_priority3_relative_priority(RW)
MC1_CTL_780 : .dword 0x0102000000040001
//0000_0001 tdfi_dram_clk_enable(RW) 0000_0010 tdfi_ctrl_delay(RW) 0000_0010 rdlvl_gate_dq_zero_count(RW) 0000_0100 rdlvl_dq_zero_count(RW) 0000_0000 lowpower_refresh_enable(RW) 0000_0110 dram_class(RW) 0000_1100 burst_on_fly_bit(RW) 0000_0001 axi2_priority3_relative_priority(RW)
MC1_CTL_790 : .dword 0x0000000000000000
//00_101000 wlmrd(RW) 00_011001 wldqsen(RW) 000_00000 lowpower_control(RW) 000_00000 lowpower_auto_enable(RW) 0000_1111 zqcs_chip(RW) 0000_0000 wrr_param_value_err(RD) 0000_0011 tdfi_wrlvl_dll(RW) 0000_0011 tdfi_rdlvl_dll(RW)
MC1_CTL_7a0 : .dword 0x0000000000000000
//_00000000 swlvl_resp_6(RW) _00000000 swlvl_resp_5(RW) _00000000 swlvl_resp_4 _00000000 swlvl_resp_3(RW) _00000000 swlvl_resp_2(RW) _00000000 swlvl_resp_1(RW) _00000000 swlvl_resp_0(RW) _00000000 dfi_wrlvl_max_delay(RW)
MC1_CTL_7b0 : .dword 0x0000000000000000
//_00000000 rdlvl_begin_delay_5(RW) _00000000 rdlvl_begin_delay_4(RW) _00000000 rdlvl_begin_delay_3(RW) _00000000 rdlvl_begin_delay_2(RW) _00000000 rdlvl_begin_delay_1(RW) _00000000 rdlvl_begin_delay_0(RW) _00000000 swlvl_resp_8(RW) _00000000 swlvl_resp_7(RW)
MC1_CTL_7c0 : .dword 0x0000000000000000
//_00000000 rdlvl_end_delay_4(RW) _00000000 rdlvl_end_delay_3(RW) _00000000 rdlvl_end_delay_2(RW) _00000000 rdlvl_end_delay_1(RW) _00000000 rdlvl_end_delay_0(RW) _00000000 rdlvl_begin_delay_8(RW) _00000000 rdlvl_begin_delay_7(RW) _00000000 rdlvl_begin_delay_6(RW)
MC1_CTL_7d0 : .dword 0x0000000000000000
//_00000000 rdlvl_gate_clk_adjust_3(RW) _00000000 rdlvl_gate_clk_adjust_2(RW) _00000000 rdlvl_gate_clk_adjust_1(RW) _00000000 rdlvl_gate_clk_adjust_0(RW) _00000000 rdlvl_end_delay_8(RW) _00000000 rdlvl_end_delay_7(RW) _00000000 rdlvl_end_delay_6(RW) 00000000 rdlvl_end_delay_5(RW)
MC1_CTL_7e0 : .dword 0x0000000000000000
//00000000 rdlvl_gate_delay_2(RD) 00000000 rdlvl_gate_delay_1(RD) 00000000 rdlvl_gate_delay_0(RD) 00000000 rdlvl_gate_clk_adjust_8(RW) 00000000 rdlvl_gate_clk_adjust_7(RW) 00000000 rdlvl_gate_clk_adjust_6(RW) 00000000 rdlvl_gate_clk_adjust_5(RW) 00000000 rdlvl_gate_clk_adjust_4(RW)
MC1_CTL_7f0 : .dword 0x0000000000000000
//11111111 rdlvl_max_delay(RW) 00001000 rdlvl_gate_max_delay(RW) 00000000 rdlvl_gate_delay_8(RD) 00000000 rdlvl_gate_delay_7(RD) 00000000 rdlvl_gate_delay_6(RD) 00000000 rdlvl_gate_delay_5(RD) 00000000 rdlvl_gate_delay_4(RD) 00000000 rdlvl_gate_delay_3(RD)
MC1_CTL_800 : .dword 0x0000000000000000
//00000000 rdlvl_midpoint_delay_7(RD) 00000000 rdlvl_midpoint_delay_6(RD) 00000000 rdlvl_midpoint_delay_5(RD) 00000000 rdlvl_midpoint_delay_4(RD) 00000000 rdlvl_midpoint_delay_3(RD) 00000000 rdlvl_midpoint_delay_2(RD) 00000000 rdlvl_midpoint_delay_1(RD) 00000000 rdlvl_midpoint_delay_0(RD)
MC1_CTL_810 : .dword 0x0000000000000000
//00000000 rdlvl_offset_delay_6(RW) 00000000 rdlvl_offset_delay_5(RW) 00000000 rdlvl_offset_delay_4(RW) 00000000 rdlvl_offset_delay_3(RW) 00000000 rdlvl_offset_delay_2(RW) 00000000 rdlvl_offset_delay_1(RW) 00000000 rdlvl_offset_delay_0(RW) 00000000 rdlvl_midpoint_delay_8(RD)
MC1_CTL_820 : .dword 0x0000000000000000
//00000100 tdfi_wrlvl_resplat(RW) 00000000 tdfi_wrlvl_resp(RD) 00000000 tdfi_rdlvl_rr(RW) 00001100 tdfi_rdlvl_resplat(RW) 00000000 tdfi_rdlvl_resp(RD) 01000000 refresh_per_zq(RW) 00000000 rdlvl_offset_delay_8(RW) 00000000 rdlvl_offset_delay_7(RW)
//MC1_CTL_830 : .dword 0x202020202020050a
MC1_CTL_830 : .dword 0x1c24241c1c1c050a
//MC1_CTL_830 : .dword 0x000000000000050a
//MC1_CTL_830 : .dword 0x40444b474543050a
//00000000 wrlvl_delay_5(RD) 00000000 wrlvl_delay_4(RD) 00000000 wrlvl_delay_3(RD) 00000000 wrlvl_delay_2(RD) 00000000 wrlvl_delay_1(RD) 00000000 wrlvl_delay_0(RD) 00000010 tmod(RW) 00001010 tdfi_wrlvl_ww(RW)
//MC1_CTL_840 : .dword 0x0000640064002000
//MC1_CTL_840 : .dword 0x0000640064002020
MC1_CTL_840 : .dword 0x0000640064001c1c
//MC1_CTL_840 : .dword 0x0000640064003b3c
//00000000000000_0001100100 axi1_priority_relax(RW) 000000_0001100100 axi0_priority_relax(RW) 00000000 wrlvl_delay_8(RD) 00000000 wrlvl_delay_7(RD) 00000000 wrlvl_delay_6(RD)
MC1_CTL_850 : .dword 0x0000000000000064
//000000_0000000000 out_of_range_source_id(RD) 000000_0000000000 ecc_u_id(RD) 000000_0000000000 ecc_c_id(RD) 000000_0000000000 axi2_priority_relax(RW)
MC1_CTL_860 : .dword 0x0000000000000000
//0000_000000000000 zqini(RW) 0000_000000000000 zqcs(RW) 000000_0000000000 port_data_error_id(RD) 000000_0000000000 port_cmd_error_id(RD)
MC1_CTL_870 : .dword 0x0046004600460046
//0_000000000000010 emrs1_data_3(RW) 0_000000000000010 emrs1_data_2(RW) 0_000000000000010 emrs1_data_1(RW) 0_000000000000010 emrs1_data_0(RW)
MC1_CTL_880 : .dword 0x0000000000000000
//0_000000000000010 emrs3_data_3(RW) 0_000000000000010 emrs3_data_2(RW) 0_000000000000010 emrs3_data_1(RW) 0_000000000000010 emrs3_data_0(RW)
MC1_CTL_890 : .dword 0x0a620a620a620a62
//0_000010000010000 mrs_data_3(RW) 0_000010000010000 mrs_data_2(RW) 0_000010000010000 mrs_data_1(RW) 0_000010000010000 mrs_data_0(RW)
MC1_CTL_8a0 : .dword 0x00000000001c001c
//hXXXX lowpower_internal_cnt(RW) hXXXX lowpower_external_cnt(RW) hXXXX axi2_en_size_lt_width_instr(RW) hXXXX axi1_en_size_lt_width_instr(RW)
MC1_CTL_8b0 : .dword 0x0000000000000000
//hXXXX refresh_per_rdlvl(RW) hXXXX lowpower_self_refresh_cnt(RW) hXXXX lowpower_refresh_hold(RW) hXXXX lowpower_power_down_cnt(RW)
MC1_CTL_8c0 : .dword 0x0000000000000000
//hXXXX wrlvl_interval(RW) hXXXX tdfi_wrlvl_max(RW) hXXXX tdfi_rdlvl_max(RW) hXXXX refresh_per_rdlvl_gate(RW)
MC1_CTL_8d0 : .dword 0x002faf0800000000
//h00_XXXXXXXX cke_inactive(RW) 000000_000000000000000000 wrlvl_status(RD)
MC1_CTL_8e0 : .dword 0x0000000023c34600
//h00000000_XXXXXXXX trst_pwron(RW)
//MC1_CTL_8f0 : .dword 0x0000000020242080
//MC1_CTL_8f0 : .dword 0x000000002b352180
MC1_CTL_8f0 : .dword 0x0000000030303080
//hXXXXXXX 000_0 XXXXXXXX dll_ctrl_reg_2(RW)
MC1_CTL_900 : .dword 0x0000000000000000
//h000000 00_00 X XXXXXXXX rdlvl_error_status(RW)
MC1_CTL_910 : .dword 0x0000000000000000
//hXXXXXXXX XXXXXXXX rdlvl_gate_resp_mask[63:0](RW)
MC1_CTL_920 : .dword 0x0000000000000000
//h00000000000000_XX rdlvl_gate_resp_mask[71:64](RW)
MC1_CTL_930 : .dword 0x0000000000000000
//hXXXXXXXX XXXXXXXX rdlvl_resp_mask[63:0](RW)
MC1_CTL_940 : .dword 0x0007070000050500
//0000_0000 tdfi_rdlvl_en(RW) 00000_000 w2r_samecs_delay(RW) 00000_000 w2r_diffcs_delay(RW) 00000_000 lvl_status(RD) 0000000_0 rdlvl_edge(RW) 0000_0000 cksrx(RW) 0000_0000 cksre(RW) _00000000 rdlvl_resp_mask[71:64](RW)
MC1_CTL_950 : .dword 0x0000000000000800
//hXXXXX 00_00 XXXX mask_int[17:0](RW) hXXXX txpdll(RW) 0000_0000 tdfi_wrlvl_en(RW)
MC1_CTL_960 : .dword 0x0705000000000000
//000_00101 rdlat_adj(RW) 0000_0100 wrlat_adj(RW) 0000000_0 swlvl_start(WR) 0000000_0 swlvl_load(WR) 0000000_0 swlvl_exit(WR) 000000_000000000000000000 int_status(RD)
MC1_CTL_970 : .dword 0x000000000003e805
//h00000 000_0 XXXX int_ack[16:0](WR) hXXXX dll_rst_delay(RW) hXX dll_rst_adj_dly(RW)
//param for RDIMM--------------------------------
ddr2_RDIMM_reg_data:
MC0_RDIMM_CTL_000 : .dword 0x0000010000000101
//000000000000000_0 concurrentap(RW) 0000000_1 bank_split_en(RW) 0000000_0 auto_refresh_mode(RW) 0000000_0 arefresh(WR) 0000000_0 ap(RW) 0000000_1 addr_cmp_en(RW) 0000000_1 active_aging(RW)
MC0_RDIMM_CTL_010 : .dword 0x0001000100010000
//0000000_0 fwc(WR) 0000000_0 fast_write(RW) 0000000_1 enable_quick_srefresh(RW) 0000000_1 eight_bank_mode(RW) 0000000_0 ecc_disable_w_uc_err(RW) 0000000_1 dqs_n_en(RW) 0000000_0 dll_bypass_mode(RW) 0000000_0 dlllockreg(RD)
MC0_RDIMM_CTL_020 : .dword 0x0100010101000000
//0000000_1 priority_en(RW) 0000000_0 power_down(RW) 0000000_1 placement_en(RW) 0000000_1 odt_add_turn_clk_en(RW) 0000000_0 no_cmd_init(RW) 0000000_0 intrptwritea(RW) 0000000_0 intrptreada(RW) 0000000_0 intrptapburst(RW)
MC0_RDIMM_CTL_030 : .dword 0x0001000001010000
//0000000_1 swap_port_rw_same_en(RW) 0000000_1 swap_en(RW) 0000000_0 start(RW) 0000000_0 srefresh(RW+) 0000000_1 rw_same_en(RW) 0000000_0 reg_dimm_enable(RW) 0000000_0 reduc(RW) 0000000_0 pwrup_srefresh_exit(RW)
MC0_RDIMM_CTL_040 : .dword 0x0102010200000100
//000000_01 rtt_0(RW) 000000_11 ctrl_raw(RW) 000000_01 axi0_w_priority(RW) 000000_01 axi0_r_priority(RW) 0000000_0 write_modereg(WR) 0000000_1 writeinterp(RW) 0000000_1 tref_enable(RW) 0000000_1 tras_lockout(RW)
MC0_RDIMM_CTL_050 : .dword 0x0200000004060100
//00000_000 q_fullness(RW) 00000_000 port_data_error_type(RD) 000_00000 out_of_range_type(RD) 00000_000 max_cs_reg(RD) 00000_100 column_size(RW) 0000_0101 caslat(RW) 00000_010 addr_pins(RW) 00000000
MC0_RDIMM_CTL_060 : .dword 0x0a05030603030003
//0000_1010 aprebit(RW) 0000_0101 wrlat(RW) 0000_0100 twtr(RW) 000_00110 twr_int(RW) 00000_011 trtp(RW) 00000_100 trrd(RW) 0000000000000_011 tcke(RW)
MC0_RDIMM_CTL_070 : .dword 0x00000200000f0c0c
//0000_0000 max_row_reg(RD) 0000_0000 max_col_reg(RD) 0000_0000 initaref(RW) 00000000000000000000_1111 cs_map(RW) 000_01010 caslat_lin_gate(RW) 000_01010 caslat_lin(RW)
MC0_RDIMM_CTL_080 : .dword 0x0804020108040201
//0000_0001 odt_wr_map_cs3(RW) 0000_0010 odt_wr_map_cs2(RW) 0000_0100 odt_wr_map_cs1(RW) 0000_1000 odt_wr_map_cs0(RW) 0000_0001 odt_rd_map_cs3(RW) 0000_0010 odt_rd_map_cs2(RW) 0000_0100 odt_rd_map_cs1(RW) 0000_1000 odt_rd_map_cs0(RW)
MC0_RDIMM_CTL_090 : .dword 0x0000070d00000000
//000_00000 ocd_adjust_pup_cs_0(RW) 000_00000 ocd_adjust_pdn_cs_0(RW) 0000_0101 trp(RW) 000_01011 tdal(RW) 000000000000_0000 port_cmd_error_type(RD) 0000000000000000
MC0_RDIMM_CTL_0a0 : .dword 0x0000003f3f18050e
//00000000000000000000000000_111111 command_age_count(RW) 00_111111 age_count(RW) 000_10100 trc(RW) 000_00110 tmrd(RW) 000_10010 tfaw(RW)
MC0_RDIMM_CTL_0b0 : .dword 0x0000000000000000
MC0_RDIMM_CTL_0c0 : .dword 0x0000330612000000
//000000000000000000101100 trfc(RW) 00000101 trcd_int(RW) 00001111 tras_min(RW) 00000000 out_of_range_length(RD) 00000000 ecc_u_synd(RD) 00000000 ecc_c_synd(RD)
MC0_RDIMM_CTL_0d0 : .dword 0x0000000000000000
MC0_RDIMM_CTL_0e0 : .dword 0x0000000000000000
MC0_RDIMM_CTL_0f0 : .dword 0x0000000000000000
//Bit 21:16 dll_lock(RD)
MC0_RDIMM_CTL_100 : .dword 0x0000000000000000
//MC0_RDIMM_CTL_110 : .dword 0x00000000000002e0 #100M+
//MC0_RDIMM_CTL_110 : .dword 0x00000000000005e0 #200M+
MC0_RDIMM_CTL_110 : .dword 0x0000000000000900 #300M+
//MC0_RDIMM_CTL_110 : .dword 0x0000000000000c00 #400M
//0_000000000000000 emrs2_data_1(RW) 0_000000000000000 emrs2_data_0(RW) 000000000000000000_00110000101101 tref(RW)
MC0_RDIMM_CTL_120 : .dword 0xffff000000000000
//0000000000011100 axi0_en_size_lt_width_instr(RW) 00000000000000000_000000000000000 emrs2_data_3(RW) 0_000000000000000 emrs2_data_2(RW)
//MC0_RDIMM_CTL_130 : .dword 0x1b20000200c800c8 #100M+
//MC0_RDIMM_CTL_130 : .dword 0x3680000200c800c8 #200M+
MC0_RDIMM_CTL_130 : .dword 0x51d0000200c800c8 #300M+
//MC0_RDIMM_CTL_130 : .dword 0x6d30000200c800c8 #400M
//0110110101010110 tras_max(RW) 0000000000000011 tpdex(RW) 0000001000000000 tdll(RW) 0000000000000000 tcpd(RW)
MC0_RDIMM_CTL_140 : .dword 0x0000204000c80037
//0000000000000000 xor_check_bits(RW) 0000000000000000 version(RD) 0000001000000000 txsr(RW) 0000000000110000 txsnr(RW)
MC0_RDIMM_CTL_150 : .dword 0x0000000000027100
//000_0000000000000000000000000000000000000 ecc_c_addr(RD) 000000000000000000011011 tinit(RW)
MC0_RDIMM_CTL_160 : .dword 0x0000000000000000
//000000000000000000000000000_0000000000000000000000000000000000000 ecc_u_addr(RD)
MC0_RDIMM_CTL_170 : .dword 0x0000000000000000
//000000000000000000000000000_0000000000000000000000000000000000000 out_of_range_addr(RD)
MC0_RDIMM_CTL_180 : .dword 0x0000000000000000
//000000000000000000000000000_0000000000000000000000000000000000000 port_cmd_error_addr(RD)
MC0_RDIMM_CTL_190 : .dword 0x0000000000000000
//0000000000000000000000000000000000000000000000000000000000000000 ecc_c_data(RD)
MC0_RDIMM_CTL_1a0 : .dword 0x0000000000000000
//0000000000000000000000000000000000000000000000000000000000000000 ecc_u_data(RD)
MC0_RDIMM_CTL_1b0 : .dword 0x0000000000000000
//0000000000000000000000000000000000000000000000000000000000000_000 cke_delay(RW)
MC0_RDIMM_CTL_1c0 : .dword 0x0000000000000000
MC0_RDIMM_CTL_1d0 : .dword 0x0200070000000001
//0000_0010 tdfi_phy_wrlat_base(RW) 0000_0000 tdfi_phy_wrlat(RD) 000_00111 tdfi_phy_rdlat(RW) 0000_0000 tdfi_ctrlupd_min(RD) 000000000000_0000 dram_clk_disable(RW) 0000000_1 odt_alt_en(RW) 0000000_1 drive_dq_dqs(RW)
MC0_RDIMM_CTL_1e0 : .dword 0x0000000000000200
//00_00000000000000 tdfi_phyupd_type0(RD) 00_00000000000000 tdfi_phyupd_resp(RD) 00_00000000000000 tdfi_ctrlupd_max(RD) 000_00000 tdfi_rddata_en_base(RW) 000_00000 tdfi_rddata_en(RD)
//wr-dq: pass range: 08~1c
MC0_RDIMM_CTL_1f0 : .dword 0x0012208000000000
MC0_RDIMM_CTL_200 : .dword 0x0012208000122080
MC0_RDIMM_CTL_210 : .dword 0x0012208000122080
MC0_RDIMM_CTL_220 : .dword 0x0012208000122080
MC0_RDIMM_CTL_230 : .dword 0x0012208000122080
MC0_RDIMM_CTL_240 : .dword 0x0000200000002000
MC0_RDIMM_CTL_250 : .dword 0x0000200000002000
MC0_RDIMM_CTL_260 : .dword 0x0000200000002000
MC0_RDIMM_CTL_270 : .dword 0x0000200000002000
MC0_RDIMM_CTL_280 : .dword 0x0000000000002000
MC0_RDIMM_CTL_290 : .dword 0x0000000000000000
//hXXXXXXX 00_00 dll_obs_reg_0_2(RW) hXXXXXXX 00_00 dll_obs_reg_0_1(RW)
MC0_RDIMM_CTL_2a0 : .dword 0x0000000000000000
//hXXXXXXX 00_00 dll_obs_reg_0_4(RW) hXXXXXXX 00_00 dll_obs_reg_0_3(RW)
MC0_RDIMM_CTL_2b0 : .dword 0x0000000000000000
//hXXXXXXX 00_00 dll_obs_reg_0_6(RW) hXXXXXXX 00_00 dll_obs_reg_0_5(RW)
MC0_RDIMM_CTL_2c0 : .dword 0x0000000000000000
//hXXXXXXX 00_00 dll_obs_reg_0_8(RW) hXXXXXXX 00_00 dll_obs_reg_0_7(RW)
MC0_RDIMM_CTL_2d0 : .dword 0x1300483303c009b4
MC0_RDIMM_CTL_2e0 : .dword 0x1300483313004833
MC0_RDIMM_CTL_2f0 : .dword 0x1300483313004833
MC0_RDIMM_CTL_300 : .dword 0x1300483313004833
MC0_RDIMM_CTL_310 : .dword 0x1300483313004833
MC0_RDIMM_CTL_320 : .dword 0x26c0000126c00001
MC0_RDIMM_CTL_330 : .dword 0x26c0000126c00001
MC0_RDIMM_CTL_340 : .dword 0x26c0000126c00001
MC0_RDIMM_CTL_350 : .dword 0x26c0000126c00001
MC0_RDIMM_CTL_360 : .dword 0x0800c00026c00001
//00000000000000001100000000000101 phy_ctrl_reg_2(RW) 00000111110000000000001100000001 phy_ctrl_reg_1_8(RD)
//--------------
MC0_RDIMM_CTL_370 : .dword 0x0000000000000000
MC0_RDIMM_CTL_380 : .dword 0x0000000000000000
MC0_RDIMM_CTL_390 : .dword 0x0000000000000000
MC0_RDIMM_CTL_3a0 : .dword 0x0000000000000000
MC0_RDIMM_CTL_3b0 : .dword 0x0000000000000000
MC0_RDIMM_CTL_3c0 : .dword 0x0000000000000000
MC0_RDIMM_CTL_3d0 : .dword 0x0000000000000000
MC0_RDIMM_CTL_3e0 : .dword 0x0000000000000000
MC0_RDIMM_CTL_3f0 : .dword 0x0000000000000000
MC0_RDIMM_CTL_400 : .dword 0x0000000000000000
MC0_RDIMM_CTL_410 : .dword 0x0000000000000000
MC0_RDIMM_CTL_420 : .dword 0x0000000000000000
MC0_RDIMM_CTL_430 : .dword 0x0000000000000000
MC0_RDIMM_CTL_440 : .dword 0x0000000000000000
MC0_RDIMM_CTL_450 : .dword 0x0000000000000000
MC0_RDIMM_CTL_460 : .dword 0x0000000000000000
MC0_RDIMM_CTL_470 : .dword 0x0000000000000000
MC0_RDIMM_CTL_480 : .dword 0x0000000000000000
MC0_RDIMM_CTL_490 : .dword 0x0000000000000000
MC0_RDIMM_CTL_4a0 : .dword 0x0000000000000000
MC0_RDIMM_CTL_4b0 : .dword 0x0000000000000000
MC0_RDIMM_CTL_4c0 : .dword 0x0000000000000000
MC0_RDIMM_CTL_4d0 : .dword 0x0000000000000000
MC0_RDIMM_CTL_4e0 : .dword 0x0000000000000000
MC0_RDIMM_CTL_4f0 : .dword 0x0000000000000000
MC0_RDIMM_CTL_500 : .dword 0x0000000000000000
MC0_RDIMM_CTL_510 : .dword 0x0000000000000000
MC0_RDIMM_CTL_520 : .dword 0x0000000000000000
MC0_RDIMM_CTL_530 : .dword 0x0000000000000000
MC0_RDIMM_CTL_540 : .dword 0x0000000000000000
MC0_RDIMM_CTL_550 : .dword 0x0000000000000000
MC0_RDIMM_CTL_560 : .dword 0x0000000000000000
MC0_RDIMM_CTL_570 : .dword 0x0000000000000000
MC0_RDIMM_CTL_580 : .dword 0x0000000000000000
MC0_RDIMM_CTL_590 : .dword 0x0000000000000000
MC0_RDIMM_CTL_5a0 : .dword 0x0000000000000000
MC0_RDIMM_CTL_5b0 : .dword 0x0000000000000000
MC0_RDIMM_CTL_5c0 : .dword 0x0000000000000000
MC0_RDIMM_CTL_5d0 : .dword 0x0000000000000000
MC0_RDIMM_CTL_5e0 : .dword 0x0000000000000000
MC0_RDIMM_CTL_5f0 : .dword 0x0000000000000000
MC0_RDIMM_CTL_600 : .dword 0x0000000000000000
MC0_RDIMM_CTL_610 : .dword 0x0000000000000000
MC0_RDIMM_CTL_620 : .dword 0x0000000000000000
MC0_RDIMM_CTL_630 : .dword 0x0000000000000000
MC0_RDIMM_CTL_640 : .dword 0x0000000000000000
MC0_RDIMM_CTL_650 : .dword 0x0000000000000000
MC0_RDIMM_CTL_660 : .dword 0x0000000000000000
MC0_RDIMM_CTL_670 : .dword 0x0000000000000000
MC0_RDIMM_CTL_680 : .dword 0x0000000000000000
MC0_RDIMM_CTL_690 : .dword 0x0000000000000000
MC0_RDIMM_CTL_6a0 : .dword 0x0000000000000000
MC0_RDIMM_CTL_6b0 : .dword 0x0000000000000000
MC0_RDIMM_CTL_6c0 : .dword 0x0000000000000000
MC0_RDIMM_CTL_6d0 : .dword 0x0000000000000000
MC0_RDIMM_CTL_6e0 : .dword 0x0000000000000000
MC0_RDIMM_CTL_6f0 : .dword 0x0000000000000000
MC0_RDIMM_CTL_700 : .dword 0x0000000000000000
//-------------
MC0_RDIMM_CTL_710 : .dword 0x0000000000000000
//bit 48 en_wr_leveling(RW)
MC0_RDIMM_CTL_720 : .dword 0x0000000000000000
//0000000_0 rdlvl_gate_req(WR) 0000000_0 rdlvl_gate_preamble_check_en(RW) 0000000_0 rdlvl_gate_en(RW) 0000000_0 rdlvl_en(RW) 0000000_0 rdlvl_begin_delay_en(RW) 00000000 00000000 0000000_0 swlvl_op_done(RD)
MC0_RDIMM_CTL_730 : .dword 0x0000000000000000
//0000000_0 rdlvl_offset_dir_7(RW) 0000000_0 rdlvl_offset_dir_6(RW) 0000000_0 rdlvl_offset_dir_5(RW)0000000_0 rdlvl_offset_dir_4(RW) 0000000_0 rdlvl_offset_dir_3(RW) 0000000_0 rdlvl_offset_dir_2(RW) 0000000_0 rdlvl_offset_dir_1(RW) 0000000_0 rdlvl_offset_dir_0(RW)
MC0_RDIMM_CTL_740 : .dword 0x0100000000000000
//000000_00 axi1_port_ordering(RW) 000000_00 axi0_port_ordering(RW) 0000000_0 wrlvl_req(WR) 0000000_0 wrlvl_interval_ct_en(RW) 0000000_0 weight_round_robin_weight_sharing(RW) 0000000_0 weight_round_robin_latency_control 0000000_0(RW) rdlvl_req 0000000_0(WR) rdlvl_offset_dir_8(RW)
MC0_RDIMM_CTL_750 : .dword 0x0000000101020101
//000000_01 wrlvl_cs(RW) 000000_00 sw_leveling_mode(RW) 000000_00 rdlvl_cs(RW) 000000_01 axi2_w_priority(RW) 000000_01 axi2_r_priority(RW) 000000_10 axi2_port_ordering(RW) 000000_01 axi1_w_priority(RW) 000000_01 axi1_r_priority(RW)
MC0_RDIMM_CTL_760 : .dword 0x0303030000020000
//0000_0011 axi0_priority2_relative_priority(RW) 0000_0011 axi0_priority1_relative_priority(RW) 0000_0011 axi0_priority0_relative_priority(RW) 0000_0000 address_mirroring(RW) 00000_000 tdfi_dram_clk_disable(RW) 00000_010 bstlen(RW) 000000_00 zq_req(WR) 000000_01 zq_on_sref_exit(RW)
MC0_RDIMM_CTL_770 : .dword 0x0101010202020203
//0000_0001 axi2_priority2_relative_priority(RW) 0000_0001 axi2_priority1_relative_priority(RW) 0000_0001 axi2_priority0_relative_priority(RW) 0000_0010 axi1_priority3_relative_priority(RW) 0000_0010 axi1_priority2_relative_priority(RW) 0000_0010 axi1_priority1_relative_priority(RW) 0000_0010 axi1_priority0_relative_priority(RW) 0000_0011 axi0_priority3_relative_priority(RW)
MC0_RDIMM_CTL_780 : .dword 0x0102000000040001
//0000_0001 tdfi_dram_clk_enable(RW) 0000_0010 tdfi_ctrl_delay(RW) 0000_0010 rdlvl_gate_dq_zero_count(RW) 0000_0100 rdlvl_dq_zero_count(RW) 0000_0000 lowpower_refresh_enable(RW) 0000_0110 dram_class(RW) 0000_1100 burst_on_fly_bit(RW) 0000_0001 axi2_priority3_relative_priority(RW)
MC0_RDIMM_CTL_790 : .dword 0x0000000000000000
//00_101000 wlmrd(RW) 00_011001 wldqsen(RW) 000_00000 lowpower_control(RW) 000_00000 lowpower_auto_enable(RW) 0000_1111 zqcs_chip(RW) 0000_0000 wrr_param_value_err(RD) 0000_0011 tdfi_wrlvl_dll(RW) 0000_0011 tdfi_rdlvl_dll(RW)
MC0_RDIMM_CTL_7a0 : .dword 0x0000000000000000
//_00000000 swlvl_resp_6(RW) _00000000 swlvl_resp_5(RW) _00000000 swlvl_resp_4 _00000000 swlvl_resp_3(RW) _00000000 swlvl_resp_2(RW) _00000000 swlvl_resp_1(RW) _00000000 swlvl_resp_0(RW) _00000000 dfi_wrlvl_max_delay(RW)
MC0_RDIMM_CTL_7b0 : .dword 0x0000000000000000
//_00000000 rdlvl_begin_delay_5(RW) _00000000 rdlvl_begin_delay_4(RW) _00000000 rdlvl_begin_delay_3(RW) _00000000 rdlvl_begin_delay_2(RW) _00000000 rdlvl_begin_delay_1(RW) _00000000 rdlvl_begin_delay_0(RW) _00000000 swlvl_resp_8(RW) _00000000 swlvl_resp_7(RW)
MC0_RDIMM_CTL_7c0 : .dword 0x0000000000000000
//_00000000 rdlvl_end_delay_4(RW) _00000000 rdlvl_end_delay_3(RW) _00000000 rdlvl_end_delay_2(RW) _00000000 rdlvl_end_delay_1(RW) _00000000 rdlvl_end_delay_0(RW) _00000000 rdlvl_begin_delay_8(RW) _00000000 rdlvl_begin_delay_7(RW) _00000000 rdlvl_begin_delay_6(RW)
MC0_RDIMM_CTL_7d0 : .dword 0x0000000000000000
//_00000000 rdlvl_gate_clk_adjust_3(RW) _00000000 rdlvl_gate_clk_adjust_2(RW) _00000000 rdlvl_gate_clk_adjust_1(RW) _00000000 rdlvl_gate_clk_adjust_0(RW) _00000000 rdlvl_end_delay_8(RW) _00000000 rdlvl_end_delay_7(RW) _00000000 rdlvl_end_delay_6(RW) 00000000 rdlvl_end_delay_5(RW)
MC0_RDIMM_CTL_7e0 : .dword 0x0000000000000000
//00000000 rdlvl_gate_delay_2(RD) 00000000 rdlvl_gate_delay_1(RD) 00000000 rdlvl_gate_delay_0(RD) 00000000 rdlvl_gate_clk_adjust_8(RW) 00000000 rdlvl_gate_clk_adjust_7(RW) 00000000 rdlvl_gate_clk_adjust_6(RW) 00000000 rdlvl_gate_clk_adjust_5(RW) 00000000 rdlvl_gate_clk_adjust_4(RW)
MC0_RDIMM_CTL_7f0 : .dword 0x0000000000000000
//11111111 rdlvl_max_delay(RW) 00001000 rdlvl_gate_max_delay(RW) 00000000 rdlvl_gate_delay_8(RD) 00000000 rdlvl_gate_delay_7(RD) 00000000 rdlvl_gate_delay_6(RD) 00000000 rdlvl_gate_delay_5(RD) 00000000 rdlvl_gate_delay_4(RD) 00000000 rdlvl_gate_delay_3(RD)
MC0_RDIMM_CTL_800 : .dword 0x0000000000000000
//00000000 rdlvl_midpoint_delay_7(RD) 00000000 rdlvl_midpoint_delay_6(RD) 00000000 rdlvl_midpoint_delay_5(RD) 00000000 rdlvl_midpoint_delay_4(RD) 00000000 rdlvl_midpoint_delay_3(RD) 00000000 rdlvl_midpoint_delay_2(RD) 00000000 rdlvl_midpoint_delay_1(RD) 00000000 rdlvl_midpoint_delay_0(RD)
MC0_RDIMM_CTL_810 : .dword 0x0000000000000000
//00000000 rdlvl_offset_delay_6(RW) 00000000 rdlvl_offset_delay_5(RW) 00000000 rdlvl_offset_delay_4(RW) 00000000 rdlvl_offset_delay_3(RW) 00000000 rdlvl_offset_delay_2(RW) 00000000 rdlvl_offset_delay_1(RW) 00000000 rdlvl_offset_delay_0(RW) 00000000 rdlvl_midpoint_delay_8(RD)
MC0_RDIMM_CTL_820 : .dword 0x0000000000000000
//00000100 tdfi_wrlvl_resplat(RW) 00000000 tdfi_wrlvl_resp(RD) 00000000 tdfi_rdlvl_rr(RW) 00001100 tdfi_rdlvl_resplat(RW) 00000000 tdfi_rdlvl_resp(RD) 01000000 refresh_per_zq(RW) 00000000 rdlvl_offset_delay_8(RW) 00000000 rdlvl_offset_delay_7(RW)
MC0_RDIMM_CTL_830 : .dword 0x181818181818050a
//00000000 wrlvl_delay_5(RD) 00000000 wrlvl_delay_4(RD) 00000000 wrlvl_delay_3(RD) 00000000 wrlvl_delay_2(RD) 00000000 wrlvl_delay_1(RD) 00000000 wrlvl_delay_0(RD) 00000010 tmod(RW) 00001010 tdfi_wrlvl_ww(RW)
MC0_RDIMM_CTL_840 : .dword 0x0000640064181818
//00000000000000_0001100100 axi1_priority_relax(RW) 000000_0001100100 axi0_priority_relax(RW) 00000000 wrlvl_delay_8(RD) 00000000 wrlvl_delay_7(RD) 00000000 wrlvl_delay_6(RD)
MC0_RDIMM_CTL_850 : .dword 0x0000000000000064
//000000_0000000000 out_of_range_source_id(RD) 000000_0000000000 ecc_u_id(RD) 000000_0000000000 ecc_c_id(RD) 000000_0000000000 axi2_priority_relax(RW)
MC0_RDIMM_CTL_860 : .dword 0x0000000000000000
//0000_000000000000 zqini(RW) 0000_000000000000 zqcs(RW) 000000_0000000000 port_data_error_id(RD) 000000_0000000000 port_cmd_error_id(RD)
MC0_RDIMM_CTL_870 : .dword 0x0046004600460046
//0_000000000000010 emrs1_data_3(RW) 0_000000000000010 emrs1_data_2(RW) 0_000000000000010 emrs1_data_1(RW) 0_000000000000010 emrs1_data_0(RW)
MC0_RDIMM_CTL_880 : .dword 0x0000000000000000
//0_000000000000010 emrs3_data_3(RW) 0_000000000000010 emrs3_data_2(RW) 0_000000000000010 emrs3_data_1(RW) 0_000000000000010 emrs3_data_0(RW)
MC0_RDIMM_CTL_890 : .dword 0x0a620a620a620a62
//0_000010000010000 mrs_data_3(RW) 0_000010000010000 mrs_data_2(RW) 0_000010000010000 mrs_data_1(RW) 0_000010000010000 mrs_data_0(RW)
MC0_RDIMM_CTL_8a0 : .dword 0x00000000001c001c
//hXXXX lowpower_internal_cnt(RW) hXXXX lowpower_external_cnt(RW) hXXXX axi2_en_size_lt_width_instr(RW) hXXXX axi1_en_size_lt_width_instr(RW)
MC0_RDIMM_CTL_8b0 : .dword 0x0000000000000000
//hXXXX refresh_per_rdlvl(RW) hXXXX lowpower_self_refresh_cnt(RW) hXXXX lowpower_refresh_hold(RW) hXXXX lowpower_power_down_cnt(RW)
MC0_RDIMM_CTL_8c0 : .dword 0x0000000000000000
//hXXXX wrlvl_interval(RW) hXXXX tdfi_wrlvl_max(RW) hXXXX tdfi_rdlvl_max(RW) hXXXX refresh_per_rdlvl_gate(RW)
MC0_RDIMM_CTL_8d0 : .dword 0x002faf0800000000
//h00_XXXXXXXX cke_inactive(RW) 000000_000000000000000000 wrlvl_status(RD)
MC0_RDIMM_CTL_8e0 : .dword 0x0000000023c34600
//h00000000_XXXXXXXX trst_pwron(RW)
MC0_RDIMM_CTL_8f0 : .dword 0x0000000000100000
//hXXXXXXX 000_0 XXXXXXXX dll_ctrl_reg_2(RW)
MC0_RDIMM_CTL_900 : .dword 0x0000000000000000
//h000000 00_00 X XXXXXXXX rdlvl_error_status(RW)
MC0_RDIMM_CTL_910 : .dword 0x0000000000000000
//hXXXXXXXX XXXXXXXX rdlvl_gate_resp_mask[63:0](RW)
MC0_RDIMM_CTL_920 : .dword 0x0000000000000000
//h00000000000000_XX rdlvl_gate_resp_mask[71:64](RW)
MC0_RDIMM_CTL_930 : .dword 0x0000000000000000
//hXXXXXXXX XXXXXXXX rdlvl_resp_mask[63:0](RW)
MC0_RDIMM_CTL_940 : .dword 0x0007070000050500
//0000_0000 tdfi_rdlvl_en(RW) 00000_000 w2r_samecs_delay(RW) 00000_000 w2r_diffcs_delay(RW) 00000_000 lvl_status(RD) 0000000_0 rdlvl_edge(RW) 0000_0000 cksrx(RW) 0000_0000 cksre(RW) _00000000 rdlvl_resp_mask[71:64](RW)
MC0_RDIMM_CTL_950 : .dword 0x0000000000000800
//hXXXXX 00_00 XXXX mask_int[17:0](RW) hXXXX txpdll(RW) 0000_0000 tdfi_wrlvl_en(RW)
MC0_RDIMM_CTL_960 : .dword 0x0705000000000000
//000_00101 rdlat_adj(RW) 0000_0100 wrlat_adj(RW) 0000000_0 swlvl_start(WR) 0000000_0 swlvl_load(WR) 0000000_0 swlvl_exit(WR) 000000_000000000000000000 int_status(RD)
MC0_RDIMM_CTL_970 : .dword 0x000000000003e805
//h00000 000_0 XXXX int_ack[16:0](WR) hXXXX dll_rst_delay(RW) hXX dll_rst_adj_dly(RW)
//use CL=6
ddr2_RDIMM_reg_data_mc1:
MC1_RDIMM_CTL_000 : .dword 0x0000010000000101
//000000000000000_0 concurrentap(RW) 0000000_1 bank_split_en(RW) 0000000_0 auto_refresh_mode(RW) 0000000_0 arefresh(WR) 0000000_0 ap(RW) 0000000_1 addr_cmp_en(RW) 0000000_1 active_aging(RW)
MC1_RDIMM_CTL_010 : .dword 0x0001000100010000
//0000000_0 fwc(WR) 0000000_0 fast_write(RW) 0000000_1 enable_quick_srefresh(RW) 0000000_1 eight_bank_mode(RW) 0000000_0 ecc_disable_w_uc_err(RW) 0000000_1 dqs_n_en(RW) 0000000_0 dll_bypass_mode(RW) 0000000_0 dlllockreg(RD)
MC1_RDIMM_CTL_020 : .dword 0x0100010101000000
//0000000_1 priority_en(RW) 0000000_0 power_down(RW) 0000000_1 placement_en(RW) 0000000_1 odt_add_turn_clk_en(RW) 0000000_0 no_cmd_init(RW) 0000000_0 intrptwritea(RW) 0000000_0 intrptreada(RW) 0000000_0 intrptapburst(RW)
MC1_RDIMM_CTL_030 : .dword 0x0001000001010000
//0000000_1 swap_port_rw_same_en(RW) 0000000_1 swap_en(RW) 0000000_0 start(RW) 0000000_0 srefresh(RW+) 0000000_1 rw_same_en(RW) 0000000_0 reg_dimm_enable(RW) 0000000_0 reduc(RW) 0000000_0 pwrup_srefresh_exit(RW)
MC1_RDIMM_CTL_040 : .dword 0x0102010200000100
//000000_01 rtt_0(RW) 000000_11 ctrl_raw(RW) 000000_01 axi0_w_priority(RW) 000000_01 axi0_r_priority(RW) 0000000_0 write_modereg(WR) 0000000_1 writeinterp(RW) 0000000_1 tref_enable(RW) 0000000_1 tras_lockout(RW)
MC1_RDIMM_CTL_050 : .dword 0x0200000004060100
//00000_000 q_fullness(RW) 00000_000 port_data_error_type(RD) 000_00000 out_of_range_type(RD) 00000_000 max_cs_reg(RD) 00000_100 column_size(RW) 0000_0101 caslat(RW) 00000_010 addr_pins(RW) 00000000
MC1_RDIMM_CTL_060 : .dword 0x0a05030603030003
//0000_1010 aprebit(RW) 0000_0101 wrlat(RW) 0000_0100 twtr(RW) 000_00110 twr_int(RW) 00000_011 trtp(RW) 00000_100 trrd(RW) 0000000000000_011 tcke(RW)
MC1_RDIMM_CTL_070 : .dword 0x00000200000f0c0c
//0000_0000 max_row_reg(RD) 0000_0000 max_col_reg(RD) 0000_0000 initaref(RW) 00000000000000000000_1111 cs_map(RW) 000_01010 caslat_lin_gate(RW) 000_01010 caslat_lin(RW)
MC1_RDIMM_CTL_080 : .dword 0x0804020108040201
//0000_0001 odt_wr_map_cs3(RW) 0000_0010 odt_wr_map_cs2(RW) 0000_0100 odt_wr_map_cs1(RW) 0000_1000 odt_wr_map_cs0(RW) 0000_0001 odt_rd_map_cs3(RW) 0000_0010 odt_rd_map_cs2(RW) 0000_0100 odt_rd_map_cs1(RW) 0000_1000 odt_rd_map_cs0(RW)
MC1_RDIMM_CTL_090 : .dword 0x0000070d00000000
//000_00000 ocd_adjust_pup_cs_0(RW) 000_00000 ocd_adjust_pdn_cs_0(RW) 0000_0101 trp(RW) 000_01011 tdal(RW) 000000000000_0000 port_cmd_error_type(RD) 0000000000000000
MC1_RDIMM_CTL_0a0 : .dword 0x0000003f3f18050e
//00000000000000000000000000_111111 command_age_count(RW) 00_111111 age_count(RW) 000_10100 trc(RW) 000_00110 tmrd(RW) 000_10010 tfaw(RW)
MC1_RDIMM_CTL_0b0 : .dword 0x0000000000000000
MC1_RDIMM_CTL_0c0 : .dword 0x0000330612000000
//000000000000000000101100 trfc(RW) 00000101 trcd_int(RW) 00001111 tras_min(RW) 00000000 out_of_range_length(RD) 00000000 ecc_u_synd(RD) 00000000 ecc_c_synd(RD)
MC1_RDIMM_CTL_0d0 : .dword 0x0000000000000000
MC1_RDIMM_CTL_0e0 : .dword 0x0000000000000000
MC1_RDIMM_CTL_0f0 : .dword 0x0000000000000000
//Bit 21:16 dll_lock(RD)
MC1_RDIMM_CTL_100 : .dword 0x0000000000000000
//MC1_RDIMM_CTL_110 : .dword 0x00000000000002e0 #100M+
//MC1_RDIMM_CTL_110 : .dword 0x00000000000005e0 #200M+
MC1_RDIMM_CTL_110 : .dword 0x0000000000000900 #300M+
//MC0_RDIMM_CTL_110 : .dword 0x0000000000000c00 #400M
//0_000000000000000 emrs2_data_1(RW) 0_000000000000000 emrs2_data_0(RW) 000000000000000000_00110000101101 tref(RW)
MC1_RDIMM_CTL_120 : .dword 0xffff000000000000
//0000000000011100 axi0_en_size_lt_width_instr(RW) 00000000000000000_000000000000000 emrs2_data_3(RW) 0_000000000000000 emrs2_data_2(RW)
//MC1_RDIMM_CTL_130 : .dword 0x1b20000200c800c8 #100M+
//MC1_RDIMM_CTL_130 : .dword 0x3680000200c800c8 #200M+
MC1_RDIMM_CTL_130 : .dword 0x51d0000200c800c8 #300M+
//MC1_RDIMM_CTL_130 : .dword 0x6d30000200c800c8 #400M
//0110110101010110 tras_max(RW) 0000000000000011 tpdex(RW) 0000001000000000 tdll(RW) 0000000000000000 tcpd(RW)
MC1_RDIMM_CTL_140 : .dword 0x0000204000c80037
//0000000000000000 xor_check_bits(RW) 0000000000000000 version(RD) 0000001000000000 txsr(RW) 0000000000110000 txsnr(RW)
MC1_RDIMM_CTL_150 : .dword 0x0000000000027100
//000_0000000000000000000000000000000000000 ecc_c_addr(RD) 000000000000000000011011 tinit(RW)
MC1_RDIMM_CTL_160 : .dword 0x0000000000000000
//000000000000000000000000000_0000000000000000000000000000000000000 ecc_u_addr(RD)
MC1_RDIMM_CTL_170 : .dword 0x0000000000000000
//000000000000000000000000000_0000000000000000000000000000000000000 out_of_range_addr(RD)
MC1_RDIMM_CTL_180 : .dword 0x0000000000000000
//000000000000000000000000000_0000000000000000000000000000000000000 port_cmd_error_addr(RD)
MC1_RDIMM_CTL_190 : .dword 0x0000000000000000
//0000000000000000000000000000000000000000000000000000000000000000 ecc_c_data(RD)
MC1_RDIMM_CTL_1a0 : .dword 0x0000000000000000
//0000000000000000000000000000000000000000000000000000000000000000 ecc_u_data(RD)
MC1_RDIMM_CTL_1b0 : .dword 0x0000000000000000
//0000000000000000000000000000000000000000000000000000000000000_000 cke_delay(RW)
MC1_RDIMM_CTL_1c0 : .dword 0x0000000000000000
MC1_RDIMM_CTL_1d0 : .dword 0x0200070000000001
//0000_0010 tdfi_phy_wrlat_base(RW) 0000_0000 tdfi_phy_wrlat(RD) 000_00111 tdfi_phy_rdlat(RW) 0000_0000 tdfi_ctrlupd_min(RD) 000000000000_0000 dram_clk_disable(RW) 0000000_1 odt_alt_en(RW) 0000000_1 drive_dq_dqs(RW)
MC1_RDIMM_CTL_1e0 : .dword 0x0000000000000200
//00_00000000000000 tdfi_phyupd_type0(RD) 00_00000000000000 tdfi_phyupd_resp(RD) 00_00000000000000 tdfi_ctrlupd_max(RD) 000_00000 tdfi_rddata_en_base(RW) 000_00000 tdfi_rddata_en(RD)
//wr_delay 375M use 07
MC1_RDIMM_CTL_1f0 : .dword 0x0012208000000000
MC1_RDIMM_CTL_200 : .dword 0x0012208000122080
MC1_RDIMM_CTL_210 : .dword 0x0012208000122080
MC1_RDIMM_CTL_220 : .dword 0x0012208000122080
MC1_RDIMM_CTL_230 : .dword 0x0012208000122080
MC1_RDIMM_CTL_240 : .dword 0x0000200000002000
MC1_RDIMM_CTL_250 : .dword 0x0000200000002000
MC1_RDIMM_CTL_260 : .dword 0x0000200000002000
MC1_RDIMM_CTL_270 : .dword 0x0000200000002000
MC1_RDIMM_CTL_280 : .dword 0x0000000000002000
MC1_RDIMM_CTL_290 : .dword 0x0000000000000000
//hXXXXXXX 00_00 dll_obs_reg_0_2(RW) hXXXXXXX 00_00 dll_obs_reg_0_1(RW)
MC1_RDIMM_CTL_2a0 : .dword 0x0000000000000000
//hXXXXXXX 00_00 dll_obs_reg_0_4(RW) hXXXXXXX 00_00 dll_obs_reg_0_3(RW)
MC1_RDIMM_CTL_2b0 : .dword 0x0000000000000000
//hXXXXXXX 00_00 dll_obs_reg_0_6(RW) hXXXXXXX 00_00 dll_obs_reg_0_5(RW)
MC1_RDIMM_CTL_2c0 : .dword 0x0000000000000000
//hXXXXXXX 00_00 dll_obs_reg_0_8(RW) hXXXXXXX 00_00 dll_obs_reg_0_7(RW)
MC1_RDIMM_CTL_2d0 : .dword 0x1300483303c009b4
MC1_RDIMM_CTL_2e0 : .dword 0x1300483313004833
MC1_RDIMM_CTL_2f0 : .dword 0x1300483313004833
MC1_RDIMM_CTL_300 : .dword 0x1300483313004833
MC1_RDIMM_CTL_310 : .dword 0x1300483313004833
MC1_RDIMM_CTL_320 : .dword 0x26c0000126c00001
MC1_RDIMM_CTL_330 : .dword 0x26c0000126c00001
MC1_RDIMM_CTL_340 : .dword 0x26c0000126c00001
MC1_RDIMM_CTL_350 : .dword 0x26c0000126c00001
MC1_RDIMM_CTL_360 : .dword 0x0800c00026c00001
//00000000000000001100000000000101 phy_ctrl_reg_2(RW) 00000111110000000000001100000001 phy_ctrl_reg_1_8(RD)
//--------------
MC1_RDIMM_CTL_370 : .dword 0x0000000000000000
MC1_RDIMM_CTL_380 : .dword 0x0000000000000000
MC1_RDIMM_CTL_390 : .dword 0x0000000000000000
MC1_RDIMM_CTL_3a0 : .dword 0x0000000000000000
MC1_RDIMM_CTL_3b0 : .dword 0x0000000000000000
MC1_RDIMM_CTL_3c0 : .dword 0x0000000000000000
MC1_RDIMM_CTL_3d0 : .dword 0x0000000000000000
MC1_RDIMM_CTL_3e0 : .dword 0x0000000000000000
MC1_RDIMM_CTL_3f0 : .dword 0x0000000000000000
MC1_RDIMM_CTL_400 : .dword 0x0000000000000000
MC1_RDIMM_CTL_410 : .dword 0x0000000000000000
MC1_RDIMM_CTL_420 : .dword 0x0000000000000000
MC1_RDIMM_CTL_430 : .dword 0x0000000000000000
MC1_RDIMM_CTL_440 : .dword 0x0000000000000000
MC1_RDIMM_CTL_450 : .dword 0x0000000000000000
MC1_RDIMM_CTL_460 : .dword 0x0000000000000000
MC1_RDIMM_CTL_470 : .dword 0x0000000000000000
MC1_RDIMM_CTL_480 : .dword 0x0000000000000000
MC1_RDIMM_CTL_490 : .dword 0x0000000000000000
MC1_RDIMM_CTL_4a0 : .dword 0x0000000000000000
MC1_RDIMM_CTL_4b0 : .dword 0x0000000000000000
MC1_RDIMM_CTL_4c0 : .dword 0x0000000000000000
MC1_RDIMM_CTL_4d0 : .dword 0x0000000000000000
MC1_RDIMM_CTL_4e0 : .dword 0x0000000000000000
MC1_RDIMM_CTL_4f0 : .dword 0x0000000000000000
MC1_RDIMM_CTL_500 : .dword 0x0000000000000000
MC1_RDIMM_CTL_510 : .dword 0x0000000000000000
MC1_RDIMM_CTL_520 : .dword 0x0000000000000000
MC1_RDIMM_CTL_530 : .dword 0x0000000000000000
MC1_RDIMM_CTL_540 : .dword 0x0000000000000000
MC1_RDIMM_CTL_550 : .dword 0x0000000000000000
MC1_RDIMM_CTL_560 : .dword 0x0000000000000000
MC1_RDIMM_CTL_570 : .dword 0x0000000000000000
MC1_RDIMM_CTL_580 : .dword 0x0000000000000000
MC1_RDIMM_CTL_590 : .dword 0x0000000000000000
MC1_RDIMM_CTL_5a0 : .dword 0x0000000000000000
MC1_RDIMM_CTL_5b0 : .dword 0x0000000000000000
MC1_RDIMM_CTL_5c0 : .dword 0x0000000000000000
MC1_RDIMM_CTL_5d0 : .dword 0x0000000000000000
MC1_RDIMM_CTL_5e0 : .dword 0x0000000000000000
MC1_RDIMM_CTL_5f0 : .dword 0x0000000000000000
MC1_RDIMM_CTL_600 : .dword 0x0000000000000000
MC1_RDIMM_CTL_610 : .dword 0x0000000000000000
MC1_RDIMM_CTL_620 : .dword 0x0000000000000000
MC1_RDIMM_CTL_630 : .dword 0x0000000000000000
MC1_RDIMM_CTL_640 : .dword 0x0000000000000000
MC1_RDIMM_CTL_650 : .dword 0x0000000000000000
MC1_RDIMM_CTL_660 : .dword 0x0000000000000000
MC1_RDIMM_CTL_670 : .dword 0x0000000000000000
MC1_RDIMM_CTL_680 : .dword 0x0000000000000000
MC1_RDIMM_CTL_690 : .dword 0x0000000000000000
MC1_RDIMM_CTL_6a0 : .dword 0x0000000000000000
MC1_RDIMM_CTL_6b0 : .dword 0x0000000000000000
MC1_RDIMM_CTL_6c0 : .dword 0x0000000000000000
MC1_RDIMM_CTL_6d0 : .dword 0x0000000000000000
MC1_RDIMM_CTL_6e0 : .dword 0x0000000000000000
MC1_RDIMM_CTL_6f0 : .dword 0x0000000000000000
MC1_RDIMM_CTL_700 : .dword 0x0000000000000000
//-------------
MC1_RDIMM_CTL_710 : .dword 0x0000000000000000
//bit 48 en_wr_leveling(RW)
MC1_RDIMM_CTL_720 : .dword 0x0000000000000000
//0000000_0 rdlvl_gate_req(WR) 0000000_0 rdlvl_gate_preamble_check_en(RW) 0000000_0 rdlvl_gate_en(RW) 0000000_0 rdlvl_en(RW) 0000000_0 rdlvl_begin_delay_en(RW) 00000000 00000000 0000000_0 swlvl_op_done(RD)
MC1_RDIMM_CTL_730 : .dword 0x0000000000000000
//0000000_0 rdlvl_offset_dir_7(RW) 0000000_0 rdlvl_offset_dir_6(RW) 0000000_0 rdlvl_offset_dir_5(RW)0000000_0 rdlvl_offset_dir_4(RW) 0000000_0 rdlvl_offset_dir_3(RW) 0000000_0 rdlvl_offset_dir_2(RW) 0000000_0 rdlvl_offset_dir_1(RW) 0000000_0 rdlvl_offset_dir_0(RW)
MC1_RDIMM_CTL_740 : .dword 0x0100000000000000
//000000_00 axi1_port_ordering(RW) 000000_00 axi0_port_ordering(RW) 0000000_0 wrlvl_req(WR) 0000000_0 wrlvl_interval_ct_en(RW) 0000000_0 weight_round_robin_weight_sharing(RW) 0000000_0 weight_round_robin_latency_control 0000000_0(RW) rdlvl_req 0000000_0(WR) rdlvl_offset_dir_8(RW)
MC1_RDIMM_CTL_750 : .dword 0x0000000101020101
//000000_01 wrlvl_cs(RW) 000000_00 sw_leveling_mode(RW) 000000_00 rdlvl_cs(RW) 000000_01 axi2_w_priority(RW) 000000_01 axi2_r_priority(RW) 000000_10 axi2_port_ordering(RW) 000000_01 axi1_w_priority(RW) 000000_01 axi1_r_priority(RW)
MC1_RDIMM_CTL_760 : .dword 0x0303030000020000
//0000_0011 axi0_priority2_relative_priority(RW) 0000_0011 axi0_priority1_relative_priority(RW) 0000_0011 axi0_priority0_relative_priority(RW) 0000_0000 address_mirroring(RW) 00000_000 tdfi_dram_clk_disable(RW) 00000_010 bstlen(RW) 000000_00 zq_req(WR) 000000_01 zq_on_sref_exit(RW)
MC1_RDIMM_CTL_770 : .dword 0x0101010202020203
//0000_0001 axi2_priority2_relative_priority(RW) 0000_0001 axi2_priority1_relative_priority(RW) 0000_0001 axi2_priority0_relative_priority(RW) 0000_0010 axi1_priority3_relative_priority(RW) 0000_0010 axi1_priority2_relative_priority(RW) 0000_0010 axi1_priority1_relative_priority(RW) 0000_0010 axi1_priority0_relative_priority(RW) 0000_0011 axi0_priority3_relative_priority(RW)
MC1_RDIMM_CTL_780 : .dword 0x0102000000040001
//0000_0001 tdfi_dram_clk_enable(RW) 0000_0010 tdfi_ctrl_delay(RW) 0000_0010 rdlvl_gate_dq_zero_count(RW) 0000_0100 rdlvl_dq_zero_count(RW) 0000_0000 lowpower_refresh_enable(RW) 0000_0110 dram_class(RW) 0000_1100 burst_on_fly_bit(RW) 0000_0001 axi2_priority3_relative_priority(RW)
MC1_RDIMM_CTL_790 : .dword 0x0000000000000000
//00_101000 wlmrd(RW) 00_011001 wldqsen(RW) 000_00000 lowpower_control(RW) 000_00000 lowpower_auto_enable(RW) 0000_1111 zqcs_chip(RW) 0000_0000 wrr_param_value_err(RD) 0000_0011 tdfi_wrlvl_dll(RW) 0000_0011 tdfi_rdlvl_dll(RW)
MC1_RDIMM_CTL_7a0 : .dword 0x0000000000000000
//_00000000 swlvl_resp_6(RW) _00000000 swlvl_resp_5(RW) _00000000 swlvl_resp_4 _00000000 swlvl_resp_3(RW) _00000000 swlvl_resp_2(RW) _00000000 swlvl_resp_1(RW) _00000000 swlvl_resp_0(RW) _00000000 dfi_wrlvl_max_delay(RW)
MC1_RDIMM_CTL_7b0 : .dword 0x0000000000000000
//_00000000 rdlvl_begin_delay_5(RW) _00000000 rdlvl_begin_delay_4(RW) _00000000 rdlvl_begin_delay_3(RW) _00000000 rdlvl_begin_delay_2(RW) _00000000 rdlvl_begin_delay_1(RW) _00000000 rdlvl_begin_delay_0(RW) _00000000 swlvl_resp_8(RW) _00000000 swlvl_resp_7(RW)
MC1_RDIMM_CTL_7c0 : .dword 0x0000000000000000
//_00000000 rdlvl_end_delay_4(RW) _00000000 rdlvl_end_delay_3(RW) _00000000 rdlvl_end_delay_2(RW) _00000000 rdlvl_end_delay_1(RW) _00000000 rdlvl_end_delay_0(RW) _00000000 rdlvl_begin_delay_8(RW) _00000000 rdlvl_begin_delay_7(RW) _00000000 rdlvl_begin_delay_6(RW)
MC1_RDIMM_CTL_7d0 : .dword 0x0000000000000000
//_00000000 rdlvl_gate_clk_adjust_3(RW) _00000000 rdlvl_gate_clk_adjust_2(RW) _00000000 rdlvl_gate_clk_adjust_1(RW) _00000000 rdlvl_gate_clk_adjust_0(RW) _00000000 rdlvl_end_delay_8(RW) _00000000 rdlvl_end_delay_7(RW) _00000000 rdlvl_end_delay_6(RW) 00000000 rdlvl_end_delay_5(RW)
MC1_RDIMM_CTL_7e0 : .dword 0x0000000000000000
//00000000 rdlvl_gate_delay_2(RD) 00000000 rdlvl_gate_delay_1(RD) 00000000 rdlvl_gate_delay_0(RD) 00000000 rdlvl_gate_clk_adjust_8(RW) 00000000 rdlvl_gate_clk_adjust_7(RW) 00000000 rdlvl_gate_clk_adjust_6(RW) 00000000 rdlvl_gate_clk_adjust_5(RW) 00000000 rdlvl_gate_clk_adjust_4(RW)
MC1_RDIMM_CTL_7f0 : .dword 0x0000000000000000
//11111111 rdlvl_max_delay(RW) 00001000 rdlvl_gate_max_delay(RW) 00000000 rdlvl_gate_delay_8(RD) 00000000 rdlvl_gate_delay_7(RD) 00000000 rdlvl_gate_delay_6(RD) 00000000 rdlvl_gate_delay_5(RD) 00000000 rdlvl_gate_delay_4(RD) 00000000 rdlvl_gate_delay_3(RD)
MC1_RDIMM_CTL_800 : .dword 0x0000000000000000
//00000000 rdlvl_midpoint_delay_7(RD) 00000000 rdlvl_midpoint_delay_6(RD) 00000000 rdlvl_midpoint_delay_5(RD) 00000000 rdlvl_midpoint_delay_4(RD) 00000000 rdlvl_midpoint_delay_3(RD) 00000000 rdlvl_midpoint_delay_2(RD) 00000000 rdlvl_midpoint_delay_1(RD) 00000000 rdlvl_midpoint_delay_0(RD)
MC1_RDIMM_CTL_810 : .dword 0x0000000000000000
//00000000 rdlvl_offset_delay_6(RW) 00000000 rdlvl_offset_delay_5(RW) 00000000 rdlvl_offset_delay_4(RW) 00000000 rdlvl_offset_delay_3(RW) 00000000 rdlvl_offset_delay_2(RW) 00000000 rdlvl_offset_delay_1(RW) 00000000 rdlvl_offset_delay_0(RW) 00000000 rdlvl_midpoint_delay_8(RD)
MC1_RDIMM_CTL_820 : .dword 0x0000000000000000
//00000100 tdfi_wrlvl_resplat(RW) 00000000 tdfi_wrlvl_resp(RD) 00000000 tdfi_rdlvl_rr(RW) 00001100 tdfi_rdlvl_resplat(RW) 00000000 tdfi_rdlvl_resp(RD) 01000000 refresh_per_zq(RW) 00000000 rdlvl_offset_delay_8(RW) 00000000 rdlvl_offset_delay_7(RW)
MC1_RDIMM_CTL_830 : .dword 0x181818181818050a
//00000000 wrlvl_delay_5(RD) 00000000 wrlvl_delay_4(RD) 00000000 wrlvl_delay_3(RD) 00000000 wrlvl_delay_2(RD) 00000000 wrlvl_delay_1(RD) 00000000 wrlvl_delay_0(RD) 00000010 tmod(RW) 00001010 tdfi_wrlvl_ww(RW)
MC1_RDIMM_CTL_840 : .dword 0x0000640064181818
//00000000000000_0001100100 axi1_priority_relax(RW) 000000_0001100100 axi0_priority_relax(RW) 00000000 wrlvl_delay_8(RD) 00000000 wrlvl_delay_7(RD) 00000000 wrlvl_delay_6(RD)
MC1_RDIMM_CTL_850 : .dword 0x0000000000000064
//000000_0000000000 out_of_range_source_id(RD) 000000_0000000000 ecc_u_id(RD) 000000_0000000000 ecc_c_id(RD) 000000_0000000000 axi2_priority_relax(RW)
MC1_RDIMM_CTL_860 : .dword 0x0000000000000000
//0000_000000000000 zqini(RW) 0000_000000000000 zqcs(RW) 000000_0000000000 port_data_error_id(RD) 000000_0000000000 port_cmd_error_id(RD)
MC1_RDIMM_CTL_870 : .dword 0x0046004600460046
//0_000000000000010 emrs1_data_3(RW) 0_000000000000010 emrs1_data_2(RW) 0_000000000000010 emrs1_data_1(RW) 0_000000000000010 emrs1_data_0(RW)
MC1_RDIMM_CTL_880 : .dword 0x0000000000000000
//0_000000000000010 emrs3_data_3(RW) 0_000000000000010 emrs3_data_2(RW) 0_000000000000010 emrs3_data_1(RW) 0_000000000000010 emrs3_data_0(RW)
MC1_RDIMM_CTL_890 : .dword 0x0a620a620a620a62
//0_000010000010000 mrs_data_3(RW) 0_000010000010000 mrs_data_2(RW) 0_000010000010000 mrs_data_1(RW) 0_000010000010000 mrs_data_0(RW)
MC1_RDIMM_CTL_8a0 : .dword 0x00000000001c001c
//hXXXX lowpower_internal_cnt(RW) hXXXX lowpower_external_cnt(RW) hXXXX axi2_en_size_lt_width_instr(RW) hXXXX axi1_en_size_lt_width_instr(RW)
MC1_RDIMM_CTL_8b0 : .dword 0x0000000000000000
//hXXXX refresh_per_rdlvl(RW) hXXXX lowpower_self_refresh_cnt(RW) hXXXX lowpower_refresh_hold(RW) hXXXX lowpower_power_down_cnt(RW)
MC1_RDIMM_CTL_8c0 : .dword 0x0000000000000000
//hXXXX wrlvl_interval(RW) hXXXX tdfi_wrlvl_max(RW) hXXXX tdfi_rdlvl_max(RW) hXXXX refresh_per_rdlvl_gate(RW)
MC1_RDIMM_CTL_8d0 : .dword 0x002faf0800000000
//h00_XXXXXXXX cke_inactive(RW) 000000_000000000000000000 wrlvl_status(RD)
MC1_RDIMM_CTL_8e0 : .dword 0x0000000023c34600
//h00000000_XXXXXXXX trst_pwron(RW)
MC1_RDIMM_CTL_8f0 : .dword 0x0000000000100000
//hXXXXXXX 000_0 XXXXXXXX dll_ctrl_reg_2(RW)
MC1_RDIMM_CTL_900 : .dword 0x0000000000000000
//h000000 00_00 X XXXXXXXX rdlvl_error_status(RW)
MC1_RDIMM_CTL_910 : .dword 0x0000000000000000
//hXXXXXXXX XXXXXXXX rdlvl_gate_resp_mask[63:0](RW)
MC1_RDIMM_CTL_920 : .dword 0x0000000000000000
//h00000000000000_XX rdlvl_gate_resp_mask[71:64](RW)
MC1_RDIMM_CTL_930 : .dword 0x0000000000000000
//hXXXXXXXX XXXXXXXX rdlvl_resp_mask[63:0](RW)
MC1_RDIMM_CTL_940 : .dword 0x0007070000050500
//0000_0000 tdfi_rdlvl_en(RW) 00000_000 w2r_samecs_delay(RW) 00000_000 w2r_diffcs_delay(RW) 00000_000 lvl_status(RD) 0000000_0 rdlvl_edge(RW) 0000_0000 cksrx(RW) 0000_0000 cksre(RW) _00000000 rdlvl_resp_mask[71:64](RW)
MC1_RDIMM_CTL_950 : .dword 0x0000000000000800
//hXXXXX 00_00 XXXX mask_int[17:0](RW) hXXXX txpdll(RW) 0000_0000 tdfi_wrlvl_en(RW)
MC1_RDIMM_CTL_960 : .dword 0x0705000000000000
//000_00101 rdlat_adj(RW) 0000_0100 wrlat_adj(RW) 0000000_0 swlvl_start(WR) 0000000_0 swlvl_load(WR) 0000000_0 swlvl_exit(WR) 000000_000000000000000000 int_status(RD)
MC1_RDIMM_CTL_970 : .dword 0x000000000003e805
//h00000 000_0 XXXX int_ack[16:0](WR) hXXXX dll_rst_delay(RW) hXX dll_rst_adj_dly(RW)

7
Targets/Bonito3adawning/Bonito/loongson3A_ddr3_param.S
View File

@ -0,0 +1,7 @@
ddr3_reg_data:
ddr3_reg_data_mc1:
ddr3_RDIMM_reg_data:
ddr3_RDIMM_reg_data_mc1:

1640
Targets/Bonito3adawning/Bonito/loongson3_ddr2_config.S
View File

File diff suppressed because it is too large

890
Targets/Bonito3adawning/Bonito/start.S
View File

@ -257,6 +257,9 @@ exc_common:
mfc0 a0, COP_0_EXC_PC
bal hexserial
nop
1:
b 1b
nop
#ifndef ROM_EXCEPTION
PRINTSTR("\r\nDERR0=")
cfc0 a0, COP_0_DERR_0
@ -1008,118 +1011,19 @@ gs_2f_v3_ddr2_cfg:
#include "loongson3_fixup.S"
##########################################
/***********************************************************
s1:
|[35:35]| mc1_dimm_type | 1'b1 | registered dual |
| | | 1'b0 | unbuffered dual |
|[34:34]| mc1_ecc | 1'b1 | with data ecc |
| | | 1'b0 | no data ecc |
|[33:33]| mc0_dimm_type | 1'b1 | registered dual |
| | | 1'b0 | unbuffered dual |
|[32:32]| mc0_ecc | 1'b1 | with data ecc |
| | | 1'b0 | no data ecc |
|[31:31]| | 1'b0 | not used |
|[30:28]| mc1_row | mc0_row | 15 - mc1_row_size |
|[27:27]| mc1_eight_bank | 1'b0 | four banks |
| | | 1'b1 | eight banks |
|[26:24]| mc1_col | mc0_col | 14 - mc1_col_size |
|[22:20]| mc0_row | mc0_row | 15 - mc0_row_size |
|[19:19]| mc0_eight_bank | 1'b0 | four banks |
| | | 1'b1 | eight banks |
|[18:16]| mc0_col_size | mc0_col | 14 - col_size |
|[15:12]| mc1_cs_map | | |
|[11: 8]| mc0_cs_map | | |
|[ 7: 7]| ddr_type | 1'b0 | ddr2 |
| | | 1'b1 | ddr3 |
|[ 6: 4]| size_per_controller| 3'b001 | 512mb |
| | | 3'b010 | 1g |
| | | 3'b011 | 2g |
|[ 3: 2]| controller_select | 2'b00 | use both |
| | | 2'b01 | mc0_only |
| | | 2'b10 | mc1_only |
|[ 1: 0]| node id | | |
***********************************************************/
TTYDBG("NODE 0 MEMORY CONFIG BEGIN\r\n")
#define MC0_USED 0x4
#define MC1_USED 0x8
#ifdef AUTO_DDR_CONFIG
/* Open the SMBUS controller */
dli a1,0x90001efdfe00a090 ; #b:d:f:r=0:14:0:90 set tmp config address
li a0,SMBUS_IO_BASE_VALUE | 0x1
sw a0, 0x0(a1);
/* enable the host controller */
dli a1,0x90001efdfe00a0d0 ; #b:d:f:r=0:14:0:d2 bit0=1
lw a0,0x0(a1);
li t1, 0x10000;
or a0, t1
sw a0, 0x0(a1);
PRINTSTR("\r\nProbing DDR SLOT: ");
li s1,0x0
//PRINTSTR("\r\nProbe MC0:JB09: ");
li a0,0xa1;
li a1,MC0_USED;
li a2,0x1
bal PROBE_DIMM;
nop;
//move a0,s1;
//bal hexserial;
//nop;
//PRINTSTR("\r\nProbe MC0:JB10: ");
li a0,0xa3;
li a1,MC0_USED;
li a2,0x1
bal PROBE_DIMM;
nop;
//move a0,s1;
//bal hexserial;
//nop;
//PRINTSTR("\r\nProbe MC1:JB11: ");
li a0,0xa5;
li a1,MC1_USED;
li a2,0x1
bal PROBE_DIMM;
nop;
//move a0,s1;
//bal hexserial;
//nop;
//PRINTSTR("\r\nProbe MC1:JB12: ");
li a0,0xa7;
li a1,MC1_USED;
li a2,0x1
bal PROBE_DIMM;
nop;
/* show value of 64 bit s1 */
move a0,s1;
dsrl a0,32;
bal hexserial;
nop;
PRINTSTR("_");
move a0,s1;
bal hexserial;
nop;
PRINTSTR("\r\n");
#else
li s1, 0x14140c24
#endif
TTYDBG("NODE 0 MEMORY CONFIG BEGIN\r\n")
li s1, 0x0
#include "loongson3_ddr2_config.S"
##########################################
#ifdef MULTI_CHIP
##########################################
#ifdef MULTI_CHIP
TTYDBG("NODE 1 MEMORY CONFIG BEGIN\r\n")
li s1, 0x1
#include "loongson3_ddr2_config.S"
##########################################
#endif
##########################################
//cww
//#include "3adawning_fixup.S"
@ -1313,10 +1217,17 @@ PRINTSTR("Jump to 9fc\r\n")
PRINTSTR("\r\n")
#endif
##########################################
//cxk: put Test Memory code here
GET_DEBUG_MEM
beqz a0, 311f
nop
//#include "Test_Mem.S"
311:
##########################################
##########################################
#include "machine/newtest/mydebug.S"
##########################################
bootnow:
@ -1326,6 +1237,16 @@ bootnow:
la a0, start
bal hexserial
nop
TTYDBG("\r\n _end = 0x")
la a0, _end
bal hexserial
nop
TTYDBG("\r\n _edata = 0x")
la a0, _edata
bal hexserial
nop
TTYDBG("\r\n")
TTYDBG("\r\n s0 = 0x")
move a0, s0
bal hexserial
@ -1598,6 +1519,57 @@ LEAF(outstring)
nop
END(outstring)
LEAF(hexserial64_1) //added by cxk
/**********************
!!specially written for DEBUG_MEM
input: t1: read address(read only)
t0: expected data(read only)
t4: read data
use reg:t5, t7
***********************/
move t7,ra
TTYDBG("\r\naddr 0x")
dsrl a0, t1, 32
bal hexserial
nop
move a0, t1
bal hexserial
nop
TTYDBG(" expected: ")
dsrl a0, t0, 32
bal hexserial
nop
move a0, t0
bal hexserial
nop
TTYDBG(" read: ")
dsrl a0, t4, 32
bal hexserial
nop
move a0, t4
bal hexserial
nop
/* reread the wrong byte, use uncached address*/
TTYDBG(" reread: ")
dli t5, 0xf7ffffffffffffff
and t5, t1, t5
ld t5, 0(t5)
nop
dsrl a0, t5, 32
bal hexserial
nop
move a0, t5
bal hexserial
nop
/* if the reread value differs the first read, print mark */
beq t4, t5, 2f
nop
TTYDBG(" DDD")
2:
TTYDBG("\r\n")
jr t7
nop
END(hexserial64_1)
LEAF(hexserial)
move a2, ra
move a1, a0
@ -2429,713 +2401,5 @@ idle1000:
#endif
#if 0 //cww for 3adawning
#include "loongson3a_ddr_config.S"
#else
#######################################
#define REG_ADDRESS 0x0
//#define CONFIG_BASE 0xaff00000
//#define CONFIG_BASE 0x900000002ff00000
#define CONFIG_BASE 0x900000000ff00000
.global ddr2_config
.ent ddr2_config
.set noreorder
.set mips3
ddr2_config:
/*get a 8-byte number from the keyboard*/
/*
move t8, a0
move t1, ra
PRINTSTR("Please input hex :\r\n");
li t6, 0x00
bal inputaddress #input value stored in v0
nop
move t5, v0 #store v0 to t5
move a0, t8
move ra, t1
*/
la a2, ddr2_reg_data
addu a2, a2, s0
li t1, 152 ##0x72
//li t1, 0x8f #first half loop #152 ##0x72 #TTTTTTTTTTTTTT
#dli v0, CONFIG_BASE
#move v0, a0 #old:li v0, CONFIG_BASE
daddiu v0, a0, 0x0
reg_write:
ld a1, 0x0(a2)
sd a1, REG_ADDRESS(v0)
subu t1, t1, 0x1
addiu a2, a2, 0x8
bne t1, $0, reg_write
daddiu v0, v0, 0x10
/*
#write the register parameter specified by the keyboard input
sd t5, REG_ADDRESS(v0)
li t1, 151-0x8f #TTTTTTTTTTT***change the register to be specified
addiu a2, a2, 0x8
daddiu v0, v0, 0x10
1:
ld a1, 0x0(a2)
sd a1, REG_ADDRESS(v0)
subu t1, t1, 0x1
addiu a2, a2, 0x8
bne t1, $0, 1b
daddiu v0, v0, 0x10
*/
li v0, 0xfff
1:
bnez v0, 1b
addi v0, v0, -1
nop
sync
############start##########
#dli v0, CONFIG_BASE
#move v0, a0 #old:li v0, CONFIG_BASE
daddiu v0, a0, 0x0
la a2,MC0_CTL_start_DATA_LO
#la a2,ddr2_start_reg
addu a2, a2, s0
ld a1, 0x0(a2)
sd a1, 0x30(v0)
daddiu v0, a0, 0x960 //wait int status
1:
ld a1, 0x0(v0)
andi a1, a1, 0x100
beqz a1, 1b
nop
daddiu v0, a0, 0x30 //Set to srefresh
dli a1, 0x0000000100000000
ld a2, 0x0(v0)
or a1, a1, a2
sd a1, 0x0(v0)
li v0, 0xfff
1:
bnez v0, 1b
addi v0, v0, -1
nop
sync
daddiu v0, a0, 0x30 //Out of srefresh
dli a1, 0xffffff00ffffffff
ld a2, 0x0(v0)
and a1, a1, a2
sd a1, 0x0(v0)
li v0, 0xfff
1:
bnez v0, 1b
addi v0, v0, -1
nop
sync
daddiu v0, a0, 0x40 //Write mode regs
dli a1, 0x0000000001000000
ld a2, 0x0(v0)
or a1, a1, a2
sd a1, 0x0(v0)
jr ra
nop
.end ddr2_config
.global ddr2_config_mc1
.ent ddr2_config_mc1
.set noreorder
.set mips3
ddr2_config_mc1:
/*get a 8-byte number from the keyboard*/
/*
move t8, a0
move t1, ra
PRINTSTR("Please input hex :\r\n");
li t6, 0x00
bal inputaddress #input value stored in v0
nop
move t5, v0 #store v0 to t5
move a0, t8
move ra, t1
*/
la a2, ddr2_reg_data_mc1
addu a2, a2, s0
li t1, 152 ##0x72
//li t1, 0x8f #first half loop #152 ##0x72 #TTTTTTTTTTTTTT
#dli v0, CONFIG_BASE
#move v0, a0 #old:li v0, CONFIG_BASE
daddiu v0, a0, 0x0
reg_write_mc1:
ld a1, 0x0(a2)
sd a1, REG_ADDRESS(v0)
subu t1, t1, 0x1
addiu a2, a2, 0x8
bne t1, $0, reg_write_mc1
daddiu v0, v0, 0x10
/*
#write the register parameter specified by the keyboard input
sd t5, REG_ADDRESS(v0)
li t1, 151-0x8f #TTTTTTTTTTT***change the register to be specified
addiu a2, a2, 0x8
daddiu v0, v0, 0x10
1:
ld a1, 0x0(a2)
sd a1, REG_ADDRESS(v0)
subu t1, t1, 0x1
addiu a2, a2, 0x8
bne t1, $0, 1b
daddiu v0, v0, 0x10
*/
li v0, 0xfff
1:
bnez v0, 1b
addi v0, v0, -1
nop
sync
############start##########
#dli v0, CONFIG_BASE
#move v0, a0 #old:li v0, CONFIG_BASE
daddiu v0, a0, 0x0
la a2,MC1_CTL_start_DATA_LO
#la a2,ddr2_start_reg
addu a2, a2, s0
ld a1, 0x0(a2)
sd a1, 0x30(v0)
daddiu v0, a0, 0x960 //wait int status
1:
ld a1, 0x0(v0)
andi a1, a1, 0x100
beqz a1, 1b
nop
daddiu v0, a0, 0x30 //Set to srefresh
dli a1, 0x0000000100000000
ld a2, 0x0(v0)
or a1, a1, a2
sd a1, 0x0(v0)
li v0, 0xfff
1:
bnez v0, 1b
addi v0, v0, -1
nop
sync
daddiu v0, a0, 0x30 //Out of srefresh
dli a1, 0xffffff00ffffffff
ld a2, 0x0(v0)
and a1, a1, a2
sd a1, 0x0(v0)
li v0, 0xfff
1:
bnez v0, 1b
addi v0, v0, -1
nop
sync
daddiu v0, a0, 0x40 //Write mode regs
dli a1, 0x0000000001000000
ld a2, 0x0(v0)
or a1, a1, a2
sd a1, 0x0(v0)
jr ra
nop
.end ddr2_config_mc1
.rdata
.align 5
.global ddr2_reg_data
ddr2_reg_data:
MC0_CTL_000 : .dword 0x0000000000000101
//000000000000000_0 concurrentap(RW) 0000000_1 bank_split_en(RW) 0000000_0 auto_refresh_mode(RW) 0000000_0 arefresh(WR) 0000000_0 ap(RW) 0000000_1 addr_cmp_en(RW) 0000000_1 active_aging(RW)
MC0_CTL_010 : .dword 0x0001000100010000
//0000000_0 fwc(WR) 0000000_0 fast_write(RW) 0000000_1 enable_quick_srefresh(RW) 0000000_1 eight_bank_mode(RW) 0000000_0 ecc_disable_w_uc_err(RW) 0000000_1 dqs_n_en(RW) 0000000_0 dll_bypass_mode(RW) 0000000_0 dlllockreg(RD)
MC0_CTL_020 : .dword 0x0100010101000000
//0000000_1 priority_en(RW) 0000000_0 power_down(RW) 0000000_1 placement_en(RW) 0000000_1 odt_add_turn_clk_en(RW) 0000000_0 no_cmd_init(RW) 0000000_0 intrptwritea(RW) 0000000_0 intrptreada(RW) 0000000_0 intrptapburst(RW)
MC0_CTL_030 : .dword 0x0101000001000000
//0000000_1 swap_port_rw_same_en(RW) 0000000_1 swap_en(RW) 0000000_0 start(RW) 0000000_0 srefresh(RW+) 0000000_1 rw_same_en(RW) 0000000_0 reg_dimm_enable(RW) 0000000_0 reduc(RW) 0000000_0 pwrup_srefresh_exit(RW)
MC0_CTL_040 : .dword 0x0100010200010101
//000000_01 rtt_0(RW) 000000_11 ctrl_raw(RW) 000000_01 axi0_w_priority(RW) 000000_01 axi0_r_priority(RW) 0000000_0 write_modereg(WR) 0000000_1 writeinterp(RW) 0000000_1 tref_enable(RW) 0000000_1 tras_lockout(RW)
MC0_CTL_050 : .dword 0x0000000404050100
//00000_000 q_fullness(RW) 00000_000 port_data_error_type(RD) 000_00000 out_of_range_type(RD) 00000_000 max_cs_reg(RD) 00000_100 column_size(RW) 0000_0101 caslat(RW) 00000_010 addr_pins(RW) 00000000
MC0_CTL_060 : .dword 0x0a04040603040003
//0000_1010 aprebit(RW) 0000_0101 wrlat(RW) 0000_0100 twtr(RW) 000_00110 twr_int(RW) 00000_011 trtp(RW) 00000_100 trrd(RW) 0000000000000_011 tcke(RW)
MC0_CTL_070 : .dword 0x0f0e020000010a08
//0000_0000 max_row_reg(RD) 0000_0000 max_col_reg(RD) 0000_0000 initaref(RW) 00000000000000000000_1111 cs_map(RW) 000_01010 caslat_lin_gate(RW) 000_01010 caslat_lin(RW)
MC0_CTL_080 : .dword 0x0004020100000000
//0000_0001 odt_wr_map_cs3(RW) 0000_0010 odt_wr_map_cs2(RW) 0000_0100 odt_wr_map_cs1(RW) 0000_1000 odt_wr_map_cs0(RW) 0000_0001 odt_rd_map_cs3(RW) 0000_0010 odt_rd_map_cs2(RW) 0000_0100 odt_rd_map_cs1(RW) 0000_1000 odt_rd_map_cs0(RW)
MC0_CTL_090 : .dword 0x0000050b00000000
//000_00000 ocd_adjust_pup_cs_0(RW) 000_00000 ocd_adjust_pdn_cs_0(RW) 0000_0101 trp(RW) 000_01011 tdal(RW) 000000000000_0000 port_cmd_error_type(RD) 0000000000000000
MC0_CTL_0a0 : .dword 0x0000003f3f140612
//MC0_CTL_0a0 : .dword 0x0000003f3f14021b
//00000000000000000000000000_111111 command_age_count(RW) 00_111111 age_count(RW) 000_10100 trc(RW) 000_00110 tmrd(RW) 000_10010 tfaw(RW)
MC0_CTL_0b0 : .dword 0x0000000000000000
MC0_CTL_0c0 : .dword 0x00002c050f000000
//000000000000000000101100 trfc(RW) 00000101 trcd_int(RW) 00001111 tras_min(RW) 00000000 out_of_range_length(RD) 00000000 ecc_u_synd(RD) 00000000 ecc_c_synd(RD)
MC0_CTL_0d0 : .dword 0x0000000000000000
MC0_CTL_0e0 : .dword 0x0000000000000000
MC0_CTL_0f0 : .dword 0x0000000000000000
MC0_CTL_100 : .dword 0x0000000000000000
MC0_CTL_110 : .dword 0x000000000000052d
//0_000000000000000 emrs2_data_1(RW) 0_000000000000000 emrs2_data_0(RW) 000000000000000000_00110000101101 tref(RW)
MC0_CTL_120 : .dword 0xffff000000000000
//0000000000011100 axi0_en_size_lt_width_instr(RW) 00000000000000000_000000000000000 emrs2_data_3(RW) 0_000000000000000 emrs2_data_2(RW)
MC0_CTL_130 : .dword 0x0d56000302000000
//0110110101010110 tras_max(RW) 0000000000000011 tpdex(RW) 0000001000000000 tdll(RW) 0000000000000000 tcpd(RW)
MC0_CTL_140 : .dword 0x0000204002000030
//0000000000000000 xor_check_bits(RW) 0000000000000000 version(RD) 0000001000000000 txsr(RW) 0000000000110000 txsnr(RW)
MC0_CTL_150 : .dword 0x0000000011000004
//000_0000000000000000000000000000000000000 ecc_c_addr(RD) 000000000000000000011011 tinit(RW)
MC0_CTL_160 : .dword 0x0000000000000000
//000000000000000000000000000_0000000000000000000000000000000000000 ecc_u_addr(RD)
MC0_CTL_170 : .dword 0x0000000000000000
//000000000000000000000000000_0000000000000000000000000000000000000 out_of_range_addr(RD)
MC0_CTL_180 : .dword 0x0000000000000000
//000000000000000000000000000_0000000000000000000000000000000000000 port_cmd_error_addr(RD)
MC0_CTL_190 : .dword 0x0000000000000000
//0000000000000000000000000000000000000000000000000000000000000000 ecc_c_data(RD)
MC0_CTL_1a0 : .dword 0x0000000000000000
//0000000000000000000000000000000000000000000000000000000000000000 ecc_u_data(RD)
MC0_CTL_1b0 : .dword 0x0000000000000000
//0000000000000000000000000000000000000000000000000000000000000_000 cke_delay(RW)
MC0_CTL_1c0 : .dword 0x0000000000000000
MC0_CTL_1d0 : .dword 0x0203070400000101
//0000_0010 tdfi_phy_wrlat_base(RW) 0000_0000 tdfi_phy_wrlat(RD) 000_00111 tdfi_phy_rdlat(RW) 0000_0000 tdfi_ctrlupd_min(RD) 000000000000_0000 dram_clk_disable(RW) 0000000_1 odt_alt_en(RW) 0000000_1 drive_dq_dqs(RW)
MC0_CTL_1e0 : .dword 0x0c2d0c2d0c2d0205
//00_00000000000000 tdfi_phyupd_type0(RD) 00_00000000000000 tdfi_phyupd_resp(RD) 00_00000000000000 tdfi_ctrlupd_max(RD) 000_00000 tdfi_rddata_en_base(RW) 000_00000 tdfi_rddata_en(RD)
MC0_CTL_1f0 : .dword 0x00120d8000000000
MC0_CTL_200 : .dword 0x00120d8000120d80
MC0_CTL_210 : .dword 0x0012108000121080
//00000000001000000000111510000000 dll_ctrl_reg_0_4(RW) 00000000001000000000111010000000 dll_ctrl_reg_0_3(RW)
MC0_CTL_220 : .dword 0x000f1080000f1080
//00000000001000000000111510000000 dll_ctrl_reg_0_6(RW) 00000000001000000000111010000000 dll_ctrl_reg_0_5(RW)
MC0_CTL_230 : .dword 0x000f1080000f1080
MC0_CTL_240 : .dword 0x0000250000002500
//00000000000000000000111000000000 dll_ctrl_reg_1_1(RW) 00000000000000000000111000000000 dll_ctrl_reg_1_0(RW)
MC0_CTL_250 : .dword 0x0000250000002200
MC0_CTL_260 : .dword 0x0000220000002200
MC0_CTL_270 : .dword 0x0000220000002200
MC0_CTL_280 : .dword 0x0000000000002200
MC0_CTL_290 : .dword 0x0000000000000000
MC0_CTL_2a0 : .dword 0x0000000000000000
MC0_CTL_2b0 : .dword 0x0000000000000000
MC0_CTL_2c0 : .dword 0x0000000000000000
MC0_CTL_2d0 : .dword 0xf300484403fc09b4
//11110100000000000011101100100111 phy_ctrl_reg_0_0(RD) 000000_00000000000000000110011101 pad_ctrl_reg_0(RW)
MC0_CTL_2e0 : .dword 0xf3004844f3004844
MC0_CTL_2f0 : .dword 0xf3004844f3004844
MC0_CTL_300 : .dword 0xf3004844f3004844
MC0_CTL_310 : .dword 0xf3004844f3004844
//MC0_CTL_2d0 : .dword 0xf3005a470000019d
////11110100000000000011101100100111 phy_ctrl_reg_0_0(RD) 000000_00000000000000000110011101 pad_ctrl_reg_0(RW)
//MC0_CTL_2e0 : .dword 0xf3005a47f3005a47
//MC0_CTL_2f0 : .dword 0xf3005a47f3005a47
//MC0_CTL_300 : .dword 0xf3005a47f3005a47
//MC0_CTL_310 : .dword 0xf3005a47f3005a47
MC0_CTL_320 : .dword 0x26c0000126c00001
MC0_CTL_330 : .dword 0x26c0000126c00001
MC0_CTL_340 : .dword 0x26c0000126c00001
MC0_CTL_350 : .dword 0x26c0000126c00001
MC0_CTL_360 : .dword 0x0800c00526c00001
//00000000000000001100000000000101 phy_ctrl_reg_2(RW) 00000111110000000000001100000001 phy_ctrl_reg_1_8(RD)
MC0_CTL_370 : .dword 0x0000000000000000
MC0_CTL_380 : .dword 0x0000000000000000
MC0_CTL_390 : .dword 0x0000000000000000
MC0_CTL_3a0 : .dword 0x0000000000000000
MC0_CTL_3b0 : .dword 0x0000000000000000
MC0_CTL_3c0 : .dword 0x0000000000000000
MC0_CTL_3d0 : .dword 0x0000000000000000
MC0_CTL_3e0 : .dword 0x0000000000000000
MC0_CTL_3f0 : .dword 0x0000000000000000
MC0_CTL_400 : .dword 0x0000000000000000
MC0_CTL_410 : .dword 0x0000000000000000
MC0_CTL_420 : .dword 0x0000000000000000
MC0_CTL_430 : .dword 0x0000000000000000
MC0_CTL_440 : .dword 0x0000000000000000
MC0_CTL_450 : .dword 0x0000000000000000
MC0_CTL_460 : .dword 0x0000000000000000
MC0_CTL_470 : .dword 0x0000000000000000
MC0_CTL_480 : .dword 0x0000000000000000
MC0_CTL_490 : .dword 0x0000000000000000
MC0_CTL_4a0 : .dword 0x0000000000000000
MC0_CTL_4b0 : .dword 0x0000000000000000
MC0_CTL_4c0 : .dword 0x0000000000000000
MC0_CTL_4d0 : .dword 0x0000000000000000
MC0_CTL_4e0 : .dword 0x0000000000000000
MC0_CTL_4f0 : .dword 0x0000000000000000
MC0_CTL_500 : .dword 0x0000000000000000
MC0_CTL_510 : .dword 0x0000000000000000
MC0_CTL_520 : .dword 0x0000000000000000
MC0_CTL_530 : .dword 0x0000000000000000
MC0_CTL_540 : .dword 0x0000000000000000
MC0_CTL_550 : .dword 0x0000000000000000
MC0_CTL_560 : .dword 0x0000000000000000
MC0_CTL_570 : .dword 0x0000000000000000
MC0_CTL_580 : .dword 0x0000000000000000
MC0_CTL_590 : .dword 0x0000000000000000
MC0_CTL_5a0 : .dword 0x0000000000000000
MC0_CTL_5b0 : .dword 0x0000000000000000
MC0_CTL_5c0 : .dword 0x0000000000000000
MC0_CTL_5d0 : .dword 0x0000000000000000
MC0_CTL_5e0 : .dword 0x0000000000000000
MC0_CTL_5f0 : .dword 0x0000000000000000
MC0_CTL_600 : .dword 0x0000000000000000
MC0_CTL_610 : .dword 0x0000000000000000
MC0_CTL_620 : .dword 0x0000000000000000
MC0_CTL_630 : .dword 0x0000000000000000
MC0_CTL_640 : .dword 0x0000000000000000
MC0_CTL_650 : .dword 0x0000000000000000
MC0_CTL_660 : .dword 0x0000000000000000
MC0_CTL_670 : .dword 0x0000000000000000
MC0_CTL_680 : .dword 0x0000000000000000
MC0_CTL_690 : .dword 0x0000000000000000
MC0_CTL_6a0 : .dword 0x0000000000000000
MC0_CTL_6b0 : .dword 0x0000000000000000
MC0_CTL_6c0 : .dword 0x0000000000000000
MC0_CTL_6d0 : .dword 0x0000000000000000
MC0_CTL_6e0 : .dword 0x0000000000000000
MC0_CTL_6f0 : .dword 0x0000000000000000
MC0_CTL_700 : .dword 0x0000000000000000
MC0_CTL_710 : .dword 0x0000000000000000
MC0_CTL_720 : .dword 0x0000000000000000
MC0_CTL_730 : .dword 0x0000000000000000
MC0_CTL_740 : .dword 0x0100000000000000
//MC0_CTL_750 : .dword 0x0100000101020101
MC0_CTL_750 : .dword 0x0101000101020101
//000000_01 wrlvl_cs(RW) 000000_00 sw_leveling_mode(RW) 000000_00 rdlvl_cs(RW) 000000_01 axi2_w_priority(RW) 000000_01 axi2_r_priority(RW) 000000_10 axi2_port_ordering(RW) 000000_01 axi1_w_priority(RW) 000000_01 axi1_r_priority(RW)
MC0_CTL_760 : .dword 0x0303030000020001
//0000_0011 axi0_priority2_relative_priority(RW) 0000_0011 axi0_priority1_relative_priority(RW) 0000_0011 axi0_priority0_relative_priority(RW) 0000_0000 address_mirroring(RW) 00000_000 tdfi_dram_clk_disable(RW) 00000_010 bstlen(RW) 000000_00 zq_req(WR) 000000_01 zq_on_sref_exit(RW)
MC0_CTL_770 : .dword 0x0101010202020203
//0000_0001 axi2_priority2_relative_priority(RW) 0000_0001 axi2_priority1_relative_priority(RW) 0000_0001 axi2_priority0_relative_priority(RW) 0000_0010 axi1_priority3_relative_priority(RW) 0000_0010 axi1_priority2_relative_priority(RW) 0000_0010 axi1_priority1_relative_priority(RW) 0000_0010 axi1_priority0_relative_priority(RW) 0000_0011 axi0_priority3_relative_priority(RW)
MC0_CTL_780 : .dword 0x0102020400040001
//0000_0001 tdfi_dram_clk_enable(RW) 0000_0010 tdfi_ctrl_delay(RW) 0000_0010 rdlvl_gate_dq_zero_count(RW) 0000_0100 rdlvl_dq_zero_count(RW) 0000_0000 lowpower_refresh_enable(RW) 0000_0110 dram_class(RW) 0000_1100 burst_on_fly_bit(RW) 0000_0001 axi2_priority3_relative_priority(RW)
MC0_CTL_790 : .dword 0x281900000f000303
//00_101000 wlmrd(RW) 00_011001 wldqsen(RW) 000_00000 lowpower_control(RW) 000_00000 lowpower_auto_enable(RW) 0000_1111 zqcs_chip(RW) 0000_0000 wrr_param_value_err(RD) 0000_0011 tdfi_wrlvl_dll(RW) 0000_0011 tdfi_rdlvl_dll(RW)
MC0_CTL_7a0 : .dword 0x00000000000000ff
MC0_CTL_7b0 : .dword 0x0000000000000000
MC0_CTL_7c0 : .dword 0x0000000000000000
MC0_CTL_7d0 : .dword 0x0000000000000000
MC0_CTL_7e0 : .dword 0x0000000000000000
//00000000 rdlvl_gate_delay_2(RD) 00000000 rdlvl_gate_delay_1(RD) 00000000 rdlvl_gate_delay_0(RD) 00000000 rdlvl_gate_clk_adjust_8(RW) 00000000 rdlvl_gate_clk_adjust_7(RW) 00000000 rdlvl_gate_clk_adjust_6(RW) 00000000 rdlvl_gate_clk_adjust_5(RW) 00000000 rdlvl_gate_clk_adjust_4(RW)
MC0_CTL_7f0 : .dword 0xff08000000000000
//11111111 rdlvl_max_delay(RW) 00001000 rdlvl_gate_max_delay(RW) 00000000 rdlvl_gate_delay_8(RD) 00000000 rdlvl_gate_delay_7(RD) 00000000 rdlvl_gate_delay_6(RD) 00000000 rdlvl_gate_delay_5(RD) 00000000 rdlvl_gate_delay_4(RD) 00000000 rdlvl_gate_delay_3(RD)
MC0_CTL_800 : .dword 0x0000000000000000
//00000000 rdlvl_midpoint_delay_7(RD) 00000000 rdlvl_midpoint_delay_6(RD) 00000000 rdlvl_midpoint_delay_5(RD) 00000000 rdlvl_midpoint_delay_4(RD) 00000000 rdlvl_midpoint_delay_3(RD) 00000000 rdlvl_midpoint_delay_2(RD) 00000000 rdlvl_midpoint_delay_1(RD) 00000000 rdlvl_midpoint_delay_0(RD)
MC0_CTL_810 : .dword 0x0000000000000000
//00000000 rdlvl_offset_delay_6(RW) 00000000 rdlvl_offset_delay_5(RW) 00000000 rdlvl_offset_delay_4(RW) 00000000 rdlvl_offset_delay_3(RW) 00000000 rdlvl_offset_delay_2(RW) 00000000 rdlvl_offset_delay_1(RW) 00000000 rdlvl_offset_delay_0(RW) 00000000 rdlvl_midpoint_delay_8(RD)
MC0_CTL_820 : .dword 0x0420000c20400000
//00000100 tdfi_wrlvl_resplat(RW) 00000000 tdfi_wrlvl_resp(RD) 00000000 tdfi_rdlvl_rr(RW) 00001100 tdfi_rdlvl_resplat(RW) 00000000 tdfi_rdlvl_resp(RD) 01000000 refresh_per_zq(RW) 00000000 rdlvl_offset_delay_8(RW) 00000000 rdlvl_offset_delay_7(RW)
//MC0_CTL_830 : .dword 0x0000000000000c0a
MC0_CTL_830 : .dword 0x282a2a2525250c0a
//00000000 wrlvl_delay_5(RD) 00000000 wrlvl_delay_4(RD) 00000000 wrlvl_delay_3(RD) 00000000 wrlvl_delay_2(RD) 00000000 wrlvl_delay_1(RD) 00000000 wrlvl_delay_0(RD) 00000010 tmod(RW) 00001010 tdfi_wrlvl_ww(RW)
MC0_CTL_840 : .dword 0x0000640064002828 # 3A2
//00000000000000_0001100100 axi1_priority_relax(RW) 000000_0001100100 axi0_priority_relax(RW) 00000000 wrlvl_delay_8(RD) 00000000 wrlvl_delay_7(RD) 00000000 wrlvl_delay_6(RD)
MC0_CTL_850 : .dword 0x0000000000000064
MC0_CTL_860 : .dword 0x0200004000000000
MC0_CTL_870 : .dword 0x0046004600460046
//0_000000000000010 emrs1_data_3(RW) 0_000000000000010 emrs1_data_2(RW) 0_000000000000010 emrs1_data_1(RW) 0_000000000000010 emrs1_data_0(RW)
MC0_CTL_880 : .dword 0x0000000000000000
MC0_CTL_890 : .dword 0x0a520a520a520a52
//0_000010000010000 mrs_data_3(RW) 0_000010000010000 mrs_data_2(RW) 0_000010000010000 mrs_data_1(RW) 0_000010000010000 mrs_data_0(RW)
MC0_CTL_8a0 : .dword 0x00000000001c001c
MC0_CTL_8b0 : .dword 0x0000000000000000
MC0_CTL_8c0 : .dword 0x0004000000000000
MC0_CTL_8d0 : .dword 0x00000000c8000000
MC0_CTL_8e0 : .dword 0x0000000000000050
//MC0_CTL_8f0 : .dword 0x0000000020202080
//MC0_CTL_8f0 : .dword 0x000000002b352180
MC0_CTL_8f0 : .dword 0x000000002a2a2a80 //clk skew of 3A2 0.4
//MC0_CTL_8f0 : .dword 0x0000000040404080
//0000000000000000000000000111100_000000000000000000000000001111000 dll_ctrl_reg_2(RW)
MC0_CTL_900 : .dword 0x0000000000000000
MC0_CTL_910 : .dword 0x0000000000000000
MC0_CTL_920 : .dword 0x0000000000000000
MC0_CTL_930 : .dword 0x0000000000000000
MC0_CTL_940 : .dword 0x0306060000050500
MC0_CTL_950 : .dword 0x0000000000000a03
MC0_CTL_960 : .dword 0x0604000100000000
//000_00101 rdlat_adj(RW) 0000_0100 wrlat_adj(RW) 0000000_0 swlvl_start(WR) 0000000_0 swlvl_load(WR) 0000000_0 swlvl_exit(WR) 000000_000000000000000000 int_status(RD)
MC0_CTL_970 : .dword 0x000000000003e805
MC0_CTL_start_DATA_LO: .word 0x00000000
//0000000_1 rw_same_en 0000000_0 reg_dimm_enable 0000000_0 reduc 0000000_0 pwrup_srefresh_exit
MC0_CTL_start_DATA_HI: .word 0x01010100
//0000000_1 swap_port_rw_same_en 0000000_1 swap_en 0000000_0 start 0000000_0 srefresh
ddr2_reg_data_mc1:
MC1_CTL_000 : .dword 0x0000000000000101
//000000000000000_0 concurrentap(RW) 0000000_1 bank_split_en(RW) 0000000_0 auto_refresh_mode(RW) 0000000_0 arefresh(WR) 0000000_0 ap(RW) 0000000_1 addr_cmp_en(RW) 0000000_1 active_aging(RW)
MC1_CTL_010 : .dword 0x0001000100010000
//0000000_0 fwc(WR) 0000000_0 fast_write(RW) 0000000_1 enable_quick_srefresh(RW) 0000000_1 eight_bank_mode(RW) 0000000_0 ecc_disable_w_uc_err(RW) 0000000_1 dqs_n_en(RW) 0000000_0 dll_bypass_mode(RW) 0000000_0 dlllockreg(RD)
MC1_CTL_020 : .dword 0x0100010101000000
//0000000_1 priority_en(RW) 0000000_0 power_down(RW) 0000000_1 placement_en(RW) 0000000_1 odt_add_turn_clk_en(RW) 0000000_0 no_cmd_init(RW) 0000000_0 intrptwritea(RW) 0000000_0 intrptreada(RW) 0000000_0 intrptapburst(RW)
MC1_CTL_030 : .dword 0x0101000001000000
//0000000_1 swap_port_rw_same_en(RW) 0000000_1 swap_en(RW) 0000000_0 start(RW) 0000000_0 srefresh(RW+) 0000000_1 rw_same_en(RW) 0000000_0 reg_dimm_enable(RW) 0000000_0 reduc(RW) 0000000_0 pwrup_srefresh_exit(RW)
MC1_CTL_040 : .dword 0x0100010200010101
//000000_01 rtt_0(RW) 000000_11 ctrl_raw(RW) 000000_01 axi0_w_priority(RW) 000000_01 axi0_r_priority(RW) 0000000_0 write_modereg(WR) 0000000_1 writeinterp(RW) 0000000_1 tref_enable(RW) 0000000_1 tras_lockout(RW)
MC1_CTL_050 : .dword 0x0000000404050100
//00000_000 q_fullness(RW) 00000_000 port_data_error_type(RD) 000_00000 out_of_range_type(RD) 00000_000 max_cs_reg(RD) 00000_100 column_size(RW) 0000_0101 caslat(RW) 00000_010 addr_pins(RW) 00000000
MC1_CTL_060 : .dword 0x0a04040603040003
//0000_1010 aprebit(RW) 0000_0101 wrlat(RW) 0000_0100 twtr(RW) 000_00110 twr_int(RW) 00000_011 trtp(RW) 00000_100 trrd(RW) 0000000000000_011 tcke(RW)
MC1_CTL_070 : .dword 0x0f0e020000010a08
//0000_0000 max_row_reg(RD) 0000_0000 max_col_reg(RD) 0000_0000 initaref(RW) 00000000000000000000_1111 cs_map(RW) 000_01010 caslat_lin_gate(RW) 000_01010 caslat_lin(RW)
MC1_CTL_080 : .dword 0x0004020100000000
//0000_0001 odt_wr_map_cs3(RW) 0000_0010 odt_wr_map_cs2(RW) 0000_0100 odt_wr_map_cs1(RW) 0000_1000 odt_wr_map_cs0(RW) 0000_0001 odt_rd_map_cs3(RW) 0000_0010 odt_rd_map_cs2(RW) 0000_0100 odt_rd_map_cs1(RW) 0000_1000 odt_rd_map_cs0(RW)
MC1_CTL_090 : .dword 0x0000050b00000000
//000_00000 ocd_adjust_pup_cs_0(RW) 000_00000 ocd_adjust_pdn_cs_0(RW) 0000_0101 trp(RW) 000_01011 tdal(RW) 000000000000_0000 port_cmd_error_type(RD) 0000000000000000
MC1_CTL_0a0 : .dword 0x0000003f3f140612
//00000000000000000000000000_111111 command_age_count(RW) 00_111111 age_count(RW) 000_10100 trc(RW) 000_00110 tmrd(RW) 000_10010 tfaw(RW)
MC1_CTL_0b0 : .dword 0x0000000000000000
MC1_CTL_0c0 : .dword 0x00002c050f000000
//000000000000000000101100 trfc(RW) 00000101 trcd_int(RW) 00001111 tras_min(RW) 00000000 out_of_range_length(RD) 00000000 ecc_u_synd(RD) 00000000 ecc_c_synd(RD)
MC1_CTL_0d0 : .dword 0x0000000000000000
MC1_CTL_0e0 : .dword 0x0000000000000000
MC1_CTL_0f0 : .dword 0x0000000000000000
MC1_CTL_100 : .dword 0x0000000000000000
MC1_CTL_110 : .dword 0x00000000000005cd
//0_000000000000000 emrs2_data_1(RW) 0_000000000000000 emrs2_data_0(RW) 000000000000000000_00110000101101 tref(RW)
MC1_CTL_120 : .dword 0xffff000000000000
//0000000000011100 axi0_en_size_lt_width_instr(RW) 00000000000000000_000000000000000 emrs2_data_3(RW) 0_000000000000000 emrs2_data_2(RW)
MC1_CTL_130 : .dword 0x0d56000302000000
//0110110101010110 tras_max(RW) 0000000000000011 tpdex(RW) 0000001000000000 tdll(RW) 0000000000000000 tcpd(RW)
MC1_CTL_140 : .dword 0x0000204002000030
//0000000000000000 xor_check_bits(RW) 0000000000000000 version(RD) 0000001000000000 txsr(RW) 0000000000110000 txsnr(RW)
MC1_CTL_150 : .dword 0x0000000011000004
//000_0000000000000000000000000000000000000 ecc_c_addr(RD) 000000000000000000011011 tinit(RW)
MC1_CTL_160 : .dword 0x0000000000000000
//000000000000000000000000000_0000000000000000000000000000000000000 ecc_u_addr(RD)
MC1_CTL_170 : .dword 0x0000000000000000
//000000000000000000000000000_0000000000000000000000000000000000000 out_of_range_addr(RD)
MC1_CTL_180 : .dword 0x0000000000000000
//000000000000000000000000000_0000000000000000000000000000000000000 port_cmd_error_addr(RD)
MC1_CTL_190 : .dword 0x0000000000000000
//0000000000000000000000000000000000000000000000000000000000000000 ecc_c_data(RD)
MC1_CTL_1a0 : .dword 0x0000000000000000
//0000000000000000000000000000000000000000000000000000000000000000 ecc_u_data(RD)
MC1_CTL_1b0 : .dword 0x0000000000000000
//0000000000000000000000000000000000000000000000000000000000000_000 cke_delay(RW)
MC1_CTL_1c0 : .dword 0x0000000000000000
MC1_CTL_1d0 : .dword 0x0203070400000101
//0000_0010 tdfi_phy_wrlat_base(RW) 0000_0000 tdfi_phy_wrlat(RD) 000_00111 tdfi_phy_rdlat(RW) 0000_0000 tdfi_ctrlupd_min(RD) 000000000000_0000 dram_clk_disable(RW) 0000000_1 odt_alt_en(RW) 0000000_1 drive_dq_dqs(RW)
MC1_CTL_1e0 : .dword 0x0c2d0c2d0c2d0205
//00_00000000000000 tdfi_phyupd_type0(RD) 00_00000000000000 tdfi_phyupd_resp(RD) 00_00000000000000 tdfi_ctrlupd_max(RD) 000_00000 tdfi_rddata_en_base(RW) 000_00000 tdfi_rddata_en(RD)
MC1_CTL_1f0 : .dword 0x000f108000000000
MC1_CTL_200 : .dword 0x000f1080000f1080
MC1_CTL_210 : .dword 0x000f1280000f1280
//00000000001000000000111510000000 dll_ctrl_reg_0_4(RW) 00000000001000000000111010000000 dll_ctrl_reg_0_3(RW)
MC1_CTL_220 : .dword 0x000f1080000f1080
//00000000001000000000111510000000 dll_ctrl_reg_0_6(RW) 00000000001000000000111010000000 dll_ctrl_reg_0_5(RW)
MC1_CTL_230 : .dword 0x000f1080000f1080
MC1_CTL_240 : .dword 0x0000220000002200
//00000000000000000000111000000000 dll_ctrl_reg_1_1(RW) 00000000000000000000111000000000 dll_ctrl_reg_1_0(RW)
MC1_CTL_250 : .dword 0x0000220000002200
MC1_CTL_260 : .dword 0x0000220000002200
MC1_CTL_270 : .dword 0x0000220000002200
MC1_CTL_280 : .dword 0x0000000000002200
MC1_CTL_290 : .dword 0x0000000000000000
MC1_CTL_2a0 : .dword 0x0000000000000000
MC1_CTL_2b0 : .dword 0x0000000000000000
MC1_CTL_2c0 : .dword 0x0000000000000000
MC1_CTL_2d0 : .dword 0xc400484403fc09b4
//11110100000000000011101100100111 phy_ctrl_reg_0_0(RD) 000000_00000000000000000110011101 pad_ctrl_reg_0(RW)
MC1_CTL_2e0 : .dword 0xc4004844c4004844
MC1_CTL_2f0 : .dword 0xc4004844c4004844
MC1_CTL_300 : .dword 0xc4004844c4004844
MC1_CTL_310 : .dword 0xc4004844c4004844
//MC1_CTL_2d0 : .dword 0xf3005a470000019d
////11110100000000000011101100100111 phy_ctrl_reg_0_0(RD) 000000_00000000000000000110011101 pad_ctrl_reg_0(RW)
//MC1_CTL_2e0 : .dword 0xf3005a47f3005a47
//MC1_CTL_2f0 : .dword 0xf3005a47f3005a47
//MC1_CTL_300 : .dword 0xf3005a47f3005a47
//MC1_CTL_310 : .dword 0xf3005a47f3005a47
MC1_CTL_320 : .dword 0x96c0000196c00001
MC1_CTL_330 : .dword 0x96c0000196c00001
MC1_CTL_340 : .dword 0x96c0000196c00001
MC1_CTL_350 : .dword 0x96c0000196c00001
MC1_CTL_360 : .dword 0x0800e00596c00001
//00000000000000001100000000000101 phy_ctrl_reg_2(RW) 00000111110000000000001100000001 phy_ctrl_reg_1_8(RD)
MC1_CTL_370 : .dword 0x0000000000000000
MC1_CTL_380 : .dword 0x0000000000000000
MC1_CTL_390 : .dword 0x0000000000000000
MC1_CTL_3a0 : .dword 0x0000000000000000
MC1_CTL_3b0 : .dword 0x0000000000000000
MC1_CTL_3c0 : .dword 0x0000000000000000
MC1_CTL_3d0 : .dword 0x0000000000000000
MC1_CTL_3e0 : .dword 0x0000000000000000
MC1_CTL_3f0 : .dword 0x0000000000000000
MC1_CTL_400 : .dword 0x0000000000000000
MC1_CTL_410 : .dword 0x0000000000000000
MC1_CTL_420 : .dword 0x0000000000000000
MC1_CTL_430 : .dword 0x0000000000000000
MC1_CTL_440 : .dword 0x0000000000000000
MC1_CTL_450 : .dword 0x0000000000000000
MC1_CTL_460 : .dword 0x0000000000000000
MC1_CTL_470 : .dword 0x0000000000000000
MC1_CTL_480 : .dword 0x0000000000000000
MC1_CTL_490 : .dword 0x0000000000000000
MC1_CTL_4a0 : .dword 0x0000000000000000
MC1_CTL_4b0 : .dword 0x0000000000000000
MC1_CTL_4c0 : .dword 0x0000000000000000
MC1_CTL_4d0 : .dword 0x0000000000000000
MC1_CTL_4e0 : .dword 0x0000000000000000
MC1_CTL_4f0 : .dword 0x0000000000000000
MC1_CTL_500 : .dword 0x0000000000000000
MC1_CTL_510 : .dword 0x0000000000000000
MC1_CTL_520 : .dword 0x0000000000000000
MC1_CTL_530 : .dword 0x0000000000000000
MC1_CTL_540 : .dword 0x0000000000000000
MC1_CTL_550 : .dword 0x0000000000000000
MC1_CTL_560 : .dword 0x0000000000000000
MC1_CTL_570 : .dword 0x0000000000000000
MC1_CTL_580 : .dword 0x0000000000000000
MC1_CTL_590 : .dword 0x0000000000000000
MC1_CTL_5a0 : .dword 0x0000000000000000
MC1_CTL_5b0 : .dword 0x0000000000000000
MC1_CTL_5c0 : .dword 0x0000000000000000
MC1_CTL_5d0 : .dword 0x0000000000000000
MC1_CTL_5e0 : .dword 0x0000000000000000
MC1_CTL_5f0 : .dword 0x0000000000000000
MC1_CTL_600 : .dword 0x0000000000000000
MC1_CTL_610 : .dword 0x0000000000000000
MC1_CTL_620 : .dword 0x0000000000000000
MC1_CTL_630 : .dword 0x0000000000000000
MC1_CTL_640 : .dword 0x0000000000000000
MC1_CTL_650 : .dword 0x0000000000000000
MC1_CTL_660 : .dword 0x0000000000000000
MC1_CTL_670 : .dword 0x0000000000000000
MC1_CTL_680 : .dword 0x0000000000000000
MC1_CTL_690 : .dword 0x0000000000000000
MC1_CTL_6a0 : .dword 0x0000000000000000
MC1_CTL_6b0 : .dword 0x0000000000000000
MC1_CTL_6c0 : .dword 0x0000000000000000
MC1_CTL_6d0 : .dword 0x0000000000000000
MC1_CTL_6e0 : .dword 0x0000000000000000
MC1_CTL_6f0 : .dword 0x0000000000000000
MC1_CTL_700 : .dword 0x0000000000000000
MC1_CTL_710 : .dword 0x0000000000000000
MC1_CTL_720 : .dword 0x0000000000000000
//0000000_0 rdlvl_gate_req(WR) 0000000_0 rdlvl_gate_preamble_check_en(RW) 0000000_0 rdlvl_gate_en(RW) 0000000_0 rdlvl_en(RW) 0000000_0 rdlvl_begin_delay_en(RW) 000000000000000_0 swlvl_op_done(RD) 00000000
MC1_CTL_730 : .dword 0x0000000000000000
//0000000_0 rdlvl_offset_dir_7(RW) 0000000_0 rdlvl_offset_dir_6(RW) 0000000_0 rdlvl_offset_dir_5(RW) 0000000_0 rdlvl_offset_dir_4(RW) 0000000_0 rdlvl_offset_dir_3(RW) 0000000_0 rdlvl_offset_dir_2(RW) 0000000_0 rdlvl_offset_dir_1(RW) 0000000_0 rdlvl_offset_dir_0(RW)
MC1_CTL_740 : .dword 0x0100000000000000
//000000_01 axi1_port_ordering(RW) 000000_00 axi0_port_ordering(RW) 0000000_0 wrlvl_req(WR) 0000000_0 wrlvl_interval_ct_en(RW) 0000000_0 weighted_round_robin_weight_sharing(RW) 0000000_0 weighted_round_robin_latency_control(RW) 0000000_0 rdlvl_req(WR) 0000000_0 rdlvl_offset_dir_8(RW)
//MC1_CTL_750 : .dword 0x0100000101020101
MC1_CTL_750 : .dword 0x0101000101020101
//000000_01 wrlvl_cs(RW) 000000_00 sw_leveling_mode(RW) 000000_00 rdlvl_cs(RW) 000000_01 axi2_w_priority(RW) 000000_01 axi2_r_priority(RW) 000000_10 axi2_port_ordering(RW) 000000_01 axi1_w_priority(RW) 000000_01 axi1_r_priority(RW)
MC1_CTL_760 : .dword 0x0303030000020001
//0000_0011 axi0_priority2_relative_priority(RW) 0000_0011 axi0_priority1_relative_priority(RW) 0000_0011 axi0_priority0_relative_priority(RW) 0000_0000 address_mirroring(RW) 00000_000 tdfi_dram_clk_disable(RW) 00000_010 bstlen(RW) 000000_00 zq_req(WR) 000000_01 zq_on_sref_exit(RW)
MC1_CTL_770 : .dword 0x0101010202020203
//0000_0001 axi2_priority2_relative_priority(RW) 0000_0001 axi2_priority1_relative_priority(RW) 0000_0001 axi2_priority0_relative_priority(RW) 0000_0010 axi1_priority3_relative_priority(RW) 0000_0010 axi1_priority2_relative_priority(RW) 0000_0010 axi1_priority1_relative_priority(RW) 0000_0010 axi1_priority0_relative_priority(RW) 0000_0011 axi0_priority3_relative_priority(RW)
MC1_CTL_780 : .dword 0x0102020400040001
//0000_0001 tdfi_dram_clk_enable(RW) 0000_0010 tdfi_ctrl_delay(RW) 0000_0010 rdlvl_gate_dq_zero_count(RW) 0000_0100 rdlvl_dq_zero_count(RW) 0000_0000 lowpower_refresh_enable(RW) 0000_0110 dram_class(RW) 0000_1100 burst_on_fly_bit(RW) 0000_0001 axi2_priority3_relative_priority(RW)
MC1_CTL_790 : .dword 0x281900000f000303
//00_101000 wlmrd(RW) 00_011001 wldqsen(RW) 000_00000 lowpower_control(RW) 000_00000 lowpower_auto_enable(RW) 0000_1111 zqcs_chip(RW) 0000_0000 wrr_param_value_err(RD) 0000_0011 tdfi_wrlvl_dll(RW) 0000_0011 tdfi_rdlvl_dll(RW)
MC1_CTL_7a0 : .dword 0x00000000000000ff
//00000000 swlvl_resp_6(RD) 00000000 swlvl_resp_5(RD) 00000000 swlvl_resp_4(RD) 00000000 swlvl_resp_3(RD) 00000000 swlvl_resp_2(RD) 00000000 swlvl_resp_1(RD) 00000000 swlvl_resp_0(RD) 11111111 dfi_wrlvl_max_delay(RW)
MC1_CTL_7b0 : .dword 0x0000000000000000
MC1_CTL_7c0 : .dword 0x0000000000000000
MC1_CTL_7d0 : .dword 0x0000000000000000
MC1_CTL_7e0 : .dword 0x0000000000000000
//00000000 rdlvl_gate_delay_2(RD) 00000000 rdlvl_gate_delay_1(RD) 00000000 rdlvl_gate_delay_0(RD) 00000000 rdlvl_gate_clk_adjust_8(RW) 00000000 rdlvl_gate_clk_adjust_7(RW) 00000000 rdlvl_gate_clk_adjust_6(RW) 00000000 rdlvl_gate_clk_adjust_5(RW) 00000000 rdlvl_gate_clk_adjust_4(RW)
MC1_CTL_7f0 : .dword 0xff08000000000000
//11111111 rdlvl_max_delay(RW) 00001000 rdlvl_gate_max_delay(RW) 00000000 rdlvl_gate_delay_8(RD) 00000000 rdlvl_gate_delay_7(RD) 00000000 rdlvl_gate_delay_6(RD) 00000000 rdlvl_gate_delay_5(RD) 00000000 rdlvl_gate_delay_4(RD) 00000000 rdlvl_gate_delay_3(RD)
MC1_CTL_800 : .dword 0x0000000000000000
//00000000 rdlvl_midpoint_delay_7(RD) 00000000 rdlvl_midpoint_delay_6(RD) 00000000 rdlvl_midpoint_delay_5(RD) 00000000 rdlvl_midpoint_delay_4(RD) 00000000 rdlvl_midpoint_delay_3(RD) 00000000 rdlvl_midpoint_delay_2(RD) 00000000 rdlvl_midpoint_delay_1(RD) 00000000 rdlvl_midpoint_delay_0(RD)
MC1_CTL_810 : .dword 0x0000000000000000
//00000000 rdlvl_offset_delay_6(RW) 00000000 rdlvl_offset_delay_5(RW) 00000000 rdlvl_offset_delay_4(RW) 00000000 rdlvl_offset_delay_3(RW) 00000000 rdlvl_offset_delay_2(RW) 00000000 rdlvl_offset_delay_1(RW) 00000000 rdlvl_offset_delay_0(RW) 00000000 rdlvl_midpoint_delay_8(RD)
MC1_CTL_820 : .dword 0x0420000c20400000
//00000100 tdfi_wrlvl_resplat(RW) 00000000 tdfi_wrlvl_resp(RD) 00000000 tdfi_rdlvl_rr(RW) 00001100 tdfi_rdlvl_resplat(RW) 00000000 tdfi_rdlvl_resp(RD) 01000000 refresh_per_zq(RW) 00000000 rdlvl_offset_delay_8(RW) 00000000 rdlvl_offset_delay_7(RW)
//MC1_CTL_830 : .dword 0x1313131313130c0a # 3A1
//MC1_CTL_830 : .dword 0x0000000000000c0a # 3A2
//MC1_CTL_830 : .dword 0x1515151515150c0a # 3A2
MC1_CTL_830 : .dword 0x2a2a2a2d2d2d0c0a
//00000000 wrlvl_delay_5(RD) 00000000 wrlvl_delay_4(RD) 00000000 wrlvl_delay_3(RD) 00000000 wrlvl_delay_2(RD) 00000000 wrlvl_delay_1(RD) 00000000 wrlvl_delay_0(RD) 00000010 tmod(RW) 00001010 tdfi_wrlvl_ww(RW)
//MC1_CTL_840 : .dword 0x0000640064001313 # 3A1
//MC1_CTL_840 : .dword 0x0000640064000000 # 3A2
//MC1_CTL_840 : .dword 0x0000640064151515 # 3A2
MC1_CTL_840 : .dword 0x0000640064002a2a # 3A2
//00000000000000_0001100100 axi1_priority_relax(RW) 000000_0001100100 axi0_priority_relax(RW) 00000000 wrlvl_delay_8(RD) 00000000 wrlvl_delay_7(RD) 00000000 wrlvl_delay_6(RD)
MC1_CTL_850 : .dword 0x0000000000000064
//000000_0000000000 out_of_range_source_id(RD) 000000_0000000000 ecc_u_id(RD) 000000_0000000000 ecc_c_id(RD) 000000_0001100100 axi2_priority_relax(RW)
MC1_CTL_860 : .dword 0x0200004000000000
MC1_CTL_870 : .dword 0x0046004600460046
//0_000000000000010 emrs1_data_3(RW) 0_000000000000010 emrs1_data_2(RW) 0_000000000000010 emrs1_data_1(RW) 0_000000000000010 emrs1_data_0(RW)
MC1_CTL_880 : .dword 0x0000000000000000
//0_000000000000000 emrs3_data_3(RW) 0_000000000000000 emrs3_data_2(RW) 0_000000000000000 emrs3_data_1(RW) 0_000000000000000 emrs3_data_0(RW)
MC1_CTL_890 : .dword 0x0a520a520a520a52
//MC1_CTL_890 : .dword 0x0a5a0a5a0a5a0a52
//0_000010000010000 mrs_data_3(RW) 0_000010000010000 mrs_data_2(RW) 0_000010000010000 mrs_data_1(RW) 0_000010000010000 mrs_data_0(RW)
MC1_CTL_8a0 : .dword 0x00000000001c001c
//0000000000000000 lowpower_internal_cnt(RW) 0000000000000000 lowpower_external_cnt(RW) 0000000000011100 axi2_en_size_lt_width_instr(RW) 0000000000011100 axi1_en_size_lt_width_instr(RW)
MC1_CTL_8b0 : .dword 0x0000000000000000
//0000000000000000 refresh_per_rdlvl(RW) 0000000000000000 lowpower_self_refresh_cnt(RW) 0000000000000000 lowpower_refresh_hold(RW) 0000000000000000 lowpower_power_down_cnt(RW)
MC1_CTL_8c0 : .dword 0x0004000000000000
//0000000000000100 wrlvl_interval(RW) 0000000000000000 tdfi_wrlvl_max(RW) 0000000000000000 tdfi_rdlvl_max(RW) 0000000000000000 refresh_per_rdlvl_gate(RW)
MC1_CTL_8d0 : .dword 0x00000000c8000000
//0000000000000000000000000000000011001000 cke_inactive(RW) 000000_000000000000000000 wrlvl_status(RD)
MC1_CTL_8e0 : .dword 0x0000000000000050
//MC1_CTL_8f0 : .dword 0x000000000a150080 //clk skew cleared
//MC1_CTL_8f0 : .dword 0x000000000a100080 //clk skew cleared
//MC1_CTL_8f0 : .dword 0x000000002b352180 // 3A1
//MC1_CTL_8f0 : .dword 0x000000001b251180
//MC1_CTL_8f0 : .dword 0x0000000040404080
//MC1_CTL_8f0 : .dword 0x0000000003000a80 //clk skew of 3A2 0.4
//MC1_CTL_8f0 : .dword 0x0000000013101a80 //clk skew of 3A2 0.4
//MC1_CTL_8f0 : .dword 0x0000000012101a80 //clk skew of 3A2 0.4
//MC1_CTL_8f0 : .dword 0x000000000a0e1080 //clk skew of 3A2 0.4
//MC1_CTL_8f0 : .dword 0x0000000085858580 //clk skew of 3A2 0.4
MC1_CTL_8f0 : .dword 0x000000002a2a2a80 //clk skew of 3A2 0.4
//MC1_CTL_8f0 : .dword 0x0000000016151580 //clk skew of 3A2 0.4
//MC1_CTL_8f0 : .dword 0x000000000c0d0d80 //clk skew of 3A2 0.4
//0000000000000000000000000111100_000000000000000000000000001111000 dll_ctrl_reg_2(RW)
MC1_CTL_900 : .dword 0x0000000000000000
MC1_CTL_910 : .dword 0x0000000000000000
MC1_CTL_920 : .dword 0x0000000000000000
MC1_CTL_930 : .dword 0x0000000000000000
MC1_CTL_940 : .dword 0x0306060000050500
//0000_0011 tdfi_rdlvl_en(RW) 00000_000 w2r_samecs_dly(RW) 00000_000 w2r_diffcs_dly(RW) 00000_000 lvl_status(RD) 0000000_0 rdlvl_edge(RW) 0000_0101 cksrx(RW) 0000_0101 cksre(RW) 00000000
MC1_CTL_950 : .dword 0x0000000000000a03
//0000000000000000000000_000000000000000000 int_mask(RW) 0000000000001010 txpdll(RW) 0000_0011 tdfi_wrlvl_en(RW)
MC1_CTL_960 : .dword 0x0604000100000000
//000_00101 rdlat_adj(RW) 0000_0100 wrlat_adj(RW) 0000000_0 swlvl_start(WR) 0000000_0 swlvl_load(WR) 0000000_0 swlvl_exit(WR) 000000_000000000000000000 int_status(RD)
MC1_CTL_970 : .dword 0x000000000003e805
//00000000000000000000000_00000000000000000 int_ack(WR) 0000001111101000 dll_rst_delay(RW) 00000101 dll_rst_adj_dly(RW)
MC1_CTL_start_DATA_LO: .word 0x00000000
//0000000_1 rw_same_en 0000000_0 reg_dimm_enable 0000000_0 reduc 0000000_0 pwrup_srefresh_exit
MC1_CTL_start_DATA_HI: .word 0x01010100
//0000000_1 swap_port_rw_same_en 0000000_1 swap_en 0000000_0 start 0000000_0 srefresh
#endif
#include "ddr2_config.S"

16
sys/arch/mips/include/newtest/mydebug.S
View File

@ -1375,7 +1375,11 @@ END(Hexserial)
#ifndef BONITOEL_CPCI
LEAF(tgt_testchar)
#ifdef HAVE_NB_SERIAL
#ifdef USE_LPC_UART
la v0, COM3_BASE_ADDR
#else
la v0, GS3_UART_BASE
#endif
#else
la v0, COM1_BASE_ADDR
#endif
@ -1388,7 +1392,11 @@ END(tgt_testchar)
LEAF(tgt_getchar)
#ifdef HAVE_NB_SERIAL
#ifdef USE_LPC_UART
la v0, COM3_BASE_ADDR
#else
la v0, GS3_UART_BASE
#endif
#else
la v0, COM1_BASE_ADDR
#endif
@ -1404,7 +1412,11 @@ END(tgt_getchar)
#else
LEAF(tgt_testchar)
#ifdef HAVE_NB_SERIAL
#ifdef USE_LPC_UART
la v0, COM3_BASE_ADDR
#else
la v0, GS3_UART_BASE
#endif
#else
la v0, COM1_BASE_ADDR
and v1,k1,1
@ -1427,7 +1439,11 @@ END(tgt_testchar)
LEAF(tgt_getchar)
#ifdef HAVE_NB_SERIAL
#ifdef USE_LPC_UART
la v0, COM3_BASE_ADDR
#else
la v0, GS3_UART_BASE
#endif
#else
la v0, COM1_BASE_ADDR
and v1,k1,1

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