Add config of CORE_FREQ

Change-Id: I386081d12a10b105a9b9d17edd428d9b38bbbe40
6 years ago · 22dd2d1001
9 changed files with 107 additions and 150 deletions
--- a/Targets/Bonito3a82h/Bonito/start.S
+++ b/Targets/Bonito3a82h/Bonito/start.S
@ -354,24 +354,29 @@ gs_2f_v3_ddr2_cfg:
 	nop
 3:
 	TTYDBG (" 3\r\n")
-2:      
+2:

 #define SOFT_CLKSEL
 #ifdef SOFT_CLKSEL

+#ifndef DDR_FREQ
 #define DDR_FREQ    528
+#endif
+
 #define DDR_REFC    1   //do not modify
 #if (DDR_FREQ < 400)
 #define DDR_DIV     8
 #else
 #define DDR_DIV     4
 #endif
-#define DDR_LOOPC  (DDR_FREQ*DDR_DIV/33)
+#define DDR_LOOPC  (DDR_FREQ*DDR_DIV*DDR_REFC/33)
+
+#ifndef CORE_FREQ    
+#define CORE_FREQ    800
+#endif

-//#define L1_LOOPC    68//850
-#define L1_LOOPC    64//800
-//#define L1_LOOPC    48//600
 #define L1_DIV      2
+#define L1_LOOPC    (CORE_FREQ*L1_DIV/25)
 #define FREQ 	800

 #define PLL_CHANG_COMMIT 0x1
--- a/Targets/Bonito3a82w/Bonito/start.S
+++ b/Targets/Bonito3a82w/Bonito/start.S
@ -388,7 +388,10 @@ gs_2f_v3_ddr2_cfg:
 #define SOFT_CLKSEL
 #ifdef SOFT_CLKSEL

+#ifndef DDR_FREQ
 #define DDR_FREQ    528
+#endif
+
 #define DDR_REFC    1   //do not modify
 #if (DDR_FREQ < 400)
 #define DDR_DIV     8
@ -398,11 +401,12 @@ gs_2f_v3_ddr2_cfg:
 #define DDR_LOOPC  (DDR_FREQ*DDR_DIV/33)

 // L1_* define both CPU and Node freq simutanleously
-#define L1_LOOPC    80//1000@25MHz
-//#define L1_LOOPC    64//800@25MHz
-//#define L1_LOOPC    49//808@33MHz
-//#define L1_LOOPC    48//600
+#ifndef CORE_FREQ
+#define CORE_FREQ    1000
+#endif
+
 #define L1_DIV      2
+#define L1_LOOPC    (CORE_FREQ*L1_DIV/25)

 #define BYPASS_CORE 0x0
 #define BYPASS_NODE 0x0
--- a/Targets/Bonito3a84w/Bonito/loongson3_clksetting.S
+++ b/Targets/Bonito3a84w/Bonito/loongson3_clksetting.S
@ -10,7 +10,10 @@ ATTENTION:

 #ifdef SOFT_CLKSEL

+#ifndef
 #define DDR_FREQ    528
+#endif
+
 #define DDR_REFC    1   //do not modify
 #if (DDR_FREQ < 400)
 #define DDR_DIV     8
@ -20,12 +23,12 @@ ATTENTION:
 #define DDR_LOOPC  (DDR_FREQ*DDR_DIV/33)   //48 //396MHz

 // L1_* define both CPU and Node freq simutanleously
-//#define L1_LOOPC    80//1000@25MHz
-#define L1_LOOPC    64//800@25MHz
-//#define L1_LOOPC    49//808@33MHz
-//#define L1_LOOPC    48//600
-//#define L1_LOOPC    40//500
+#ifndef
+#define CORE_FREQ    800
+#endif
+
 #define L1_DIV      2
+#define L1_LOOPC    (CORE_FREQ*L1_DIV/25)

 #define BYPASS_CORE 0x0
 #define BYPASS_NODE 0x0
--- a/Targets/Bonito3a8780e/Bonito/start.S
+++ b/Targets/Bonito3a8780e/Bonito/start.S
@ -367,20 +367,21 @@ gs_2f_v3_ddr2_cfg:
 #define SOFT_CLKSEL
 #ifdef SOFT_CLKSEL

+#ifndef DDR_FREQ
 #define DDR_FREQ    396
-//#define DDR_FREQ    495
-//#define DDR_FREQ    594
+#endif
+
 #define DDR_REFC    1   //do not modify
 #define DDR_DIV     4
 #define DDR_LOOPC  (DDR_FREQ*DDR_DIV/33)   //48 //396MHz

 // L1_* define both CPU and Node freq simutanleously
-//#define L1_LOOPC    80//1000
-//#define L1_LOOPC    72//900
-#define L1_LOOPC    64//800
-//#define L1_LOOPC    48//600
-//#define L1_LOOPC    40//500
+#ifndef CORE_FREQ
+#define CORE_FREQ    800
+#endif
+
 #define L1_DIV      2
+#define L1_LOOPC    (CORE_FREQ*L1_DIV/25)

 #define BYPASS_CORE 0x0
 #define BYPASS_NODE 0x0
--- a/Targets/Bonito3a92h/Bonito/start.S
+++ b/Targets/Bonito3a92h/Bonito/start.S
@ -407,59 +407,44 @@ gs_2f_v3_ddr2_cfg:
 #define PLL_L1_LOCKED ((ST_PLL << 17) | (LS_PLL << 16))

 #define DDR_SEL_ST 1
+
+#ifndef CORE_FREQ
+#define CORE_FREQ 1400
+#endif
+
 //#define REF_33M
 //#define REF_100M
 #ifdef REF_100M

-//#define L1_LOOPC    80//1000
-//#define L1_LOOPC    72//900
-//#define L1_LOOPC   256//800
-//#define L1_LOOPC   32//400
-//#define L1_LOOPC    48//600
-#define L1_LOOPC    48//600
-//#define L1_LOOPC    40//500
 #define L1_DIV      2
 //#define L1_DIV      2
 #define L1_REFC   1
+#define CPU_PLLIN 100

 #elsif REF_33M

-//#define L1_LOOPC    80//1000
-//#define L1_LOOPC    72//900
-//#define L1_LOOPC   256//800
-//#define L1_LOOPC   32//400
-#define L1_LOOPC   144//600
-//#define L1_LOOPC    40//500
 #define L1_DIV      8
 //#define L1_DIV      2
 #define L1_REFC   1
+#define CPU_PLLIN 33

 #else //REF_25M

-//#define L1_LOOPC   128//1600
-//#define L1_LOOPC   124//1550
-//#define L1_LOOPC   122//1525
-//#define L1_LOOPC   120//1500
-//#define L1_LOOPC   116//1450
-#define L1_LOOPC   112//1400
-//#define L1_LOOPC   108//1350
-//#define L1_LOOPC   104//1300
-//#define L1_LOOPC   100//1250
-//#define L1_LOOPC   192//1200
-//#define L1_LOOPC   184//1150
-//#define L1_LOOPC   160//1000
-//#define L1_LOOPC  144//900
-//#define L1_LOOPC  128//800
 //#define L1_DIV      4
 #define L1_DIV      2
 #define L1_REFC   1
+#define CPU_PLLIN 25
 #endif

+#define L1_LOOPC    (CORE_FREQ*L1_REFC*L1_DIV/CPU_PLLIN)
+
 #ifdef DDR_SEL_ST
-#define DDR_FREQ (L1_LOOPC*25/L1_DIV/L1_REFC/DDR_REFC)
+#define DDR_FREQ (L1_LOOPC*CPU_PLLIN/L1_DIV/L1_REFC/DDR_REFC)
 #else
+#ifndef DDR_FREQ
 #define DDR_FREQ  (DDR_LOOPC*33/DDR_DIV/DDR_REFC)
 #endif
+#endif

 #define BYPASS_CORE 0x0
 #define BYPASS_NODE 0x0
--- a/Targets/Bonito3a92w/Bonito/loongson3_clksetting.S
+++ b/Targets/Bonito3a92w/Bonito/loongson3_clksetting.S
@ -30,61 +30,47 @@ ATTENTION:
 #define PLL_L1_LOCKED ((ST_PLL << 17) | (LS_PLL << 16))

 #define DDR_SEL_ST 1
+
+#ifndef CORE_FREQ
+#define CORE_FREQ 1400
+#endif
+
 //#define REF_33M
 //#define REF_100M
+
 #ifdef REF_100M

-//#define L1_LOOPC    80//1000
-//#define L1_LOOPC    72//900
-//#define L1_LOOPC   256//800
-//#define L1_LOOPC   32//400
-//#define L1_LOOPC    48//600
-#define L1_LOOPC    48//600
-//#define L1_LOOPC    40//500
 #define L1_DIV      2
-//#define L1_DIV      2
 #define L1_REFC   1
+#define CPU_PLLIN 100
+
+#elsif REF_33M

-#else
-#ifdef REF_33M
-
-//#define L1_LOOPC    80//1000
-//#define L1_LOOPC    72//900
-//#define L1_LOOPC   256//800
-//#define L1_LOOPC   32//400
-#define L1_LOOPC   144//600
-//#define L1_LOOPC    40//500
 #define L1_DIV      8
 //#define L1_DIV      2
 #define L1_REFC   1
+#define CPU_PLLIN 33

 #else //REF_25M

-//#define L1_LOOPC   128//1600
-//#define L1_LOOPC   124//1550
-//#define L1_LOOPC   122//1525
-//#define L1_LOOPC   120//1500
-//#define L1_LOOPC   116//1450
-#define L1_LOOPC   112//1400
-//#define L1_LOOPC   108//1350
-//#define L1_LOOPC   104//1300
-//#define L1_LOOPC   100//1250
-//#define L1_LOOPC   192//1200
-//#define L1_LOOPC   184//1150
-//#define L1_LOOPC   160//1000
-//#define L1_LOOPC   128//800
-//#define L1_LOOPC   192//600
 //#define L1_DIV      4
 #define L1_DIV      2
 #define L1_REFC   1
+#define CPU_PLLIN 25
 #endif
-#endif
+
+#define L1_LOOPC    (CORE_FREQ*L1_REFC*L1_DIV/CPU_PLLIN)

 #ifdef DDR_SEL_ST
-#define DDR_FREQ (L1_LOOPC*25/L1_DIV/L1_REFC/DDR_REFC)
+#define DDR_FREQ (L1_LOOPC*CPU_PLLIN/L1_DIV/L1_REFC/DDR_REFC)
 #else
+#ifndef DDR_FREQ
 #define DDR_FREQ  (DDR_LOOPC*33/DDR_DIV/DDR_REFC)
 #endif
+#endif
+
+
+
 #define BYPASS_CORE 0x0
 #define BYPASS_NODE 0x0
 #define BYPASS_L1   0x0
--- a/Targets/Bonito3a94w/Bonito/loongson3_clksetting.S
+++ b/Targets/Bonito3a94w/Bonito/loongson3_clksetting.S
@ -30,60 +30,45 @@ ATTENTION:
 #define PLL_L1_LOCKED ((ST_PLL << 17) | (LS_PLL << 16))

 #define DDR_SEL_ST 1
+
+#ifndef CORE_FREQ
+#define CORE_FREQ 1000
+#endif
+
 //#define REF_33M
 //#define REF_100M
 #ifdef REF_100M

-//#define L1_LOOPC    80//1000
-//#define L1_LOOPC    72//900
-//#define L1_LOOPC   256//800
-//#define L1_LOOPC   32//400
-//#define L1_LOOPC    48//600
-#define L1_LOOPC    48//600
-//#define L1_LOOPC    40//500
 #define L1_DIV      2
 //#define L1_DIV      2
 #define L1_REFC   1
+#define CPU_PLLIN 100
+
+#elsif REF_33M

-#else
-#ifdef REF_33M
-
-//#define L1_LOOPC    80//1000
-//#define L1_LOOPC    72//900
-//#define L1_LOOPC   256//800
-//#define L1_LOOPC   32//400
-#define L1_LOOPC   144//600
-//#define L1_LOOPC    40//500
 #define L1_DIV      8
 //#define L1_DIV      2
 #define L1_REFC   1
+#define CPU_PLLIN 33

 #else //REF_25M

-//#define L1_LOOPC   128//1600
-//#define L1_LOOPC   124//1550
-//#define L1_LOOPC   122//1525
-//#define L1_LOOPC   120//1500
-//#define L1_LOOPC   116//1450
-//#define L1_LOOPC   112//1400
-//#define L1_LOOPC   108//1350
-//#define L1_LOOPC   104//1300
-//#define L1_LOOPC   100//1250
-//#define L1_LOOPC   192//1200
-//#define L1_LOOPC   184//1150
-#define L1_LOOPC   160//1000
-//#define L1_LOOPC   128//800
 #define L1_DIV      4
 //#define L1_DIV      2
 #define L1_REFC   1
+#define CPU_PLLIN 25
 #endif
-#endif
+
+#define L1_LOOPC    (CORE_FREQ*L1_REFC*L1_DIV/CPU_PLLIN)

 #ifdef DDR_SEL_ST
-#define DDR_FREQ (L1_LOOPC*25/L1_DIV/L1_REFC/DDR_REFC)
+#define DDR_FREQ (L1_LOOPC*CPU_PLLIN/L1_DIV/L1_REFC/DDR_REFC)
 #else
+#ifndef DDR_FREQ
 #define DDR_FREQ  (DDR_LOOPC*33/DDR_DIV/DDR_REFC)
 #endif
+#endif
+

 #define BYPASS_CORE 0x0
 #define BYPASS_NODE 0x0
--- a/Targets/Bonito3a9780e/Bonito/start.S
+++ b/Targets/Bonito3a9780e/Bonito/start.S
@ -410,58 +410,43 @@ gs_2f_v3_ddr2_cfg:

 #define DDR_SEL_ST 1

+#ifndef CORE_FREQ
+#define CORE_FREQ 1200
+#endif
+
 //#define REF_33M
 //#define REF_100M
+
 #ifdef REF_100M

-//#define L1_LOOPC    80//1000
-//#define L1_LOOPC    72//900
-//#define L1_LOOPC   256//800
-//#define L1_LOOPC   32//400
-//#define L1_LOOPC    48//600
-#define L1_LOOPC    48//600
-//#define L1_LOOPC    40//500
 #define L1_DIV      2
-//#define L1_DIV      2
 #define L1_REFC   1
+#define CPU_PLLIN 100

 #elsif REF_33M

-//#define L1_LOOPC    80//1000
-//#define L1_LOOPC    72//900
-//#define L1_LOOPC   256//800
-//#define L1_LOOPC   32//400
-#define L1_LOOPC   144//600
-//#define L1_LOOPC    40//500
 #define L1_DIV      8
 //#define L1_DIV      2
 #define L1_REFC   1
+#define CPU_PLLIN 33

 #else //REF_25M

-//#define L1_LOOPC   128//1600
-//#define L1_LOOPC   124//1550
-//#define L1_LOOPC   122//1525
-//#define L1_LOOPC   120//1500
-//#define L1_LOOPC   116//1450
-//#define L1_LOOPC   112//1400
-//#define L1_LOOPC   108//1350
-//#define L1_LOOPC   104//1300
-//#define L1_LOOPC   100//1250
-#define L1_LOOPC   192//1200
-//#define L1_LOOPC   184//1150
-//#define L1_LOOPC   160//1000
 #define L1_DIV      4
 //#define L1_DIV      2
 #define L1_REFC   1
+#define CPU_PLLIN 25
 #endif
-#define 	FREQ 1200
+
+#define L1_LOOPC    (CORE_FREQ*L1_REFC*L1_DIV/CPU_PLLIN)

 #ifdef DDR_SEL_ST
-#define DDR_FREQ (L1_LOOPC*25/L1_DIV/L1_REFC/DDR_REFC)
+#define DDR_FREQ (L1_LOOPC*CPU_PLLIN/L1_DIV/L1_REFC/DDR_REFC)
 #else
+#ifndef DDR_FREQ
 #define DDR_FREQ  (DDR_LOOPC*33/DDR_DIV/DDR_REFC)
 #endif
+#endif

 #define BYPASS_CORE 0x0
 #define BYPASS_NODE 0x0
--- a/Targets/LS2K/ls2k/loongson3_clksetting.S
+++ b/Targets/LS2K/ls2k/loongson3_clksetting.S
@ -15,7 +15,7 @@ ATTENTION:

 #ifndef DDR_FREQ
 /* MEM @ 500Mhz */
-#define DDR_FREQ   500   //this param must change with DDR freq together,ether soft or hard freq modified!!!
+//#define DDR_FREQ   500   //this param must change with DDR freq together,ether soft or hard freq modified!!!
 /* MEM @ 400Mhz */
 #define DDR_FREQ   400
 #endif
@ -23,8 +23,18 @@ ATTENTION:

 #define DDR_REFC   4
 #define DDR_DIV    1
-#define DDR_LOOPC  (DDR_FREQ*DDR_DIV*DDR_REFC/25)
 #define DDR_DIV_L2    4
+#define DDR_LOOPC  (DDR_FREQ*DDR_REFC*DDR_DIV*DDR_DIV_L2/100)
+
+#ifndef CORE_FREQ
+/* CPU @ 800Mhz */
+#define CORE_FREQ   800
+#endif
+
+#define L1_REFC     4
+#define L1_DIV      1
+#define L2_DIV      2
+#define CORE_LOOPC  (CORE_FREQ*L1_DIV*L2_DIV*L1_REFC/100)

 #if 1
 /* GPU @ 400Mhz */
@ -42,13 +52,6 @@ ATTENTION:
 #define L1_DIV      1
 #define L2_DIV      2
 #endif
-#if 1
-/* CPU @ 800Mhz */
-#define L1_LOOPC    64
-#define L1_REFC     4
-#define L1_DIV      1
-#define L2_DIV      2
-#endif
 /* DC @ 200Mhz */
 /* GMAC @ 125Mhz */
 #define DC_LOOPC    80