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3A2H: Add the pciscan command support. 

Change-Id: Ia686873e98d2bbf5430ac8229fc83bc19d1e751f
master
zhangbaoqi 10 years ago
parent
f4433ecf7e
commit
24a40dd03b
10 changed files with 1097 additions and 75 deletions
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  1. 5
      Targets/Bonito3a2h/Bonito/tgt_machdep.c
  2. 3
      Targets/Bonito3a2h/conf/Bonito.3a2h
  3. 2
      Targets/Bonito3a2h/conf/files.Bonito3a2h
  4. 291
      Targets/Bonito3a2h/pci/ls2h.h
  5. 163
      Targets/Bonito3a2h/pci/ls2h_int.h
  6. 472
      Targets/Bonito3a2h/pci/ls2h_pci.c
  7. 73
      Targets/Bonito3a2h/pci/pci_machdep.c
  8. 21
      pmon/cmds/pcicmds.c
  9. 20
      sys/dev/pci/pciconf.c
  10. 8
      sys/dev/pci/pcivar.h

5
Targets/Bonito3a2h/Bonito/tgt_machdep.c
View File

@ -493,6 +493,8 @@ asm(\
/*
* Probe clock frequencys so delays will work properly.
*/
delay(0x200000);
ls2h_pcibios_init();
tgt_cpufreq();
SBD_DISPLAY("DONE",0);
/*
@ -677,7 +679,7 @@ tgt_devconfig()
superio_base = 0xbff00000;
}
// _pci_devinit(1); /* PCI device initialization */
_pci_devinit(1); /* PCI device initialization */
#if (NMOD_X86EMU_INT10 > 0)||(NMOD_X86EMU >0)
SBD_DISPLAY("VGAI", 0);
rc = vga_bios_init();
@ -1227,6 +1229,7 @@ tgt_devinit()
}
#endif
_pci_businit(1); /* PCI bus initialization */
#if defined(VIA686B_POWERFIXUP) && (PCI_IDSEL_VIA686B != 0)
if(getenv("noautopower")) vt82c686_powerfixup();

3
Targets/Bonito3a2h/conf/Bonito.3a2h
View File

@ -171,6 +171,9 @@ loopdev0 at mainbus0
#fd0 at mainbus0
pcibr0 at mainbus0
#pcibr1 at mainbus0
pcibr2 at mainbus0 #For the port1 device register
pcibr4 at mainbus0 #For the port2 device register
pcibr6 at mainbus0 #For the port3 device register
pci* at pcibr?
#ppb* at pci? dev ? function ? # PCI-PCI bridges
#pci* at ppb? bus ?

2
Targets/Bonito3a2h/conf/files.Bonito3a2h
View File

@ -7,7 +7,7 @@ file Targets/Bonito3a2h/pci/pci_machdep.c
file Targets/Bonito3a2h/Bonito/tgt_machdep.c
file Targets/Bonito3a2h/pci/cs5536_io.c cs5536
file Targets/Bonito3a2h/pci/cs5536_vsm.c cs5536
file Targets/Bonito3a2h/pci/rs780_cmn.c loongson2h
file Targets/Bonito3a2h/pci/ls2h_pci.c loongson2h
#file Targets/Bonito3a2h/pci/amd_2h.c amd_2h
#file Targets/Bonito3a2h/pci/sb700.c amd_2h
#file Targets/Bonito3a2h/pci/sb700_ide.c amd_2h

291
Targets/Bonito3a2h/pci/ls2h.h
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@ -0,0 +1,291 @@
#ifndef _LS2H_H
#define _LS2H_H
#define LS2H_IO_REG_BASE 0x1b000000
/* CHIP CONFIG regs */
#define LS2H_CHIP_CFG_REG_BASE (LS2H_IO_REG_BASE + 0x00d00000)
#define LS2H_INT_REG_BASE (LS2H_CHIP_CFG_REG_BASE + 0x0040)
#define LS2H_INT_ISR0_REG (LS2H_CHIP_CFG_REG_BASE + 0x0040)
#define LS2H_INT_IEN0_REG (LS2H_CHIP_CFG_REG_BASE + 0x0044)
#define LS2H_INT_SET0_REG (LS2H_CHIP_CFG_REG_BASE + 0x0048)
#define LS2H_INT_CLR0_REG (LS2H_CHIP_CFG_REG_BASE + 0x004c)
#define LS2H_INT_POL0_REG (LS2H_CHIP_CFG_REG_BASE + 0x0050)
#define LS2H_INT_EDGE0_REG (LS2H_CHIP_CFG_REG_BASE + 0x0054)
#define LS2H_GPIO_CFG_REG (LS2H_CHIP_CFG_REG_BASE + 0x00c0)
#define LS2H_GPIO_OE_REG (LS2H_CHIP_CFG_REG_BASE + 0x00c4)
#define LS2H_GPIO_IN_REG (LS2H_CHIP_CFG_REG_BASE + 0x00c8)
#define LS2H_GPIO_OUT_REG (LS2H_CHIP_CFG_REG_BASE + 0x00cc)
#define LS2H_DMA_ORDER_REG (LS2H_CHIP_CFG_REG_BASE + 0x0100)
#define LS2H_CHIP_CFG0_REG (LS2H_CHIP_CFG_REG_BASE + 0x0200)
#define LS2H_CHIP_CFG1_REG (LS2H_CHIP_CFG_REG_BASE + 0x0204)
#define LS2H_CHIP_CFG2_REG (LS2H_CHIP_CFG_REG_BASE + 0x0208)
#define LS2H_CHIP_CFG3_REG (LS2H_CHIP_CFG_REG_BASE + 0x020c)
#define LS2H_CHIP_SAMP0_REG (LS2H_CHIP_CFG_REG_BASE + 0x0210)
#define LS2H_CHIP_SAMP1_REG (LS2H_CHIP_CFG_REG_BASE + 0x0214)
#define LS2H_CHIP_SAMP2_REG (LS2H_CHIP_CFG_REG_BASE + 0x0218)
#define LS2H_CHIP_SAMP3_REG (LS2H_CHIP_CFG_REG_BASE + 0x021c)
#define LS2H_CLK_CTRL0_REG (LS2H_CHIP_CFG_REG_BASE + 0x0220)
#define LS2H_CLK_CTRL1_REG (LS2H_CHIP_CFG_REG_BASE + 0x0224)
#define LS2H_CLK_CTRL2_REG (LS2H_CHIP_CFG_REG_BASE + 0x0228)
#define LS2H_CLK_CTRL3_REG (LS2H_CHIP_CFG_REG_BASE + 0x022c)
#define LS2H_PIXCLK0_CTRL0_REG (LS2H_CHIP_CFG_REG_BASE + 0x0230)
#define LS2H_PIXCLK0_CTRL1_REG (LS2H_CHIP_CFG_REG_BASE + 0x0234)
#define LS2H_PIXCLK1_CTRL0_REG (LS2H_CHIP_CFG_REG_BASE + 0x0238)
#define LS2H_PIXCLK1_CTRL1_REG (LS2H_CHIP_CFG_REG_BASE + 0x023c)
#define LS2H_WIN_CFG_BASE (LS2H_CHIP_CFG_REG_BASE + 0x80000)
#define LS2H_M4_WIN0_BASE_REG (LS2H_WIN_CFG_BASE + 0x0400)
#define LS2H_M4_WIN0_MASK_REG (LS2H_WIN_CFG_BASE + 0x0440)
#define LS2H_M4_WIN0_MMAP_REG (LS2H_WIN_CFG_BASE + 0x0480)
/* USB regs */
#define LS2H_EHCI_REG_BASE (LS2H_IO_REG_BASE + 0x00e00000)
#define LS2H_OHCI_REG_BASE (LS2H_IO_REG_BASE + 0x00e08000)
/* GMAC regs */
#define LS2H_GMAC0_REG_BASE (LS2H_IO_REG_BASE + 0x00e10000)
#define LS2H_GMAC1_REG_BASE (LS2H_IO_REG_BASE + 0x00e18000)
/* HDA regs */
#define LS2H_HDA_REG_BASE (LS2H_IO_REG_BASE + 0x00e20000)
/* SATAregs */
#define LS2H_SATA_REG_BASE (LS2H_IO_REG_BASE + 0x00e30000)
/* GPU regs */
#define LS2H_GPU_REG_BASE (LS2H_IO_REG_BASE + 0x00e40000)
/* DC regs */
#define LS2H_DC_REG_BASE (LS2H_IO_REG_BASE + 0x00e50000)
#define LS2H_FB_CFG_DVO_REG (LS2H_DC_REG_BASE + 0x1240)
#define LS2H_FB_CFG_VGA_REG (LS2H_DC_REG_BASE + 0x1250)
#define LS2H_FB_ADDR0_DVO_REG (LS2H_DC_REG_BASE + 0x1260)
#define LS2H_FB_ADDR0_VGA_REG (LS2H_DC_REG_BASE + 0x1270)
#define LS2H_FB_STRI_DVO_REG (LS2H_DC_REG_BASE + 0x1280)
#define LS2H_FB_STRI_VGA_REG (LS2H_DC_REG_BASE + 0x1290)
#define LS2H_FB_DITCFG_DVO_REG (LS2H_DC_REG_BASE + 0x1360)
#define LS2H_FB_DITCFG_VGA_REG (LS2H_DC_REG_BASE + 0x1370)
#define LS2H_FB_DITTAB_LO_DVO_REG (LS2H_DC_REG_BASE + 0x1380)
#define LS2H_FB_DITTAB_LO_VGA_REG (LS2H_DC_REG_BASE + 0x1390)
#define LS2H_FB_DITTAB_HI_DVO_REG (LS2H_DC_REG_BASE + 0x13a0)
#define LS2H_FB_DITTAB_HI_VGA_REG (LS2H_DC_REG_BASE + 0x13b0)
#define LS2H_FB_PANCFG_DVO_REG (LS2H_DC_REG_BASE + 0x13c0)
#define LS2H_FB_PANCFG_VGA_REG (LS2H_DC_REG_BASE + 0x13d0)
#define LS2H_FB_PANTIM_DVO_REG (LS2H_DC_REG_BASE + 0x13e0)
#define LS2H_FB_PANTIM_VGA_REG (LS2H_DC_REG_BASE + 0x13f0)
#define LS2H_FB_HDISPLAY_DVO_REG (LS2H_DC_REG_BASE + 0x1400)
#define LS2H_FB_HDISPLAY_VGA_REG (LS2H_DC_REG_BASE + 0x1410)
#define LS2H_FB_HSYNC_DVO_REG (LS2H_DC_REG_BASE + 0x1420)
#define LS2H_FB_HSYNC_VGA_REG (LS2H_DC_REG_BASE + 0x1430)
#define LS2H_FB_VDISPLAY_DVO_REG (LS2H_DC_REG_BASE + 0x1480)
#define LS2H_FB_VDISPLAY_VGA_REG (LS2H_DC_REG_BASE + 0x1490)
#define LS2H_FB_VSYNC_DVO_REG (LS2H_DC_REG_BASE + 0x14a0)
#define LS2H_FB_VSYNC_VGA_REG (LS2H_DC_REG_BASE + 0x14b0)
#define LS2H_FB_GAMINDEX_DVO_REG (LS2H_DC_REG_BASE + 0x14e0)
#define LS2H_FB_GAMINDEX_VGA_REG (LS2H_DC_REG_BASE + 0x14f0)
#define LS2H_FB_GAMDATA_DVO_REG (LS2H_DC_REG_BASE + 0x1500)
#define LS2H_FB_GAMDATA_VGA_REG (LS2H_DC_REG_BASE + 0x1510)
#define LS2H_FB_CUR_CFG_REG (LS2H_DC_REG_BASE + 0x1520)
#define LS2H_FB_CUR_ADDR_REG (LS2H_DC_REG_BASE + 0x1530)
#define LS2H_FB_CUR_LOC_ADDR_REG (LS2H_DC_REG_BASE + 0x1540)
#define LS2H_FB_CUR_BACK_REG (LS2H_DC_REG_BASE + 0x1550)
#define LS2H_FB_CUR_FORE_REG (LS2H_DC_REG_BASE + 0x1560)
#define LS2H_FB_INT_REG (LS2H_DC_REG_BASE + 0x1570)
#define LS2H_FB_ADDR1_DVO_REG (LS2H_DC_REG_BASE + 0x1580)
#define LS2H_FB_ADDR1_VGA_REG (LS2H_DC_REG_BASE + 0x1590)
#define LS2H_FB_DAC_CTRL_REG (LS2H_DC_REG_BASE + 0x1600)
/* OTG regs */
#define LS2H_OTG_REG_BASE (LS2H_IO_REG_BASE + 0x00e60000)
/* SPI regs */
#define LS2H_SPI_REG_BASE (LS2H_IO_REG_BASE + 0x00e70000)
/* UART regs */
#define LS2H_UART0_REG_BASE (LS2H_IO_REG_BASE + 0x00e80000)
#define LS2H_UART1_REG_BASE (LS2H_IO_REG_BASE + 0x00e81000)
#define LS2H_UART2_REG_BASE (LS2H_IO_REG_BASE + 0x00e82000)
#define LS2H_UART3_REG_BASE (LS2H_IO_REG_BASE + 0x00e83000)
/* I2C regs */
#define LS2H_I2C0_REG_BASE (LS2H_IO_REG_BASE + 0x00e90000)
#define LS2H_I2C0_PRER_LO_REG (LS2H_I2C0_REG_BASE + 0x0)
#define LS2H_I2C0_PRER_HI_REG (LS2H_I2C0_REG_BASE + 0x1)
#define LS2H_I2C0_CTR_REG (LS2H_I2C0_REG_BASE + 0x2)
#define LS2H_I2C0_TXR_REG (LS2H_I2C0_REG_BASE + 0x3)
#define LS2H_I2C0_RXR_REG (LS2H_I2C0_REG_BASE + 0x3)
#define LS2H_I2C0_CR_REG (LS2H_I2C0_REG_BASE + 0x4)
#define LS2H_I2C0_SR_REG (LS2H_I2C0_REG_BASE + 0x4)
#define LS2H_I2C1_REG_BASE (LS2H_IO_REG_BASE + 0x00e91000)
#define LS2H_I2C1_PRER_LO_REG (LS2H_I2C1_REG_BASE + 0x0)
#define LS2H_I2C1_PRER_HI_REG (LS2H_I2C1_REG_BASE + 0x1)
#define LS2H_I2C1_CTR_REG (LS2H_I2C1_REG_BASE + 0x2)
#define LS2H_I2C1_TXR_REG (LS2H_I2C1_REG_BASE + 0x3)
#define LS2H_I2C1_RXR_REG (LS2H_I2C1_REG_BASE + 0x3)
#define LS2H_I2C1_CR_REG (LS2H_I2C1_REG_BASE + 0x4)
#define LS2H_I2C1_SR_REG (LS2H_I2C1_REG_BASE + 0x4)
#define CR_START 0x80
#define CR_STOP 0x40
#define CR_READ 0x20
#define CR_WRITE 0x10
#define CR_ACK 0x8
#define CR_IACK 0x1
#define SR_NOACK 0x80
#define SR_BUSY 0x40
#define SR_AL 0x20
#define SR_TIP 0x2
#define SR_IF 0x1
/* PWM regs */
#define LS2H_PWM_REG_BASE (LS2H_IO_REG_BASE + 0x00ea0000)
/* HPET regs */
#define LS2H_HPET_REG_BASE (LS2H_IO_REG_BASE + 0x00ec0000)
/* AC97 regs */
#define LS2H_AC97_REG_BASE (LS2H_IO_REG_BASE + 0x00ed0000)
/* NAND regs */
#define LS2H_NAND_REG_BASE (LS2H_IO_REG_BASE + 0x00ee0000)
#define LS2H_NAND_CMD_REG (LS2H_NAND_REG_BASE + 0x0000)
#define LS2H_NAND_ADDR_C_REG (LS2H_NAND_REG_BASE + 0x0004)
#define LS2H_NAND_ADDR_R_REG (LS2H_NAND_REG_BASE + 0x0008)
#define LS2H_NAND_TIMING_REG (LS2H_NAND_REG_BASE + 0x000c)
#define LS2H_NAND_IDL_REG (LS2H_NAND_REG_BASE + 0x0010)
#define LS2H_NAND_STA_IDH_REG (LS2H_NAND_REG_BASE + 0x0014)
#define LS2H_NAND_PARAM_REG (LS2H_NAND_REG_BASE + 0x0018)
#define LS2H_NAND_OP_NUM_REG (LS2H_NAND_REG_BASE + 0x001c)
#define LS2H_NAND_CSRDY_MAP_REG (LS2H_NAND_REG_BASE + 0x0020)
#define LS2H_NAND_DMA_ACC_REG (LS2H_NAND_REG_BASE + 0x0040)
/* ACPI regs */
#define LS2H_ACPI_REG_BASE (LS2H_IO_REG_BASE + 0x00ef0000)
#define LS2H_PM_SOC_REG (LS2H_ACPI_REG_BASE + 0x0000)
#define LS2H_PM_RESUME_REG (LS2H_ACPI_REG_BASE + 0x0004)
#define LS2H_PM_RTC_REG (LS2H_ACPI_REG_BASE + 0x0008)
#define LS2H_PM1_STS_REG (LS2H_ACPI_REG_BASE + 0x000c)
#define LS2H_PM1_EN_REG (LS2H_ACPI_REG_BASE + 0x0010)
#define LS2H_PM1_CNT_REG (LS2H_ACPI_REG_BASE + 0x0014)
#define LS2H_PM1_TMR_REG (LS2H_ACPI_REG_BASE + 0x0018)
#define LS2H_P_CNT_REG (LS2H_ACPI_REG_BASE + 0x001c)
#define LS2H_P_LVL2_REG (LS2H_ACPI_REG_BASE + 0x0020)
#define LS2H_P_LVL3_REG (LS2H_ACPI_REG_BASE + 0x0024)
#define LS2H_GPE0_STS_REG (LS2H_ACPI_REG_BASE + 0x0028)
#define LS2H_GPE0_EN_REG (LS2H_ACPI_REG_BASE + 0x002c)
#define LS2H_RST_CNT_REG (LS2H_ACPI_REG_BASE + 0x0030)
#define LS2H_WD_SET_REG (LS2H_ACPI_REG_BASE + 0x0034)
#define LS2H_WD_TIMER_REG (LS2H_ACPI_REG_BASE + 0x0038)
#define LS2H_DVFS_CNT_REG (LS2H_ACPI_REG_BASE + 0x003c)
#define LS2H_DVFS_STS_REG (LS2H_ACPI_REG_BASE + 0x0040)
#define LS2H_MS_CNT_REG (LS2H_ACPI_REG_BASE + 0x0044)
#define LS2H_MS_THT_REG (LS2H_ACPI_REG_BASE + 0x0048)
#define LS2H_THSENS_CNT_REG (LS2H_ACPI_REG_BASE + 0x004c)
#define LS2H_GEN_RTC1_REG (LS2H_ACPI_REG_BASE + 0x0050)
#define LS2H_GEN_RTC2_REG (LS2H_ACPI_REG_BASE + 0x0054)
/* RTC regs */
#define LS2H_RTC_REG_BASE (LS2H_IO_REG_BASE + 0x00ef8000)
#define LS2H_TOY_TRIM_REG (LS2H_RTC_REG_BASE + 0x0020)
#define LS2H_TOY_WRITE0_REG (LS2H_RTC_REG_BASE + 0x0024)
#define LS2H_TOY_WRITE1_REG (LS2H_RTC_REG_BASE + 0x0028)
#define LS2H_TOY_READ0_REG (LS2H_RTC_REG_BASE + 0x002c)
#define LS2H_TOY_READ1_REG (LS2H_RTC_REG_BASE + 0x0030)
#define LS2H_TOY_MATCH0_REG (LS2H_RTC_REG_BASE + 0x0034)
#define LS2H_TOY_MATCH1_REG (LS2H_RTC_REG_BASE + 0x0038)
#define LS2H_TOY_MATCH2_REG (LS2H_RTC_REG_BASE + 0x003c)
#define LS2H_RTC_CTRL_REG (LS2H_RTC_REG_BASE + 0x0040)
#define LS2H_RTC_TRIM_REG (LS2H_RTC_REG_BASE + 0x0060)
#define LS2H_RTC_WRITE0_REG (LS2H_RTC_REG_BASE + 0x0064)
#define LS2H_RTC_READ0_REG (LS2H_RTC_REG_BASE + 0x0068)
#define LS2H_RTC_MATCH0_REG (LS2H_RTC_REG_BASE + 0x006c)
#define LS2H_RTC_MATCH1_REG (LS2H_RTC_REG_BASE + 0x0070)
#define LS2H_RTC_MATCH2_REG (LS2H_RTC_REG_BASE + 0x0074)
/* LPC regs */
#define LS2H_LPC_IO_BASE (LS2H_IO_REG_BASE + 0x00f00000)
#define LS2H_LPC_REG_BASE (LS2H_IO_REG_BASE + 0x00f10000)
#define LS2H_LPC_CFG0_REG (LS2H_LPC_REG_BASE + 0x0)
#define LS2H_LPC_CFG1_REG (LS2H_LPC_REG_BASE + 0x4)
#define LS2H_LPC_CFG2_REG (LS2H_LPC_REG_BASE + 0x8)
#define LS2H_LPC_CFG3_REG (LS2H_LPC_REG_BASE + 0xc)
/* REG ACCESS*/
#define ls2h_readb(addr) (*(volatile unsigned char *)CKSEG1ADDR(addr))
#define ls2h_readw(addr) (*(volatile unsigned int *)CKSEG1ADDR(addr))
#define ls2h_readl(addr) (*(volatile unsigned int *)CKSEG1ADDR(addr))
#define ls2h_writeb(val, addr) *(volatile unsigned char *)CKSEG1ADDR(addr) = (val)
#define ls2h_writew(val, addr) *(volatile unsigned int *)CKSEG1ADDR(addr) = (val)
#define ls2h_writel(val, addr) *(volatile unsigned int *)CKSEG1ADDR(addr) = (val)
/* Board Version Number */
enum {
LS2H_BOARD_VER_2_2 = 0x4,
LS2H_BOARD_VER_OLD = 0xf,
};
#define LS2H_PCIE_MAX_PORTNUM 3
#define LS2H_PCIE_PORT0 0
#define LS2H_PCIE_PORT1 1
#define LS2H_PCIE_PORT2 2
#define LS2H_PCIE_PORT3 3
#define LS2H_PCIE_GET_PORTNUM(sysdata) \
((((struct pci_controller *)(sysdata))->mem_resource->start \
& ~LS2H_PCIE_MEM0_DOWN_MASK) >> 25)
#define LS2H_CHIP_CFG_REG_CLK_CTRL3 0x22c
#define LS2H_CLK_CTRL3_BIT_PEREF_EN(portnum) (1 << (24 + portnum))
#define LS2H_PCIE_MEM0_BASE_PORT(portnum) (0x10000000 + (portnum << 25))
#define LS2H_PCIE_IO_BASE_PORT(portnum) (0x18100000 + (portnum << 22))
#define LS2H_PCIE_REG_BASE_PORT(portnum) (0x18118000 + (portnum << 22))
#define LS2H_PCIE_PORT_REG_CTR0 0x0
#define LS2H_PCIE_REG_CTR0_BIT_LTSSM_EN (1 << 3)
#define LS2H_PCIE_REG_CTR0_BIT_REQ_L1 (1 << 12)
#define LS2H_PCIE_REG_CTR0_BIT_RDY_L23 (1 << 13)
#define LS2H_PCIE_PORT_REG_STAT1 0xC
#define LS2H_PCIE_REG_STAT1_MASK_LTSSM 0x0000003f
#define LS2H_PCIE_REG_STAT1_BIT_LINKUP (1 << 6)
#define LS2H_PCIE_PORT_REG_CFGADDR 0x24
#define LS2H_PCIE_PORT_REG_CTR_STAT 0x28
#define LS2H_PCIE_REG_CTR_STAT_BIT_ISX4 (1 << 26)
#define LS2H_PCIE_REG_CTR_STAT_BIT_ISRC (1 << 27)
#define LS2H_PCIE_PORT_HEAD_BASE_PORT(portnum) (0x18114000 + (portnum << 22))
#define LS2H_PCIE_DEV_HEAD_BASE_PORT(portnum) (0x18116000 + (portnum << 22))
#define LIE_IN_WINDOW(addr,base,mask) ((addr & mask) == base)
#define MAP_2_WINDOW(addr,mmap,mask) ((addr & (~(mask))) | (mmap & mask))
#define LS2H_PCIE_MEM0_DOWN_BASE 0x10000000
#define LS2H_PCIE_MEM0_DOWN_MASK 0xf8000000
#define LS2H_PCIE_MEM0_UP_BASE 0x10000000
#define LS2H_PCIE_MEM0_UP_MASK 0xfe000000
#define LS2H_PCIE_IO_DOWN_BASE 0x18100000
#define LS2H_PCIE_IO_DOWN_MASK 0xff3f0000
#define LS2H_PCIE_IO_UP_BASE 0x0
#define LS2H_PCIE_IO_UP_MASK 0xffff0000
#if 0
struct ls2h_usbh_data {
u8 ports; /* number of ports on root hub */
u8 vbus_pin[]; /* port power-control pin */
};
#endif
#endif /*_LS2H_H*/

163
Targets/Bonito3a2h/pci/ls2h_int.h
View File

@ -0,0 +1,163 @@
/*
*
* BRIEF MODULE DESCRIPTION
* LS232 EVA BOARD Interrupt Numbering
*
* Copyright 2000 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* ppopov@mvista.com or source@mvista.com
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef _LS2H_INT_H
#define _LS2H_INT_H
#define LS2H_IRQ_OFF 64
#define LS2H_IRQ_BASE LS2H_IRQ_OFF
/* group 0 */
#define LS2H_ACPI_IRQ (0 + LS2H_IRQ_OFF)
#define LS2H_HPET_IRQ (1 + LS2H_IRQ_OFF)
#define LS2H_UART0_IRQ (2 + LS2H_IRQ_OFF)
#define LS2H_UART1_IRQ (3 + LS2H_IRQ_OFF)
#define LS2H_UART2_IRQ (4 + LS2H_IRQ_OFF)
#define LS2H_UART3_IRQ (5 + LS2H_IRQ_OFF)
#define LS2H_SPI_IRQ (6 + LS2H_IRQ_OFF)
#define LS2H_I2C0_IRQ (7 + LS2H_IRQ_OFF)
#define LS2H_I2C1_IRQ (8 + LS2H_IRQ_OFF)
#define LS2H_AC97_IRQ (9 + LS2H_IRQ_OFF)
#define LS2H_DMA0_IRQ (10 + LS2H_IRQ_OFF)
#define LS2H_DMA1_IRQ (11 + LS2H_IRQ_OFF)
#define LS2H_DMA2_IRQ (12 + LS2H_IRQ_OFF)
#define LS2H_LPC_IRQ (13 + LS2H_IRQ_OFF)
#define LS2H_RTC_INT0_IRQ (14 + LS2H_IRQ_OFF)
#define LS2H_RTC_INT1_IRQ (15 + LS2H_IRQ_OFF)
#define LS2H_RTC_INT2_IRQ (16 + LS2H_IRQ_OFF)
#define LS2H_TOY_INT0_IRQ (17 + LS2H_IRQ_OFF)
#define LS2H_TOY_INT1_IRQ (18 + LS2H_IRQ_OFF)
#define LS2H_TOY_INT2_IRQ (19 + LS2H_IRQ_OFF)
#define LS2H_RTC_TICK_IRQ (20 + LS2H_IRQ_OFF)
#define LS2H_TOY_TICK_IRQ (21 + LS2H_IRQ_OFF)
#define LS2H_NAND_IRQ (22 + LS2H_IRQ_OFF)
#define LS2H_SYS_INTN_IRQ (23 + LS2H_IRQ_OFF)
/* group 1 */
#define LS2H_EHCI_IRQ (32 + LS2H_IRQ_OFF)
#define LS2H_OHCI_IRQ (33 + LS2H_IRQ_OFF)
#define LS2H_OTG_IRQ (34 + LS2H_IRQ_OFF)
#define LS2H_GMAC0_IRQ (35 + LS2H_IRQ_OFF)
#define LS2H_GMAC1_IRQ (36 + LS2H_IRQ_OFF)
#define LS2H_SATA_IRQ (37 + LS2H_IRQ_OFF)
#define LS2H_GPU_IRQ (38 + LS2H_IRQ_OFF)
#define LS2H_DC_IRQ (39 + LS2H_IRQ_OFF)
#define LS2H_PWM0_IRQ (40 + LS2H_IRQ_OFF)
#define LS2H_PWM1_IRQ (41 + LS2H_IRQ_OFF)
#define LS2H_PWM2_IRQ (42 + LS2H_IRQ_OFF)
#define LS2H_PWM3_IRQ (43 + LS2H_IRQ_OFF)
#define LS2H_HT0_IRQ (44 + LS2H_IRQ_OFF)
#define LS2H_HT1_IRQ (45 + LS2H_IRQ_OFF)
#define LS2H_HT2_IRQ (46 + LS2H_IRQ_OFF)
#define LS2H_HT3_IRQ (47 + LS2H_IRQ_OFF)
#define LS2H_HT4_IRQ (48 + LS2H_IRQ_OFF)
#define LS2H_HT5_IRQ (49 + LS2H_IRQ_OFF)
#define LS2H_HT6_IRQ (50 + LS2H_IRQ_OFF)
#define LS2H_HT7_IRQ (51 + LS2H_IRQ_OFF)
#define LS2H_PCIE_PORT0_INTA_IRQ (52 + LS2H_IRQ_OFF)
#define LS2H_PCIE_PORT1_INTA_IRQ (53 + LS2H_IRQ_OFF)
#define LS2H_PCIE_PORT2_INTA_IRQ (54 + LS2H_IRQ_OFF)
#define LS2H_PCIE_PORT3_INTA_IRQ (55 + LS2H_IRQ_OFF)
#define LS2H_SATA_PHY_IRQ (56 + LS2H_IRQ_OFF)
#define LS2H_HDA_IRQ (57 + LS2H_IRQ_OFF)
#define LS2H_PCIE_PORT0_INTA_BIT (1 << 20)
#define LS2H_PCIE_PORT1_INTA_BIT (1 << 21)
#define LS2H_PCIE_PORT2_INTA_BIT (1 << 22)
#define LS2H_PCIE_PORT3_INTA_BIT (1 << 23)
/* group 2 */
#define LS2H_GPIO0_IRQ (64 + LS2H_IRQ_OFF)
#define LS2H_GPIO1_IRQ (65 + LS2H_IRQ_OFF)
#define LS2H_GPIO2_IRQ (66 + LS2H_IRQ_OFF)
#define LS2H_GPIO3_IRQ (67 + LS2H_IRQ_OFF)
#define LS2H_GPIO4_IRQ (68 + LS2H_IRQ_OFF)
#define LS2H_GPIO5_IRQ (69 + LS2H_IRQ_OFF)
#define LS2H_GPIO6_IRQ (70 + LS2H_IRQ_OFF)
#define LS2H_GPIO7_IRQ (71 + LS2H_IRQ_OFF)
#define LS2H_GPIO8_IRQ (72 + LS2H_IRQ_OFF)
#define LS2H_GPIO9_IRQ (73 + LS2H_IRQ_OFF)
#define LS2H_GPIO10_IRQ (74 + LS2H_IRQ_OFF)
#define LS2H_GPIO11_IRQ (75 + LS2H_IRQ_OFF)
#define LS2H_GPIO12_IRQ (76 + LS2H_IRQ_OFF)
#define LS2H_GPIO13_IRQ (77 + LS2H_IRQ_OFF)
#define LS2H_GPIO14_IRQ (78 + LS2H_IRQ_OFF)
#define LS2H_GPIO15_IRQ (79 + LS2H_IRQ_OFF)
#define LS2H_GPIO_IRQ 64+LS2H_IRQ_OFF
#define LS2H_GPIO_FIRST_IRQ 64+LS2H_IRQ_OFF
#define LS2H_GPIO_IRQ_COUNT 96
#define LS2H_GPIO_LAST_IRQ (LS2H_GPIO_FIRST_IRQ + LS2H_GPIO_IRQ_COUNT-1)
#define LS2H_LAST_IRQ (160 + LS2H_IRQ_OFF)
#define LS2H_KBD_IRQ 1
#define LS2H_AUX_IRQ 12
struct ls2h_int_ctrl_regs
{
volatile unsigned int int_isr;
volatile unsigned int int_en;
volatile unsigned int int_set;
volatile unsigned int int_clr; /* offset 0x10*/
volatile unsigned int int_pol;
volatile unsigned int int_edge; /* offset 0 */
};
struct ls2h_cop_global_registers
{
volatile unsigned int control;
volatile unsigned int rd_inten;
volatile unsigned int wr_inten;
volatile unsigned int rd_intisr; /* offset 0x10*/
volatile unsigned int wr_intisr;
unsigned int unused[11];
};
struct ls2h_cop_channel_regs
{
volatile unsigned int rd_control;
volatile unsigned int rd_src;
volatile unsigned int rd_cnt;
volatile unsigned int rd_status; /* offset 0x10*/
volatile unsigned int wr_control;
volatile unsigned int wr_src;
volatile unsigned int wr_cnt;
volatile unsigned int wr_status; /* offset 0x10*/
};
struct ls2h_cop_regs
{
struct ls2h_cop_global_registers global;
struct ls2h_cop_channel_regs chan[8][2];
};
#endif

472
Targets/Bonito3a2h/pci/ls2h_pci.c
View File

@ -0,0 +1,472 @@
#include <linux/types.h>
#include <types.h>
#include "Targets/Bonito3a2h/include/bonito.h"
#include "ls2h.h"
#include "ls2h_int.h"
#include "sys/dev/pci/pcireg.h"
//#include "sys/dev/pci/pcivar.h"
#define PCI_ACCESS_READ 0
#define PCI_ACCESS_WRITE 1
#define PCIBIOS_SUCCESSFUL 0x00
#define PCIBIOS_DEVICE_NOT_FOUND 0x86
#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
#define PCI_BASE_ADDRESS_SPACE_IO 0x01
#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
#define IORESOURCE_IO 0x00000100 /* Resource type */
#define IORESOURCE_MEM 0x00000200
#define IORESOURCE_IRQ 0x00000400
#define IORESOURCE_DMA 0x00000800
#define IORESOURCE_PREFETCH 0x00001000 /* No side effects */
#define PCI_CLASS_BRIDGE_PCI 0x0604
#define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 revision */
#define PCI_REVISION_ID 0x08 /* Revision ID */
#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
#define PCI_CLASS_DEVICE 0x0a /* Device class */
#define le32_to_cpu(x) (x)
#define le64_to_cpu(x) (x)
#define cpu_to_le32(x) (x)
#define cpu_to_le64(x) (x)
#define CKSEG1ADDR(x) (x|0xa0000000)
typedef u_int32_t pcireg_t; /* configuration space register XXX */
typedef unsigned long device_t;
u32 _pci_conf_readn(device_t tag, int reg, int width)
{
tgt_printf("[%s]--ERROR!!\n",__func__);
return 0;
}
void _pci_conf_writen(device_t tag, int reg, u32 data,int width)
{
tgt_printf("[%s]-ERROR!!\n",__func__);
return ;
}
u32 _pci_conf_read(device_t tag, int reg)
{
u32 val;
int busnum;
int device;
int function;
int port_num;
_pci_break_tag (tag, &busnum, &device, &function);
port_num = busnum / 2;
ls2h_pcibios_read_port(tag, reg, 4, &val, port_num);
return val;
}
u32 _pci_conf_read32(device_t tag,int reg)
{
u32 val;
int busnum;
int device;
int function;
int port_num;
_pci_break_tag (tag, &busnum, &device, &function);
port_num = busnum / 2;
ls2h_pcibios_read_port(tag, reg, 4, &val,port_num);
return val;
}
u32 _pci_conf_read8(device_t tag,int reg)
{
u32 val;
int busnum;
int device;
int function;
int port_num;
_pci_break_tag (tag, &busnum, &device, &function);
port_num = busnum / 2;
ls2h_pcibios_read_port(tag, reg, 1, &val,port_num);
return (u8)val;
}
u32 _pci_conf_read16(device_t tag,int reg)
{
u32 val;
int busnum;
int device;
int function;
int port_num;
_pci_break_tag (tag, &busnum, &device, &function);
port_num = busnum / 2;
ls2h_pcibios_read_port(tag, reg, 2, &val,port_num);
return (u16)val;
}
void _pci_conf_write(device_t tag, int reg, u32 data)
{
int busnum;
int device;
int function;
int port_num;
_pci_break_tag (tag, &busnum, &device, &function);
port_num = busnum / 2;
ls2h_pcibios_write_port(tag, reg, 4, data,port_num);
return ;
}
void _pci_conf_write32(device_t tag, int reg, u32 data)
{
int busnum;
int device;
int function;
int port_num;
_pci_break_tag (tag, &busnum, &device, &function);
port_num = busnum / 2;
ls2h_pcibios_write_port(tag, reg, 4, data,port_num);
return ;
}
void _pci_conf_write8(device_t tag, int reg, u8 data)
{
int busnum;
int device;
int function;
int port_num;
_pci_break_tag (tag, &busnum, &device, &function);
port_num = busnum / 2;
u32 val = data;
ls2h_pcibios_write_port(tag, reg, 1, val,port_num);
return;
}
void _pci_conf_write16(device_t tag, int reg, u16 data)
{
int busnum;
int device;
int function;
int port_num;
_pci_break_tag (tag, &busnum, &device, &function);
port_num = busnum / 2;
u16 val = data;
ls2h_pcibios_write_port(tag, reg, 2, val,port_num);
return ;
}
u32 ls2h_pcie_bar_translate(unsigned char access_type, u32 bar_in, unsigned char portnum)
{
#if 0
atic unsigned char tag_mem = 0, tag_io = 0;
if (portnum > LS2H_PCIE_MAX_PORTNUM)
return bar_in;
if ((access_type == PCI_ACCESS_WRITE) && LIE_IN_WINDOW(bar_in, \
LS2H_PCIE_MEM0_DOWN_BASE, LS2H_PCIE_MEM0_DOWN_MASK))
return MAP_2_WINDOW(bar_in, LS2H_PCIE_MEM0_UP_BASE,
LS2H_PCIE_MEM0_UP_MASK);
//it's a little tricky here
if ((access_type == PCI_ACCESS_READ) && LIE_IN_WINDOW(bar_in, \
LS2H_PCIE_MEM0_UP_BASE, LS2H_PCIE_MEM0_UP_MASK)) {
if (tag_mem)
return MAP_2_WINDOW(bar_in, LS2H_PCIE_MEM0_BASE_PORT(portnum),
LS2H_PCIE_MEM0_UP_MASK);
else {
tag_mem = 1;
return bar_in;
}
}
if ((access_type == PCI_ACCESS_WRITE) && LIE_IN_WINDOW(bar_in, \
LS2H_PCIE_IO_DOWN_BASE, LS2H_PCIE_IO_DOWN_MASK))
return MAP_2_WINDOW(bar_in, LS2H_PCIE_IO_UP_BASE,
LS2H_PCIE_IO_UP_MASK);
if ((access_type == PCI_ACCESS_READ) && LIE_IN_WINDOW(bar_in, \
LS2H_PCIE_IO_UP_BASE, LS2H_PCIE_IO_UP_MASK) &&
(bar_in & PCI_BASE_ADDRESS_SPACE_IO)) {
if (tag_io)
return bar_in;
else {
tag_io = 1;
return bar_in;
}
}
#endif
return bar_in;
}
void cfg_device_read(
unsigned int type, unsigned int bus_num,
unsigned int dev_num, unsigned int func_num,
unsigned int reg_id, unsigned int * read_data,
unsigned int port_id
)
{
unsigned int port_ctrl = CKSEG1ADDR(LS2H_PCIE_REG_BASE_PORT(port_id));
unsigned int port_cfg = CKSEG1ADDR(LS2H_PCIE_DEV_HEAD_BASE_PORT(port_id));
*(volatile unsigned char *)( port_ctrl + 0x24) = (type&0x1) | (bus_num<< 24) | (dev_num <<19) | (func_num <<16);
//*(read_data) = *(volatile unsigned int *)( port_cfg + (reg_id<<2));
*(read_data) = *(volatile unsigned int *)( port_cfg + (reg_id));
}
void cfg_device_write(
unsigned int type, unsigned int bus_num,
unsigned int dev_num, unsigned int func_num,
unsigned int reg_id, unsigned int write_data,
unsigned int port_id
)
{
unsigned int port_ctrl = CKSEG1ADDR(LS2H_PCIE_REG_BASE_PORT(port_id));
unsigned int port_cfg = CKSEG1ADDR(LS2H_PCIE_DEV_HEAD_BASE_PORT(port_id));
*(volatile unsigned char *)( port_ctrl + 0x24) = (type&0x1) | (bus_num << 24) | (dev_num <<19) | (func_num <<16);
//*(volatile unsigned int *)( port_cfg + (reg_id<<2)) = write_data;
*(volatile unsigned int *)( port_cfg + (reg_id)) = write_data;
}
int ls2h_pci_config_access(unsigned char access_type,
device_t tag, int where, u32 * data, unsigned char portnum)
{
int busnum ;
u32 addr, type;
u32 addr_i, cfg_addr, reg_data;
u32 datarp;
void *addrp;
int device;
int function;
int reg = where & ~3;
unsigned char need_bar_translate = 0;
static int mytmp = 0;
_pci_break_tag (tag, &busnum, &device, &function);
if (portnum > LS2H_PCIE_MAX_PORTNUM)
return PCIBIOS_DEVICE_NOT_FOUND;
// if (!bus->parent) {
if(!(busnum % 2)){
/* in-chip virtual-bus has no parent,
so access is routed to PORT_HEAD */
if (device > 0 || function > 0) {
*data = -1; /* only one Controller lay on a virtual-bus */
return PCIBIOS_DEVICE_NOT_FOUND;
}
else {
addr = LS2H_PCIE_PORT_HEAD_BASE_PORT(portnum) | reg;
if (reg == PCI_BASE_ADDRESS_0)
/* the default value of PCI_BASE_ADDRESS_0 of
PORT_HEAD is wrong, use PCI_BASE_ADDESS_1 instead */
addr += 4;
}
} else {
/* offboard PCIE-bus has parent,
so access is routed to DEV_HEAD */
/* check if LTSSM of controller link-up */
addr_i = LS2H_PCIE_REG_BASE_PORT(portnum)
| LS2H_PCIE_PORT_REG_STAT1;
addrp = (void *)CKSEG1ADDR(addr_i);
reg_data = le32_to_cpu(*(volatile unsigned int *)addrp);
if (busnum > 255 || device > 31 || function > 1
|| !(reg_data & LS2H_PCIE_REG_STAT1_BIT_LINKUP)) {
*data = -1; /* link is not up at all */
return PCIBIOS_DEVICE_NOT_FOUND;
}
//if (!bus->parent->parent) {
if(1){
/* the bus is child of virtual-bus(pcie slot),
so use Type 0 access for device on it */
if (device > 0) {
*data = -1; /* only one device on PCIE slot */
return PCIBIOS_DEVICE_NOT_FOUND;
}
type = 0;
} else {
/* the bus is emitted from offboard-bridge,
so use Type 1 access for device on it */
type = 1;
}
/* write busnum/devnum/funcnum/type into PCIE_REG_BASE +0x24 */
addr_i = LS2H_PCIE_REG_BASE_PORT(portnum)
| LS2H_PCIE_PORT_REG_CFGADDR;
cfg_addr = (busnum << 16) | (device << 11) | (function << 8) | type;
addrp = (void *)CKSEG1ADDR(addr_i);
*(volatile unsigned int *)addrp = cpu_to_le32(cfg_addr);
/* access mapping memory instead of direct configuration access */
addr = LS2H_PCIE_DEV_HEAD_BASE_PORT(portnum) | reg;
if (reg >= PCI_BASE_ADDRESS_0 && reg <= PCI_BASE_ADDRESS_5)
/* Base Address Register need to be translated */
need_bar_translate = 1;
}
addrp = (void *)CKSEG1ADDR(addr);
if (access_type == PCI_ACCESS_WRITE) {
if (need_bar_translate) {
datarp = ls2h_pcie_bar_translate(PCI_ACCESS_WRITE, *data, portnum);
} else
datarp = *data;
*(volatile unsigned int *)addrp = cpu_to_le32(datarp);
} else {
datarp = le32_to_cpu(*(volatile unsigned int *)addrp);
if (need_bar_translate) {
*data = ls2h_pcie_bar_translate(PCI_ACCESS_READ, datarp, portnum);
} else
*data = datarp;
}
return PCIBIOS_SUCCESSFUL;
}
int ls2h_pcibios_read_port(device_t tag, int where, int size, u32 * val,int port_num)
{
u32 data = 0;
*val = -1;
if (ls2h_pci_config_access(PCI_ACCESS_READ, tag, where, &data, port_num))
return PCIBIOS_DEVICE_NOT_FOUND;
if (size == 1)
*val = (data >> ((where & 3) << 3)) & 0xff;
else if (size == 2)
*val = (data >> ((where & 3) << 3)) & 0xffff;
else
*val = data;
return PCIBIOS_SUCCESSFUL;
}
int ls2h_pcibios_write_port(device_t tag, int where, int size, u32 val,int port_num)
{
u32 data = 0;
if (size == 4)
data = val;
else {
if (ls2h_pci_config_access(PCI_ACCESS_READ, tag, where, &data, port_num))
return PCIBIOS_DEVICE_NOT_FOUND;
if (size == 1)
data = (data & ~(0xff << ((where & 3) << 3))) |
(val << ((where & 3) << 3));
else if (size == 2)
data = (data & ~(0xffff << ((where & 3) << 3))) |
(val << ((where & 3) << 3));
}
if (ls2h_pci_config_access(PCI_ACCESS_WRITE, tag, where, &data, port_num))
return PCIBIOS_DEVICE_NOT_FOUND;
return PCIBIOS_SUCCESSFUL;
}
static void en_ref_clock(void)
{
unsigned int data;
data = ls2h_readl(LS2H_CLK_CTRL3_REG);
data |= (LS2H_CLK_CTRL3_BIT_PEREF_EN(0)
| LS2H_CLK_CTRL3_BIT_PEREF_EN(1)
| LS2H_CLK_CTRL3_BIT_PEREF_EN(2)
| LS2H_CLK_CTRL3_BIT_PEREF_EN(3));
ls2h_writel(data, LS2H_CLK_CTRL3_REG);
}
static int is_rc_mode(void)
{
unsigned data;
data = ls2h_readl(LS2H_PCIE_REG_BASE_PORT(0)
| LS2H_PCIE_PORT_REG_CTR_STAT);
return data & LS2H_PCIE_REG_CTR_STAT_BIT_ISRC;
}
int is_x4_mode(void)
{
unsigned data;
data = ls2h_readl(LS2H_PCIE_REG_BASE_PORT(0)
| LS2H_PCIE_PORT_REG_CTR_STAT);
return data & LS2H_PCIE_REG_CTR_STAT_BIT_ISX4;
}
void ls2h_pcie_port_init(int port)
{
unsigned reg, data;
reg = LS2H_PCIE_PORT_HEAD_BASE_PORT(port) | 0x7c;
data = ls2h_readl(reg);
data &= ~0xf;
data |=1;
ls2h_writel(data, reg);
reg = LS2H_PCIE_REG_BASE_PORT(port) | LS2H_PCIE_PORT_REG_CTR0;
ls2h_writel(0xff204c, reg);
reg = LS2H_PCIE_PORT_HEAD_BASE_PORT(port) | PCI_CLASS_REVISION;
data = ls2h_readl(reg);
data &= 0xffff;
data |= (PCI_CLASS_BRIDGE_PCI << 16);
ls2h_writel(data, reg);
}
int ls2h_pcibios_init(void)
{
tgt_printf("arch_initcall:pcibios_init\n");
en_ref_clock();
if (!is_rc_mode())
return 0;
ls2h_pcie_port_init(0);
if (is_x4_mode())
{
tgt_printf(" x4 mode\n");
return 0;
}
ls2h_pcie_port_init(1);
ls2h_pcie_port_init(2);
ls2h_pcie_port_init(3);
return 0;
}

73
Targets/Bonito3a2h/pci/pci_machdep.c
View File

@ -82,6 +82,8 @@ _pci_hwinit(initialise, iot, memt)
struct pci_device *pd;
struct pci_bus *pb;
int newcfg=0;
int i,k;
if(getenv("newcfg"))newcfg=1;
if (!initialise) {
@ -95,6 +97,11 @@ _pci_hwinit(initialise, iot, memt)
/*
* PCI Bus 0
*/
if (is_x4_mode())
k = 1;
else
k = 4;
for (i = 0;i < k;i++) {
pd = pmalloc(sizeof(struct pci_device));
pb = pmalloc(sizeof(struct pci_bus));
if(pd == NULL || pb == NULL) {
@ -113,15 +120,46 @@ _pci_hwinit(initialise, iot, memt)
pd->pa.pa_memt->bus_base = 0xc0000000;
pd->pa.pa_dmat = &bus_dmamap_tag;
pd->bridge.secbus = pb;
_pci_head = pd;
#ifdef LS3_HT /* whd */
pb->minpcimemaddr = BONITO_PCILO0_BASE;
pb->nextpcimemaddr = BONITO_PCILO0_BASE+BONITO_PCILO_SIZE;
pb->minpciioaddr = PCI_IO_SPACE_BASE+0x0004000;
pb->nextpciioaddr = PCI_IO_SPACE_BASE+ BONITO_PCIIO_SIZE;
pb->pci_mem_base = BONITO_PCILO_BASE_VA;
pb->pci_io_base = BONITO_PCIIO_BASE_VA;
if (i == 0) {
_pci_head = pd;
} else if (i == 1){
_pci_head->next = pd;
} else if (i == 2){
_pci_head->next->next = pd;
} else if (i == 3){
_pci_head->next->next->next = pd;
}
#ifdef LS3_HT /* whd */
if (i == 0) {
pb->minpcimemaddr = 0x10000000;
pb->nextpcimemaddr = 0x12000000;
pb->minpciioaddr = 0x18100000;
pb->nextpciioaddr = 0x18110000;
pb->pci_mem_base = 0x10000000;
pb->pci_io_base = 0x18100000;
} else if (i == 1){
pb->minpcimemaddr = 0x12000000;
pb->nextpcimemaddr = 0x14000000;
pb->minpciioaddr = 0x18500000;
pb->nextpciioaddr = 0x18510000;
pb->pci_mem_base = 0x12000000;
pb->pci_io_base = 0x18500000;
} else if (i == 2){
pb->minpcimemaddr = 0x14000000;
pb->nextpcimemaddr = 0x16000000;
pb->minpciioaddr = 0x18900000;
pb->nextpciioaddr = 0x18910000;
pb->pci_mem_base = 0x14000000;
pb->pci_io_base = 0x18900000;
} else if (i == 3){
pb->minpcimemaddr = 0x16000000;
pb->nextpcimemaddr = 0x18000000;
pb->minpciioaddr = 0x18d00000;
pb->nextpciioaddr = 0x18e10000;
pb->pci_mem_base = 0x16000000;
pb->pci_io_base = 0x18d00000;
}
#else
if(newcfg)
{
@ -157,9 +195,16 @@ _pci_hwinit(initialise, iot, memt)
pb->prefetch = 1;
pb->bandwidth = 4000000;
pb->ndev = 1;
if (i == 0)
_pci_bushead = pb;
_pci_bus[_max_pci_bus++] = pd;
else if (i == 1)
_pci_bushead->next = pb;
else if (i == 2)
_pci_bushead->next->next = pb;
else if (i == 3)
_pci_bushead->next->next->next = pb;
_pci_bus[_max_pci_bus++] = pd;
bus_dmamap_tag._dmamap_offs = 0;
@ -169,7 +214,11 @@ _pci_hwinit(initialise, iot, memt)
#else
BONITO_PCIBASE0 = 0x80000000;
#endif
}
if (is_x4_mode())
return(1);
else
return(7);
}
/*
@ -203,7 +252,6 @@ _pci_dmamap(va, len)
}
#if 1
/*
* Map the PCI address of an area of local memory to a CPU physical
* address.
@ -215,7 +263,6 @@ _pci_cpumap(pcia, len)
{
return PA_TO_VA(pcia - pci_local_mem_pci_base);
}
#endif
/*
@ -260,9 +307,7 @@ _pci_canscan (pcitag_t tag)
int bus, device, function;
_pci_break_tag (tag, &bus, &device, &function);
if((bus == 0 ) && device == 0) {
return(0); /* Ignore the Discovery itself */
}
return (1);
}

21
pmon/cmds/pcicmds.c
View File

@ -200,7 +200,7 @@ extern char *optarg;
maxbus = 255;
firstdev = 0;
maxdev = 31;
#if (defined LOONGSON_3A2H) || (defined LOONGSON_3C2H)
#ifdef LOONGSON_3C2H
printf("----------------------------------\n");
printf("Warn:LS3A2H don't use this command\n");
printf("----------------------------------\n");
@ -232,7 +232,22 @@ extern char *optarg;
return (-1);
}
}
#ifdef LOONGSON_3A2H
if (is_x4_mode()) {
printf("Is x4 mode!\n");
maxbus = 1;
} else if (ac == 2) {
bus = 2 * atoi(av[1]);
if (bus >= 0 && bus < 7)
maxbus = bus + 1;
else {
bus = 0;
maxbus = 7;
printf("THE PORT ONLY 0 ~ 3\n");
}
} else
maxbus = 7;
#endif
for (; bus <= maxbus; bus++) {
ndevs = 0;
for(dev = firstdev; dev <= maxdev; dev++) {
@ -282,9 +297,11 @@ pci_query_bar(tag, index)
if( old_bar & 0x1 ){
//printf("0x%08x:0x%08x i/o @0x%08x, %d bytes\n", old_bar, bar, old_bar & 0xfffffffc, (~(bar&0xfffffffc))+1);
printf("0x%08x:0x%08x i/o @0x%08x, %d bytes \n", old_bar, bar, old_bar & 0xfffffffc, (((bar&0xfffffffc)^((bar&0xfffffffc)-1))+1)>>1);
#ifndef LOONGSON_3A2H
}else if(old_bar & 0x4){
printf("64-bit mem\n");
skipnext = 1;
#endif
}else {
//printf("0x%08x:0x%08x mem @0x%08x, %d bytes\n", old_bar, bar, old_bar & 0xfffffff0, (~(bar&0xfffffff0))+1);
printf("0x%08x:0x%08x mem @0x%08x, %d bytes \n", old_bar, bar, old_bar & 0xfffffff0, (((bar&0xfffffff0)^((bar&0xfffffff0)-1))+1)>>1);

20
sys/dev/pci/pciconf.c
View File

@ -113,6 +113,14 @@ struct tgt_bus_space def_bus_iot; /* Default bus tags */
struct tgt_bus_space def_bus_memt; /* Default bus tags */
struct pci_device *_pci_head;
struct pci_bus *_pci_bushead;
#ifdef LOONGSON_3A2H
struct pci_device *_pci_head1;
struct pci_device *_pci_head2;
struct pci_device *_pci_head3;
struct pci_bus *_pci_bushead1;
struct pci_bus *_pci_bushead2;
struct pci_bus *_pci_bushead3;
#endif
struct pci_intline_routing *_pci_inthead;
struct pci_device *vga_dev = NULL,*pcie_dev = NULL;
@ -1019,7 +1027,11 @@ tgt_putchar('2');
if (_pciverbose) {
printf("setting up %d bus\n", init);
}
#ifdef LOONGSON_3A2H
for(i = 0, pb = _pci_head; i < pci_roots; i+=2, pb = pb->next) {
#else
for(i = 0, pb = _pci_head; i < pci_roots; i++, pb = pb->next) {
#endif
_pci_scan_dev(pb, i, 0, init);
}
_setup_pcibuses(init);
@ -1137,7 +1149,11 @@ _setup_pcibuses(int initialise)
/* setup the individual device windows */
SBD_DISPLAY ("PCIW", CHKPNT_PCIW);
#ifdef LOONGSON_3A2H
for(i = 0, pd = _pci_head; i < pci_roots; i+=2, pd = pd->next) {
#else
for(i = 0, pd = _pci_head; i < pci_roots; i++, pd = pd->next) {
#endif
_pci_setup_windows (pd);
}
@ -1155,7 +1171,11 @@ _pci_devinit (int initialise)
int i;
struct pci_device *pd;
#ifdef LOONGSON_3A2H
for(i = 0, pd = _pci_head; i < pci_roots; i+=2, pd = pd->next) {
#else
for(i = 0, pd = _pci_head; i < pci_roots; i++, pd = pd->next) {
#endif
_pci_setup_devices (pd, initialise);
}
}

8
sys/dev/pci/pcivar.h
View File

@ -262,6 +262,14 @@ struct pci_device {
extern struct pci_device *_pci_head;
extern struct pci_bus *_pci_bushead;
#ifdef LOONGSON_3A2H
extern struct pci_device *_pci_head1;
extern struct pci_bus *_pci_bushead1;
extern struct pci_device *_pci_head2;
extern struct pci_bus *_pci_bushead2;
extern struct pci_device *_pci_head3;
extern struct pci_bus *_pci_bushead3;
#endif
extern struct pci_intline_routing *_pci_inthead;
extern int InitInterruptRouting(void);

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