ls2k
/
pmon
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity
Browse Source

3a3000 leveling file update,add some dll training program 

Change-Id: I47cfe6c611726be19a2110027619e18662c2cc75
master
wuze 6 years ago
committed by 吴泽
parent
b110c9119d
commit
2872dd1ceb
5 changed files with 3106 additions and 2480 deletions
Whitespace
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
Split View
Diff Options
Show Stats Download Patch File Download Diff File
  1. 484
      Targets/Bonito3a3000_7a/Bonito/loongson_mc2_param.S
  2. 6
      Targets/Bonito3a3000_7a/Bonito/start.S
  3. 49
      pmon/arch/mips/mm/ddr_leveling_define.h
  4. 266
      pmon/arch/mips/mm/loongson3C_ddr3_leveling.S
  5. 89
      pmon/arch/mips/mm/ls3A8_ddr_config.S

484
Targets/Bonito3a3000_7a/Bonito/loongson_mc2_param.S
View File

@ -260,7 +260,7 @@ MC0_DDR3_RDIMM_CTRL_0x010: .dword 0x0000000000000000
//MC0_DDR3_RDIMM_CTRL_0x018: .dword 0x5252525216100000
//MC0_DDR3_RDIMM_CTRL_0x018: .dword 0x4040404016100000
//MC0_DDR3_RDIMM_CTRL_0x018: .dword 0x3030303016100000
MC0_DDR3_RDIMM_CTRL_0x018: .dword 0x5050505016100000
MC0_DDR3_RDIMM_CTRL_0x018: .dword 0x4343434316100000
//MC0_DDR3_RDIMM_CTRL_0x018: .dword 0x2525252516100000
//_00000000 pm_dll_ck_3 _00000000 pm_dll_ck_2 _00000000 pm_dll_ck_1 _00000000 pm_dll_ck_0 _00000000 pm_dll_increment _00000000 pm_dll_start_point _0000000_0 pm_dll_bypass _0000000_0 pm_init_start
MC0_DDR3_RDIMM_CTRL_0x020: .dword 0x0201000201000000
@ -500,7 +500,7 @@ MC1_DDR3_RDIMM_CTRL_0x010: .dword 0x0000000000000000
//MC1_DDR3_RDIMM_CTRL_0x018: .dword 0x5252525216100000
//MC1_DDR3_RDIMM_CTRL_0x018: .dword 0x4040404016100000
//MC1_DDR3_RDIMM_CTRL_0x018: .dword 0x3030303016100000
MC1_DDR3_RDIMM_CTRL_0x018: .dword 0x5050505016100000
MC1_DDR3_RDIMM_CTRL_0x018: .dword 0x4a4a4a4a16100000
//MC1_DDR3_RDIMM_CTRL_0x018: .dword 0x2525252516100000
//_00000000 pm_dll_ck_3 _00000000 pm_dll_ck_2 _00000000 pm_dll_ck_1 _00000000 pm_dll_ck_0 _00000000 pm_dll_increment _00000000 pm_dll_start_point _0000000_0 pm_dll_bypass _0000000_0 pm_init_start
MC1_DDR3_RDIMM_CTRL_0x020: .dword 0x0201000201000000
@ -730,3 +730,483 @@ MC1_DDR3_RDIMM_CTRL_0x388: .dword 0x0000000000000000
MC1_DDR3_RDIMM_CTRL_0x390: .dword 0x0000000000000000
MC1_DDR3_RDIMM_CTRL_0x398: .dword 0x0000000000000000
n1_ddr3_RDIMM_reg_data:
MC2_DDR3_RDIMM_CTRL_0x000: .dword 0x0300000000000000
//XXXX pm_dll_value_0(RD) XXXX pm_dll_value_ck(RD) XXXX pm_dll_init_done(RD) XXXX pm_version(RD)
MC2_DDR3_RDIMM_CTRL_0x008: .dword 0x0000000000000000
//XXXX pm_dll_value_4(RD) XXXX pm_dll_value_3 (RD) XXXX pm_dll_value_2(RD) XXXX pm_dll_value_1(RD)
MC2_DDR3_RDIMM_CTRL_0x010: .dword 0x0000000000000000
//XXXX pm_dll_value_8(RD) XXXX pm_dll_value_7 (RD) XXXX pm_dll_value_6(RD) XXXX pm_dll_value_5(RD)
//MC2_DDR3_RDIMM_CTRL_0x018: .dword 0x5252525216100000
//MC2_DDR3_RDIMM_CTRL_0x018: .dword 0x4040404016100000
//MC2_DDR3_RDIMM_CTRL_0x018: .dword 0x3030303016100000
MC2_DDR3_RDIMM_CTRL_0x018: .dword 0x3d3d3d3d16100000
//MC2_DDR3_RDIMM_CTRL_0x018: .dword 0x2525252516100000
//_00000000 pm_dll_ck_3 _00000000 pm_dll_ck_2 _00000000 pm_dll_ck_1 _00000000 pm_dll_ck_0 _00000000 pm_dll_increment _00000000 pm_dll_start_point _0000000_0 pm_dll_bypass _0000000_0 pm_init_start
MC2_DDR3_RDIMM_CTRL_0x020: .dword 0x0201000201000000
//0000_0000 pm_dq_oe_end_0 0000_0000 pm_dq_oe_begin_0 000000_00 pm_dq_stop_edge_0 000000_00 pm_dq_start_edge_0 0000000_0 pm_rddata_delay_0 0000000_0 pm_rddqs_lt_half_0 0000000_0 pm_wrdqs_lt_half_0 0000000_0 pm_wrdq_lt_half_0
MC2_DDR3_RDIMM_CTRL_0x028: .dword 0x0303020202010100
//0000_0000 pm_rd_oe_end_0 0000_0000 pm_rd_oe_begin_0 000000_00 pm_rd_stop_edge_0 000000_00 pm_rd_start_edge_0 0000_0000 pm_dqs_oe_end_0 0000_0000 pm_dqs_oe_begin_0 000000_00 pm_dqs_stop_edge_0 000000_00 pm_dqs_start_edge_0
MC2_DDR3_RDIMM_CTRL_0x030: .dword 0x0000000003020202
//hXXXXXX (RD) 0000000_0 pm_wrdq_clkdelay_0 0000_0000 pm_odt_oe_end_0 0000_0000 pm_odt_oe_begin_0 000000_00 pm_odt_stop_edge_0 000000_00 pm_odt_start_edge_0
MC2_DDR3_RDIMM_CTRL_0x038: .dword 0x0000042020056500
//hXXXXXX (RD) _00000000 pm_dll_rddqs_n_0 _00000000 pm_dll_rddqs_p_0 _00000000 pm_dll_wrdqs_0 _00000000 pm_dll_wrdata_0 _00000000 pm_dll_gate_0
MC2_DDR3_RDIMM_CTRL_0x040: .dword 0x0201000201000000
//0000_0000 pm_dq_oe_end_1 0000_0000 pm_dq_oe_begin_1 000000_00 pm_dq_stop_edge_1 000000_00 pm_dq_start_edge_1 0000000_0 pm_rddata_delay_1 0000000_0 pm_rddqs_lt_half_1 0000000_0 pm_wrdqs_lt_half_1 0000000_0 pm_wrdq_lt_half_1
MC2_DDR3_RDIMM_CTRL_0x048: .dword 0x0303020202010100
//0000_0000 pm_rd_oe_end_1 0000_0000 pm_rd_oe_begin_1 000000_00 pm_rd_stop_edge_1 000000_00 pm_rd_start_edge_1 0000_0000 pm_dqs_oe_end_1 0000_0000 pm_dqs_oe_begin_1 000000_00 pm_dqs_stop_edge_1 000000_00 pm_dqs_start_edge_1
MC2_DDR3_RDIMM_CTRL_0x050: .dword 0x0000000003020202
//hXXXXXX (RD) 0000000_0 pm_wrdq_clkdelay_1 0000_0000 pm_odt_oe_end_1 0000_0000 pm_odt_oe_begin_1 000000_00 pm_odt_stop_edge_1 000000_00 pm_odt_start_edge_1
MC2_DDR3_RDIMM_CTRL_0x058: .dword 0x0000042020056500
//hXXXXXX (RD) _00000000 pm_dll_rddqs_n_1 _00000000 pm_dll_rddqs_p_1 _00000000 pm_dll_wrdqs_1 _00000000 pm_dll_wrdata_1 _00000000 pm_dll_gate_1
MC2_DDR3_RDIMM_CTRL_0x060: .dword 0x0201000201000000
//0000_0000 pm_dq_oe_end_2 0000_0000 pm_dq_oe_begin_2 000000_00 pm_dq_stop_edge_2 000000_00 pm_dq_start_edge_2 0000000_0 pm_rddata_delay_2 0000000_0 pm_rddqs_lt_half_2 0000000_0 pm_wrdqs_lt_half_2 0000000_0 pm_wrdq_lt_half_2
MC2_DDR3_RDIMM_CTRL_0x068: .dword 0x0303020202010100
//0000_0000 pm_rd_oe_end_2 0000_0000 pm_rd_oe_begin_2 000000_00 pm_rd_stop_edge_2 000000_00 pm_rd_start_edge_2 0000_0000 pm_dqs_oe_end_2 0000_0000 pm_dqs_oe_begin_2 000000_00 pm_dqs_stop_edge_2 000000_00 pm_dqs_start_edge_2
MC2_DDR3_RDIMM_CTRL_0x070: .dword 0x0000000003020202
//hXXXXXX (RD) 0000000_0 pm_wrdq_clkdelay_2 0000_0000 pm_odt_oe_end_2 0000_0000 pm_odt_oe_begin_2 000000_00 pm_odt_stop_edge_2 000000_00 pm_odt_start_edge_2
MC2_DDR3_RDIMM_CTRL_0x078: .dword 0x0000042020056500
//hXXXXXX (RD) _00000000 pm_dll_rddqs_n_2 _00000000 pm_dll_rddqs_p_2 _00000000 pm_dll_wrdqs_2 _00000000 pm_dll_wrdata_2 _00000000 pm_dll_gate_2
MC2_DDR3_RDIMM_CTRL_0x080: .dword 0x0201000201000000
//0000_0000 pm_dq_oe_end_3 0000_0000 pm_dq_oe_begin_3 000000_00 pm_dq_stop_edge_3 000000_00 pm_dq_start_edge_3 0000000_0 pm_rddata_delay_3 0000000_0 pm_rddqs_lt_half_3 0000000_0 pm_wrdqs_lt_half_3 0000000_0 pm_wrdq_lt_half_3
MC2_DDR3_RDIMM_CTRL_0x088: .dword 0x0303020202010100
//0000_0000 pm_rd_oe_end_3 0000_0000 pm_rd_oe_begin_3 000000_00 pm_rd_stop_edge_3 000000_00 pm_rd_start_edge_3 0000_0000 pm_dqs_oe_end_3 0000_0000 pm_dqs_oe_begin_3 000000_00 pm_dqs_stop_edge_3 000000_00 pm_dqs_start_edge_3
MC2_DDR3_RDIMM_CTRL_0x090: .dword 0x0000000003020202
//hXXXXXX (RD) 0000000_0 pm_wrdq_clkdelay_3 0000_0000 pm_odt_oe_end_3 0000_0000 pm_odt_oe_begin_3 000000_00 pm_odt_stop_edge_3 000000_00 pm_odt_start_edge_3
MC2_DDR3_RDIMM_CTRL_0x098: .dword 0x0000042020056500
//hXXXXXX (RD) _00000000 pm_dll_rddqs_n_3 _00000000 pm_dll_rddqs_p_3 _00000000 pm_dll_wrdqs_3 _00000000 pm_dll_wrdata_3 _00000000 pm_dll_gate_3
MC2_DDR3_RDIMM_CTRL_0x0a0: .dword 0x0201000201000000
//0000_0000 pm_dq_oe_end_4 0000_0000 pm_dq_oe_begin_4 000000_00 pm_dq_stop_edge_4 000000_00 pm_dq_start_edge_4 0000000_0 pm_rddata_delay_4 0000000_0 pm_rddqs_lt_half_4 0000000_0 pm_wrdqs_lt_half_4 0000000_0 pm_wrdq_lt_half_4
MC2_DDR3_RDIMM_CTRL_0x0a8: .dword 0x0303020202010100
//0000_0000 pm_rd_oe_end_4 0000_0000 pm_rd_oe_begin_4 000000_00 pm_rd_stop_edge_4 000000_00 pm_rd_start_edge_4 0000_0000 pm_dqs_oe_end_4 0000_0000 pm_dqs_oe_begin_4 000000_00 pm_dqs_stop_edge_4 000000_00 pm_dqs_start_edge_4
MC2_DDR3_RDIMM_CTRL_0x0b0: .dword 0x0000000003020202
//hXXXXXX (RD) 0000000_0 pm_wrdq_clkdelay_4 0000_0000 pm_odt_oe_end_4 0000_0000 pm_odt_oe_begin_4 000000_00 pm_odt_stop_edge_4 000000_00 pm_odt_start_edge_4
MC2_DDR3_RDIMM_CTRL_0x0b8: .dword 0x0000042020056500
//hXXXXXX (RD) _00000000 pm_dll_rddqs_n_4 _00000000 pm_dll_rddqs_p_4 _00000000 pm_dll_wrdqs_4 _00000000 pm_dll_wrdata_4 _00000000 pm_dll_gate_4
MC2_DDR3_RDIMM_CTRL_0x0c0: .dword 0x0201000201000000
//0000_0000 pm_dq_oe_end_5 0000_0000 pm_dq_oe_begin_5 000000_00 pm_dq_stop_edge_5 000000_00 pm_dq_start_edge_5 0000000_0 pm_rddata_delay_5 0000000_0 pm_rddqs_lt_half_5 0000000_0 pm_wrdqs_lt_half_5 0000000_0 pm_wrdq_lt_half_5
MC2_DDR3_RDIMM_CTRL_0x0c8: .dword 0x0303020202010100
//0000_0000 pm_rd_oe_end_5 0000_0000 pm_rd_oe_begin_5 000000_00 pm_rd_stop_edge_5 000000_00 pm_rd_start_edge_5 0000_0000 pm_dqs_oe_end_5 0000_0000 pm_dqs_oe_begin_5 000000_00 pm_dqs_stop_edge_5 000000_00 pm_dqs_start_edge_5
MC2_DDR3_RDIMM_CTRL_0x0d0: .dword 0x0000000003020202
//hXXXXXX (RD) 0000000_0 pm_wrdq_clkdelay_5 0000_0000 pm_odt_oe_end_5 0000_0000 pm_odt_oe_begin_5 000000_00 pm_odt_stop_edge_5 000000_00 pm_odt_start_edge_5
MC2_DDR3_RDIMM_CTRL_0x0d8: .dword 0x0000042020056500
//hXXXXXX (RD) _00000000 pm_dll_rddqs_n_5 _00000000 pm_dll_rddqs_p_5 _00000000 pm_dll_wrdqs_5 _00000000 pm_dll_wrdata_5 _00000000 pm_dll_gate_5
MC2_DDR3_RDIMM_CTRL_0x0e0: .dword 0x0201000201000000
//0000_0000 pm_dq_oe_end_6 0000_0000 pm_dq_oe_begin_6 000000_00 pm_dq_stop_edge_6 000000_00 pm_dq_start_edge_6 0000000_0 pm_rddata_delay_6 0000000_0 pm_rddqs_lt_half_6 0000000_0 pm_wrdqs_lt_half_6 0000000_0 pm_wrdq_lt_half_6
MC2_DDR3_RDIMM_CTRL_0x0e8: .dword 0x0303020202010100
//0000_0000 pm_rd_oe_end_6 0000_0000 pm_rd_oe_begin_6 000000_00 pm_rd_stop_edge_6 000000_00 pm_rd_start_edge_6 0000_0000 pm_dqs_oe_end_6 0000_0000 pm_dqs_oe_begin_6 000000_00 pm_dqs_stop_edge_6 000000_00 pm_dqs_start_edge_6
MC2_DDR3_RDIMM_CTRL_0x0f0: .dword 0x0000000003020202
//hXXXXXX (RD) 0000000_0 pm_wrdq_clkdelay_6 0000_0000 pm_odt_oe_end_6 0000_0000 pm_odt_oe_begin_6 000000_00 pm_odt_stop_edge_6 000000_00 pm_odt_start_edge_6
MC2_DDR3_RDIMM_CTRL_0x0f8: .dword 0x0000042020056500
//hXXXXXX (RD) _00000000 pm_dll_rddqs_n_6 _00000000 pm_dll_rddqs_p_6 _00000000 pm_dll_wrdqs_6 _00000000 pm_dll_wrdata_6 _00000000 pm_dll_gate_6
MC2_DDR3_RDIMM_CTRL_0x100: .dword 0x0201000201000000
//0000_0000 pm_dq_oe_end_7 0000_0000 pm_dq_oe_begin_7 000000_00 pm_dq_stop_edge_7 000000_00 pm_dq_start_edge_7 0000000_0 pm_rddata_delay_7 0000000_0 pm_rddqs_lt_half_7 0000000_0 pm_wrdqs_lt_half_7 0000000_0 pm_wrdq_lt_half_7
MC2_DDR3_RDIMM_CTRL_0x108: .dword 0x0303020202010100
//0000_0000 pm_rd_oe_end_7 0000_0000 pm_rd_oe_begin_7 000000_00 pm_rd_stop_edge_7 000000_00 pm_rd_start_edge_7 0000_0000 pm_dqs_oe_end_7 0000_0000 pm_dqs_oe_begin_7 000000_00 pm_dqs_stop_edge_7 000000_00 pm_dqs_start_edge_7
MC2_DDR3_RDIMM_CTRL_0x110: .dword 0x0000000003020202
//hXXXXXX (RD) 0000000_0 pm_wrdq_clkdelay_7 0000_0000 pm_odt_oe_end_7 0000_0000 pm_odt_oe_begin_7 000000_00 pm_odt_stop_edge_7 000000_00 pm_odt_start_edge_7
MC2_DDR3_RDIMM_CTRL_0x118: .dword 0x0000042020056500
//hXXXXXX (RD) _00000000 pm_dll_rddqs_n_7 _00000000 pm_dll_rddqs_p_7 _00000000 pm_dll_wrdqs_7 _00000000 pm_dll_wrdata_7 _00000000 pm_dll_gate_7
MC2_DDR3_RDIMM_CTRL_0x120: .dword 0x0201000201000000
//0000_0000 pm_dq_oe_end_8 0000_0000 pm_dq_oe_begin_8 000000_00 pm_dq_stop_edge_8 000000_00 pm_dq_start_edge_8 0000000_0 pm_rddata_delay_8 0000000_0 pm_rddqs_lt_half_8 0000000_0 pm_wrdqs_lt_half_8 0000000_0 pm_wrdq_lt_half_8
MC2_DDR3_RDIMM_CTRL_0x128: .dword 0x0303020202010100
//0000_0000 pm_rd_oe_end_8 0000_0000 pm_rd_oe_begin_8 000000_00 pm_rd_stop_edge_8 000000_00 pm_rd_start_edge_8 0000_0000 pm_dqs_oe_end_8 0000_0000 pm_dqs_oe_begin_8 000000_00 pm_dqs_stop_edge_8 000000_00 pm_dqs_start_edge_8
MC2_DDR3_RDIMM_CTRL_0x130: .dword 0x0000000003020202
//hXXXXXX (RD) 0000000_0 pm_wrdq_clkdelay_8 0000_0000 pm_odt_oe_end_8 0000_0000 pm_odt_oe_begin_8 000000_00 pm_odt_stop_edge_8 000000_00 pm_odt_start_edge_8
MC2_DDR3_RDIMM_CTRL_0x138: .dword 0x00000020207f6000
//hXXXXXX (RD) _00000000 pm_dll_rddqs_n_8 _00000000 pm_dll_rddqs_p_8 _00000000 pm_dll_wrdqs_8 _00000000 pm_dll_wrdata_8 _00000000 pm_dll_gate_8
MC2_DDR3_RDIMM_CTRL_0x140: .dword 0x0403000001ff01ff
//00000_000 pm_pad_ocd_clk 00000_000 pm_pad_ocd_ctl 0000000_0 pm_pad_ocd_dqs 0000000_0 pm_pad_ocd_dq 0000000_0_00000000 pm_pad_enzi 0000000_0 pm_pad_en_ctl _00000000 pm_pad_en_clk
MC2_DDR3_RDIMM_CTRL_0x148: .dword 0x0000000000010100
//_0000 pm_pad_adj_ncode_dq _0000 pm_pad_adj_pcode_dq 00000 _0 pm_pad_outodt_dq _0 pm_pad_slewrate_dq _0 pm_pad_code_dq _0000 pm_pad_adj_ncode_dq _0000 pm_pad_adj_pcode_dq 00000 _0 pm_pad_outodt_dq _0 pm_pad_slewrate_dq _0 00000000 0000000_0 pm_pad_vref_internal 0000000_0 pm_pad_odt_se 0000000_0 pm_pad_modezi1v8
MC2_DDR3_RDIMM_CTRL_0x150: .dword 0x00020000f0020000
//hXXXX _0000 pm_pad_adj_ncode_clk _0000 pm_pad_adj_pcode_clk 00000 _0 pm_pad_outodt_clk _0 pm_pad_slewrate_clk _0 pm_pad_code_clk _0000 pm_pad_adj_ncode_cmd _0000 pm_pad_adj_pcode_cmd 00000 _0 pm_pad_outodt_cmd _0 pm_pad_slewrate_cmd _0 pm_pad_code_cmd _0000 pm_pad_adj_ncode_addr _0000 pm_pad_adj_pcode_addr 00000 _0 pm_pad_outodt_addr _0 pm_pad_slewrate_addr _0 pm_pad_code_addr
MC2_DDR3_RDIMM_CTRL_0x158: .dword 0x00000000f0000000
//hXXXXXXXX (RD) _0000 pm_pad_comp_ncode_i _0000 pm_pad_comp_pcode_i 0000000_0 pm_pad_comp_mode 0000000_0 pm_pad_comp_tm 0000000_0 pm_pad_comp_pd
MC2_DDR3_RDIMM_CTRL_0x160: .dword 0x0000000000010101
//MC2_DDR3_RDIMM_CTRL_0x160: .dword 0x0000000000000001
//0000000_0_00000000 pm_rdfifo_empty(RD) 0000000_0_00000000 pm_overflow(RD) 0000_0000 pm_dram_init(RD) 0000000_0 pm_rdfifo_valid 000000_00 pm_cmd_timing 0000000_0 pm_ddr3_mode
MC2_DDR3_RDIMM_CTRL_0x168: .dword 0x140a000707030101
//hXX (RD) 0000_0000 pm_addr_mirror 000000_00 pm_cmd_delay _00000000 pm_burst_length 00000_000 pm_bank 0000_0000 pm_cs_zq 0000_0000 pm_cs_mrs 0000_0000 pm_cs_enable
//MC2_DDR3_RDIMM_CTRL_0x170: .dword 0x0000000001ff01ff
MC2_DDR3_RDIMM_CTRL_0x170: .dword 0x8421050084120501
//_00000000_00000000 pm_odt_wr_cs_map 0000_0000 pm_odt_wr_length 0000_0000 pm_odt_wr_delay _00000000_00000000 pm_odt_rd_cs_map 0000_0000 pm_odt_rd_length 0000_0000 pm_odt_rd_delay
MC2_DDR3_RDIMM_CTRL_0x178: .dword 0x0000000000000000
//hXXXXXXXXXXXXXXXX (RD)
MC2_DDR3_RDIMM_CTRL_0x180: .dword 0x0000000001100000
//_00000000 pm_lvl_resp_0(RD) 0000000_0 pm_lvl_done(RD) 0000000_0 pm_lvl_ready(RD) 00000000 0000_0000 pm_lvl_cs _00000000 pm_tLVL_DELAY 0000000_0 pm_leveling_req(WR) 000000_00 pm_leveling_mode
MC2_DDR3_RDIMM_CTRL_0x188: .dword 0x0000000000000000
//_00000000 pm_lvl_resp_8(RD) _00000000 pm_lvl_resp_7(RD) _00000000 _pm_lvl_resp_6(RD) _00000000 pm_lvl_resp_5(RD) _00000000 pm_lvl_resp_4(RD) _00000000 pm_lvl_resp_3(RD) _00000000 pm_lvl_resp_2(RD) _00000000 pm_lvl_resp_1(RD)
//CMD CONFIG
MC2_DDR3_RDIMM_CTRL_0x190: .dword 0x0000000000000000
//_00000000_00000000 pm_cmd_a 00000_000 pm_cmd_ba 00000_000 pm_cmd_cmd 0000_0000 pm_cmd_cs 0000000_0 pm_status_cmd(RD) 0000000_0 pm_cmd_req(WR) 0000000_0 pm_command
MC2_DDR3_RDIMM_CTRL_0x198: .dword 0x0000000000000000
//00000000 00000000 0000_0000 pm_status_sref(RD) 0000_0000 pm_srefresh_req 0000000_0 pm_pre_all_done(RD) 0000000_0 pm_pre_all_req(WR) 0000000_0 pm_mrs_done(RD) 0000000_0 pm_mrs_req(WR)
MC2_DDR3_RDIMM_CTRL_0x1a0: .dword 0x0000001000060d40
//_00000000_00000000 pm_mr_3_cs_0 _00000000_00000000 pm_mr_2_cs_0 _00000000_00000000 pm_mr_1_cs_0 _00000000_00000000 pm_mr_0_cs_0
MC2_DDR3_RDIMM_CTRL_0x1a8: .dword 0x0000001000060d40
//_00000000_00000000 pm_mr_3_cs_1 _00000000_00000000 pm_mr_2_cs_1 _00000000_00000000 pm_mr_1_cs_1 _00000000_00000000 pm_mr_0_cs_1
MC2_DDR3_RDIMM_CTRL_0x1b0: .dword 0x0000001000060d40
//_00000000_00000000 pm_mr_3_cs_2 _00000000_00000000 pm_mr_2_cs_2 _00000000_00000000 pm_mr_1_cs_2 _00000000_00000000 pm_mr_0_cs_2
MC2_DDR3_RDIMM_CTRL_0x1b8: .dword 0x0000001000060d40
//_00000000_00000000 pm_mr_3_cs_3 _00000000_00000000 pm_mr_2_cs_3 _00000000_00000000 pm_mr_1_cs_3 _00000000_00000000 pm_mr_0_cs_3
MC2_DDR3_RDIMM_CTRL_0x1c0: .dword 0x3030c80c03042006
//_00000000 pm_tRESET _00000000 pm_tCKE _00000000 pm_tXPR _00000000 pm_tMOD _00000000 pm_tZQCL _00000000 pm_tZQ_CMD _00000000 pm_tWLDQSEN 000_00000 pm_tRDDATA
//MC2_DDR3_RDIMM_CTRL_0x1c8: .dword 0x11040b0b15904080
MC2_DDR3_RDIMM_CTRL_0x1c8: .dword 0x11040b0b22c34080
//00_000000 pm_tFAW 0000_0000 pm_tRRD 0000_0000 pm_tRCD _00000000 pm_tRP _00000000 pm_tREF _00000000 pm_tRFC _00000000 pm_tZQCS _00000000 pm_tZQperiod
MC2_DDR3_RDIMM_CTRL_0x1d0: .dword 0x0a020d0502000018
//0000_0000 pm_tODTL _00000000 pm_tXSRD 0000_0000 pm_tPHY_RDLAT 000_00000 pm_tPHY_WRLAT 000000_00_00000000_00000000 pm_tRAS_max 00_000000 pm_tRAS_min
MC2_DDR3_RDIMM_CTRL_0x1d8: .dword 0x14050c0408070405
//_00000000 pm_tXPDLL _00000000 pm_tXP 000_00000 pm_tWR 0000_0000 pm_tRTP 0000_0000 pm_tRL 0000_0000 pm_tWL 0000_0000 pm_tCCD 0000_0000 pm_tWTR
MC2_DDR3_RDIMM_CTRL_0x1e0: .dword 0x0503000000000000
//00_000000 pm_tW2R_diffcs_dly 00_000000 pm_tW2W_diffcs_adj_dly 00_000000 pm_tR2P_sameba_adj_dly 00_000000 pm_tW2P_sameba_adj_dly 00_000000 pm_tR2R_sameba_adj_dly 00_000000 pm_tR2W_sameba_adj_dly 00_000000 pm_tW2R_sameba_adj_dly 00_000000 pm_tW2W_sameba_adj_dly
MC2_DDR3_RDIMM_CTRL_0x1e8: .dword 0x030a000000010000
//00_000000 pm_tR2R_diffcs_adj_dly 00_000000 pm_tR2W_diffcs_dly 00_000000 pm_tR2P_samecs_dly 00_000000 pm_tW2P_samecs_dly 00_000000 pm_tR2R_samecs_adj_dly 00_000000 pm_tR2W_samecs_adj_dly 00_000000 pm_tW2R_samecs_adj_dly 00_000000 pm_tW2W_samecs_adj_dly
MC2_DDR3_RDIMM_CTRL_0x1f0: .dword 0x000801e4ff000101
//0000_0000 pm_power_up _00000000 pm_age_step _00000000 pm_tCPDED _00000000 pm_cs_map _00000000 pm_bs_config 00000_000 pm_channel_32 pm_channel_16 pm_nc 0000_0000 pm_pr_r2w 0000000_0 pm_placement_en
MC2_DDR3_RDIMM_CTRL_0x1f8: .dword 0x0000000004081001
//0000_0000 pm_hardware_pd_3 0000_0000 pm_hardware_pd_2 0000_0000 pm_hardware_pd_1 0000_0000 pm_hardware_pd_0 00_000000 pm_credit_16 00_000000 pm_credit_32 00_000000 pm_credit_64 0000000_0 pm_selection_en
MC2_DDR3_RDIMM_CTRL_0x200: .dword 0x0c000c000c000c00
//0000_0000_00000000 pm_cmdq_age_16 0000_0000_00000000 pm_cmdq_age_32 0000_0000_00000000 pm_cmdq_age_64 _00000000 pm_tCKESR _00000000 pm_tRDPDEN
MC2_DDR3_RDIMM_CTRL_0x208: .dword 0x0c000c0000000000
//0000_0000_00000000 pm_wrfifo_age 0000_0000_00000000 pm_rdfifo_age 0000_0000 pm_power_status_3 0000_0000 pm_power_status_2 0000_0000 pm_power_status_1 0000_0000 pm_power_status_0
MC2_DDR3_RDIMM_CTRL_0x210: .dword 0x0008010f00030006
//_00000000_00000000 pm_active_age 0000000_0 pm_cs_place_0 0000_0000 pm_addr_win_0 000000_00 pm_cs_diff_0 00000_000 pm_row_diff_0 000000_00 pm_ba_diff_0 00000_000 pm_col_diff_0
MC2_DDR3_RDIMM_CTRL_0x218: .dword 0x0008000b00030106
//_00000000_00000000 pm_fastpd_age 0000000_0 pm_cs_place_1 0000_0000 pm_addr_win_1 000000_00 pm_cs_diff_1 00000_000 pm_row_diff_1 000000_00 pm_ba_diff_1 00000_000 pm_col_diff_1
MC2_DDR3_RDIMM_CTRL_0x220: .dword 0x0008000b00030106
//_00000000_00000000 pm_slowpd_age 0000000_0 pm_cs_place_2 0000_0000 pm_addr_win_2 000000_00 pm_cs_diff_2 00000_000 pm_row_diff_2 000000_00 pm_ba_diff_2 00000_000 pm_col_diff_2
MC2_DDR3_RDIMM_CTRL_0x228: .dword 0x0008000b00030106
//_00000000_00000000 pm_selfref_age 0000000_0 pm_cs_place_3 0000_0000 pm_addr_win_3 000000_00 pm_cs_diff_3 00000_000 pm_row_diff_3 000000_00 pm_ba_diff_3 00000_000 pm_col_diff_3
MC2_DDR3_RDIMM_CTRL_0x230: .dword 0x0fff000000000000
//0000_0000_00000000_00000000_00000000 pm_addr_mask_0 0000_0000_00000000_00000000_00000000 pm_addr_base_0
MC2_DDR3_RDIMM_CTRL_0x238: .dword 0x0ffffe000000ff00
//0000_0000_00000000_00000000_00000000 pm_addr_mask_1 0000_0000_00000000_00000000_00000000 pm_addr_base_1
MC2_DDR3_RDIMM_CTRL_0x240: .dword 0x0ffffe000000ff00
//0000_0000_00000000_00000000_00000000 pm_addr_mask_2 0000_0000_00000000_00000000_00000000 pm_addr_base_2
MC2_DDR3_RDIMM_CTRL_0x248: .dword 0x0ffffe000000ff00
//0000_0000_00000000_00000000_00000000 pm_addr_mask_3 0000_0000_00000000_00000000_00000000 pm_addr_base_3
MC2_DDR3_RDIMM_CTRL_0x250: .dword 0x0000000000000000
//00000000 _00_00_00_00 pm_cmd_monitor_3_2_1_0 000000_00_00000000 pm_axi_monitor _00000000 pm_ecc_code(RD) 0000_0_000 pm_int_trigger pm_ecc_enable 000000_00 pm_int_vector 000000_00 pm_int_enable
MC2_DDR3_RDIMM_CTRL_0x258: .dword 0x0000000000000000
//XXXXXXXXXXXXXXXX (RD)
MC2_DDR3_RDIMM_CTRL_0x260: .dword 0x0000000000000000
//_XXXXXXXXXXXXXXXX pm_ecc_addr(RD)
MC2_DDR3_RDIMM_CTRL_0x268: .dword 0x0000000000000000
//_XXXXXXXXXXXXXXXX pm_ecc_data(RD)
MC2_DDR3_RDIMM_CTRL_0x270: .dword 0x0000001000000000
//000000_00 pm_lpbk_ecc_mask(RD) 0_0000000_00000000_00000000 pm_prbs_init 0000000_0 pm_lpbk_error(RD) 0000000_0 pm_prbs_23 0000000_0 pm_lpbk_start 0000000_0 pm_lpbk_en
MC2_DDR3_RDIMM_CTRL_0x278: .dword 0x0000000000000000
//_00000000_00000000 pm_lpbk_ecc(RD) _00000000_00000000 pm_lpbk_data_mask(RD) _00000000_00000000 pm_lpbk_correct(RD) _00000000_00000000 pm_lpbk_counter(RD)
MC2_DDR3_RDIMM_CTRL_0x280: .dword 0x0000000000000000
//_XXXXXXXXXXXXXXXX pm_lpbk_data[ 63: 0](RD)
MC2_DDR3_RDIMM_CTRL_0x288: .dword 0x0000000000000000
//_XXXXXXXXXXXXXXXX pm_lpbk_data[127:64](RD)
//Monitor fbck
MC2_DDR3_RDIMM_CTRL_0x290: .dword 0x0000000000000000
//_XXXXXXXXXXXXXXXX pm_axi0_fbck[ 63: 0](RD)
MC2_DDR3_RDIMM_CTRL_0x298: .dword 0x0000000000000000
//_XXXXXXXXXXXXXXXX pm_axi0_fbck[127:64](RD)
MC2_DDR3_RDIMM_CTRL_0x2a0: .dword 0x0000000000000000
//_XXXXXXXXXXXXXXXX pm_axi1_fbck[ 63: 0](RD)
MC2_DDR3_RDIMM_CTRL_0x2a8: .dword 0x0000000000000000
//_XXXXXXXXXXXXXXXX pm_axi1_fbck[127:64](RD)
MC2_DDR3_RDIMM_CTRL_0x2b0: .dword 0x0000000000000000
//_XXXXXXXXXXXXXXXX pm_axi2_fbck[ 63: 0](RD)
MC2_DDR3_RDIMM_CTRL_0x2b8: .dword 0x0000000000000000
//_XXXXXXXXXXXXXXXX pm_axi2_fbck[127:64](RD)
MC2_DDR3_RDIMM_CTRL_0x2c0: .dword 0x0000000000000000
//_XXXXXXXXXXXXXXXX pm_axi3_fbck[ 63: 0](RD)
MC2_DDR3_RDIMM_CTRL_0x2c8: .dword 0x0000000000000000
//_XXXXXXXXXXXXXXXX pm_axi3_fbck[127:64](RD)
MC2_DDR3_RDIMM_CTRL_0x2d0: .dword 0x0000000000000000
//_XXXXXXXXXXXXXXXX pm_axi4_fbck[ 63: 0](RD)
MC2_DDR3_RDIMM_CTRL_0x2d8: .dword 0x0000000000000000
//_XXXXXXXXXXXXXXXX pm_axi4_fbck[127:64](RD)
MC2_DDR3_RDIMM_CTRL_0x2e0: .dword 0x0000000000000000
//_XXXXXXXXXXXXXXXX pm_cmd_fbck0[ 63: 0](RD)
MC2_DDR3_RDIMM_CTRL_0x2e8: .dword 0x0000000000000000
//_XXXXXXXXXXXXXXXX pm_cmd_fbck0[127:64](RD)
MC2_DDR3_RDIMM_CTRL_0x2f0: .dword 0x0000000000000000
//_XXXXXXXXXXXXXXXX pm_cmd_fbck1[ 63: 0](RD)
MC2_DDR3_RDIMM_CTRL_0x2f8: .dword 0x0000000000000000
//_XXXXXXXXXXXXXXXX pm_cmd_fbck1[127:64](RD)
MC2_DDR3_RDIMM_CTRL_0x300: .dword 0x0000000000000000
//_XXXXXXXXXXXXXXXX pm_cmd_fbck2[ 63: 0](RD)
MC2_DDR3_RDIMM_CTRL_0x308: .dword 0x0000000000000000
//_XXXXXXXXXXXXXXXX pm_cmd_fbck2[127:64](RD)
MC2_DDR3_RDIMM_CTRL_0x310: .dword 0x0000000000000000
//_XXXXXXXXXXXXXXXX pm_cmd_fbck3[ 63: 0](RD)
MC2_DDR3_RDIMM_CTRL_0x318: .dword 0x0000000000000000
//_XXXXXXXXXXXXXXXX pm_cmd_fbck3[127:64](RD)
MC2_DDR3_RDIMM_CTRL_0x320: .dword 0x080830100000600a
//_XXXXXXXXXXXXXXXX 0000_0000 pm_REF_low
MC2_DDR3_RDIMM_CTRL_0x328: .dword 0x0000000000000000
//_XXXXXXXXXXXXXXXX (RD)
MC2_DDR3_RDIMM_CTRL_0x330: .dword 0x0000001000010400
//0000000_0 pm_stat_en 0_0000000 pm_rdbuffer_max(RD) 0000000_0 pm_retry 00_000000 pm_wr_pkg_num 0000000_0 pm_rwq_rb 0000000_0 pm_stb_en 000_00000 pm_addr_new 0000_0000 pm_tRDQidle
MC2_DDR3_RDIMM_CTRL_0x338: .dword 0x0000000000000000
//_XXXXXXXXXXXXXXXX 0000_0000 pm_fifo_depth 00000000_00000000_00000000_00000000 pm_retry_cnt(RD)
//MC2_DDR3_RDIMM_CTRL_0x340: .dword 0x02dc6c00000f0f01
MC2_DDR3_RDIMM_CTRL_0x340: .dword 0x0030d40000070f01
//00000000_00000000_00000000_00000000 pm_tREFretention 0000_0000 pm_ref_num 00000000 pm_tREF_IDLE 0000000_0 pm_ref_sch_en
MC2_DDR3_RDIMM_CTRL_0x348: .dword 0x0000000000000000
//_XXXXXXXXXXXXXXXX
MC2_DDR3_RDIMM_CTRL_0x350: .dword 0xffffffffffffffff
//_XXXXXXXXXXXXXXXX pm_lpbk_data_en
MC2_DDR3_RDIMM_CTRL_0x358: .dword 0x000000000001ffff
//0000000_0 pm_lpbk_ecc_mask_en 00000000 pm_lpbk_ecc_en 00000000 pm_lpbk_data_mask_en
MC2_DDR3_RDIMM_CTRL_0x360: .dword 0x0000000000000000
//00000000 pm_ecc_int_cnt_fatal 00000000 pm_ecc_int_cnt_error 00000000 pm_ecc_cnt_cs_3 00000000 pm_ecc_cnt_cs_2 00000000 pm_ecc_cnt_cs_1 00000000 pm_ecc_cnt_cs_0
MC2_DDR3_RDIMM_CTRL_0x368: .dword 0x0000000000000000
//_XXXXXXXXXXXXXXXX
MC2_DDR3_RDIMM_CTRL_0x370: .dword 0x0000000000000000
MC2_DDR3_RDIMM_CTRL_0x378: .dword 0x0000000000000001
MC2_DDR3_RDIMM_CTRL_0x380: .dword 0x0000000000000000
MC2_DDR3_RDIMM_CTRL_0x388: .dword 0x0000000000000000
MC2_DDR3_RDIMM_CTRL_0x390: .dword 0x0000000000000000
MC2_DDR3_RDIMM_CTRL_0x398: .dword 0x0000000000000000
n1_ddr3_RDIMM_reg_data_mc1:
MC3_DDR3_RDIMM_CTRL_0x000: .dword 0x0300000000000000
//XXXX pm_dll_value_0(RD) XXXX pm_dll_value_ck(RD) XXXX pm_dll_init_done(RD) XXXX pm_version(RD)
MC3_DDR3_RDIMM_CTRL_0x008: .dword 0x0000000000000000
//XXXX pm_dll_value_4(RD) XXXX pm_dll_value_3 (RD) XXXX pm_dll_value_2(RD) XXXX pm_dll_value_1(RD)
MC3_DDR3_RDIMM_CTRL_0x010: .dword 0x0000000000000000
//XXXX pm_dll_value_8(RD) XXXX pm_dll_value_7 (RD) XXXX pm_dll_value_6(RD) XXXX pm_dll_value_5(RD)
//MC3_DDR3_RDIMM_CTRL_0x018: .dword 0x5252525216100000
//MC3_DDR3_RDIMM_CTRL_0x018: .dword 0x4040404016100000
//MC3_DDR3_RDIMM_CTRL_0x018: .dword 0x3030303016100000
MC3_DDR3_RDIMM_CTRL_0x018: .dword 0x4b4b4b4b16100000
//MC3_DDR3_RDIMM_CTRL_0x018: .dword 0x2525252516100000
//_00000000 pm_dll_ck_3 _00000000 pm_dll_ck_2 _00000000 pm_dll_ck_1 _00000000 pm_dll_ck_0 _00000000 pm_dll_increment _00000000 pm_dll_start_point _0000000_0 pm_dll_bypass _0000000_0 pm_init_start
MC3_DDR3_RDIMM_CTRL_0x020: .dword 0x0201000201000000
//0000_0000 pm_dq_oe_end_0 0000_0000 pm_dq_oe_begin_0 000000_00 pm_dq_stop_edge_0 000000_00 pm_dq_start_edge_0 0000000_0 pm_rddata_delay_0 0000000_0 pm_rddqs_lt_half_0 0000000_0 pm_wrdqs_lt_half_0 0000000_0 pm_wrdq_lt_half_0
MC3_DDR3_RDIMM_CTRL_0x028: .dword 0x0303000002010100
//0000_0000 pm_rd_oe_end_0 0000_0000 pm_rd_oe_begin_0 000000_00 pm_rd_stop_edge_0 000000_00 pm_rd_start_edge_0 0000_0000 pm_dqs_oe_end_0 0000_0000 pm_dqs_oe_begin_0 000000_00 pm_dqs_stop_edge_0 000000_00 pm_dqs_start_edge_0
MC3_DDR3_RDIMM_CTRL_0x030: .dword 0x0000000003020202
//hXXXXXX (RD) 0000000_0 pm_wrdq_clkdelay_0 0000_0000 pm_odt_oe_end_0 0000_0000 pm_odt_oe_begin_0 000000_00 pm_odt_stop_edge_0 000000_00 pm_odt_start_edge_0
MC3_DDR3_RDIMM_CTRL_0x038: .dword 0x0000042020056500
//hXXXXXX (RD) _00000000 pm_dll_rddqs_n_0 _00000000 pm_dll_rddqs_p_0 _00000000 pm_dll_wrdqs_0 _00000000 pm_dll_wrdata_0 _00000000 pm_dll_gate_0
MC3_DDR3_RDIMM_CTRL_0x040: .dword 0x0201000201000000
//0000_0000 pm_dq_oe_end_1 0000_0000 pm_dq_oe_begin_1 000000_00 pm_dq_stop_edge_1 000000_00 pm_dq_start_edge_1 0000000_0 pm_rddata_delay_1 0000000_0 pm_rddqs_lt_half_1 0000000_0 pm_wrdqs_lt_half_1 0000000_0 pm_wrdq_lt_half_1
MC3_DDR3_RDIMM_CTRL_0x048: .dword 0x0303000002010100
//0000_0000 pm_rd_oe_end_1 0000_0000 pm_rd_oe_begin_1 000000_00 pm_rd_stop_edge_1 000000_00 pm_rd_start_edge_1 0000_0000 pm_dqs_oe_end_1 0000_0000 pm_dqs_oe_begin_1 000000_00 pm_dqs_stop_edge_1 000000_00 pm_dqs_start_edge_1
MC3_DDR3_RDIMM_CTRL_0x050: .dword 0x0000000003020202
//hXXXXXX (RD) 0000000_0 pm_wrdq_clkdelay_1 0000_0000 pm_odt_oe_end_1 0000_0000 pm_odt_oe_begin_1 000000_00 pm_odt_stop_edge_1 000000_00 pm_odt_start_edge_1
MC3_DDR3_RDIMM_CTRL_0x058: .dword 0x0000042020056500
//hXXXXXX (RD) _00000000 pm_dll_rddqs_n_1 _00000000 pm_dll_rddqs_p_1 _00000000 pm_dll_wrdqs_1 _00000000 pm_dll_wrdata_1 _00000000 pm_dll_gate_1
MC3_DDR3_RDIMM_CTRL_0x060: .dword 0x0201000201000000
//0000_0000 pm_dq_oe_end_2 0000_0000 pm_dq_oe_begin_2 000000_00 pm_dq_stop_edge_2 000000_00 pm_dq_start_edge_2 0000000_0 pm_rddata_delay_2 0000000_0 pm_rddqs_lt_half_2 0000000_0 pm_wrdqs_lt_half_2 0000000_0 pm_wrdq_lt_half_2
MC3_DDR3_RDIMM_CTRL_0x068: .dword 0x0303000002010100
//0000_0000 pm_rd_oe_end_2 0000_0000 pm_rd_oe_begin_2 000000_00 pm_rd_stop_edge_2 000000_00 pm_rd_start_edge_2 0000_0000 pm_dqs_oe_end_2 0000_0000 pm_dqs_oe_begin_2 000000_00 pm_dqs_stop_edge_2 000000_00 pm_dqs_start_edge_2
MC3_DDR3_RDIMM_CTRL_0x070: .dword 0x0000000003020202
//hXXXXXX (RD) 0000000_0 pm_wrdq_clkdelay_2 0000_0000 pm_odt_oe_end_2 0000_0000 pm_odt_oe_begin_2 000000_00 pm_odt_stop_edge_2 000000_00 pm_odt_start_edge_2
MC3_DDR3_RDIMM_CTRL_0x078: .dword 0x0000042020056500
//hXXXXXX (RD) _00000000 pm_dll_rddqs_n_2 _00000000 pm_dll_rddqs_p_2 _00000000 pm_dll_wrdqs_2 _00000000 pm_dll_wrdata_2 _00000000 pm_dll_gate_2
MC3_DDR3_RDIMM_CTRL_0x080: .dword 0x0201000201000000
//0000_0000 pm_dq_oe_end_3 0000_0000 pm_dq_oe_begin_3 000000_00 pm_dq_stop_edge_3 000000_00 pm_dq_start_edge_3 0000000_0 pm_rddata_delay_3 0000000_0 pm_rddqs_lt_half_3 0000000_0 pm_wrdqs_lt_half_3 0000000_0 pm_wrdq_lt_half_3
MC3_DDR3_RDIMM_CTRL_0x088: .dword 0x0303000002010100
//0000_0000 pm_rd_oe_end_3 0000_0000 pm_rd_oe_begin_3 000000_00 pm_rd_stop_edge_3 000000_00 pm_rd_start_edge_3 0000_0000 pm_dqs_oe_end_3 0000_0000 pm_dqs_oe_begin_3 000000_00 pm_dqs_stop_edge_3 000000_00 pm_dqs_start_edge_3
MC3_DDR3_RDIMM_CTRL_0x090: .dword 0x0000000003020202
//hXXXXXX (RD) 0000000_0 pm_wrdq_clkdelay_3 0000_0000 pm_odt_oe_end_3 0000_0000 pm_odt_oe_begin_3 000000_00 pm_odt_stop_edge_3 000000_00 pm_odt_start_edge_3
MC3_DDR3_RDIMM_CTRL_0x098: .dword 0x0000042020056500
//hXXXXXX (RD) _00000000 pm_dll_rddqs_n_3 _00000000 pm_dll_rddqs_p_3 _00000000 pm_dll_wrdqs_3 _00000000 pm_dll_wrdata_3 _00000000 pm_dll_gate_3
MC3_DDR3_RDIMM_CTRL_0x0a0: .dword 0x0201000201000000
//0000_0000 pm_dq_oe_end_4 0000_0000 pm_dq_oe_begin_4 000000_00 pm_dq_stop_edge_4 000000_00 pm_dq_start_edge_4 0000000_0 pm_rddata_delay_4 0000000_0 pm_rddqs_lt_half_4 0000000_0 pm_wrdqs_lt_half_4 0000000_0 pm_wrdq_lt_half_4
MC3_DDR3_RDIMM_CTRL_0x0a8: .dword 0x0303000002010100
//0000_0000 pm_rd_oe_end_4 0000_0000 pm_rd_oe_begin_4 000000_00 pm_rd_stop_edge_4 000000_00 pm_rd_start_edge_4 0000_0000 pm_dqs_oe_end_4 0000_0000 pm_dqs_oe_begin_4 000000_00 pm_dqs_stop_edge_4 000000_00 pm_dqs_start_edge_4
MC3_DDR3_RDIMM_CTRL_0x0b0: .dword 0x0000000003020202
//hXXXXXX (RD) 0000000_0 pm_wrdq_clkdelay_4 0000_0000 pm_odt_oe_end_4 0000_0000 pm_odt_oe_begin_4 000000_00 pm_odt_stop_edge_4 000000_00 pm_odt_start_edge_4
MC3_DDR3_RDIMM_CTRL_0x0b8: .dword 0x0000042020056500
//hXXXXXX (RD) _00000000 pm_dll_rddqs_n_4 _00000000 pm_dll_rddqs_p_4 _00000000 pm_dll_wrdqs_4 _00000000 pm_dll_wrdata_4 _00000000 pm_dll_gate_4
MC3_DDR3_RDIMM_CTRL_0x0c0: .dword 0x0201000201000000
//0000_0000 pm_dq_oe_end_5 0000_0000 pm_dq_oe_begin_5 000000_00 pm_dq_stop_edge_5 000000_00 pm_dq_start_edge_5 0000000_0 pm_rddata_delay_5 0000000_0 pm_rddqs_lt_half_5 0000000_0 pm_wrdqs_lt_half_5 0000000_0 pm_wrdq_lt_half_5
MC3_DDR3_RDIMM_CTRL_0x0c8: .dword 0x0303000002010100
//0000_0000 pm_rd_oe_end_5 0000_0000 pm_rd_oe_begin_5 000000_00 pm_rd_stop_edge_5 000000_00 pm_rd_start_edge_5 0000_0000 pm_dqs_oe_end_5 0000_0000 pm_dqs_oe_begin_5 000000_00 pm_dqs_stop_edge_5 000000_00 pm_dqs_start_edge_5
MC3_DDR3_RDIMM_CTRL_0x0d0: .dword 0x0000000003020202
//hXXXXXX (RD) 0000000_0 pm_wrdq_clkdelay_5 0000_0000 pm_odt_oe_end_5 0000_0000 pm_odt_oe_begin_5 000000_00 pm_odt_stop_edge_5 000000_00 pm_odt_start_edge_5
MC3_DDR3_RDIMM_CTRL_0x0d8: .dword 0x0000042020056500
//hXXXXXX (RD) _00000000 pm_dll_rddqs_n_5 _00000000 pm_dll_rddqs_p_5 _00000000 pm_dll_wrdqs_5 _00000000 pm_dll_wrdata_5 _00000000 pm_dll_gate_5
MC3_DDR3_RDIMM_CTRL_0x0e0: .dword 0x0201000201000000
//0000_0000 pm_dq_oe_end_6 0000_0000 pm_dq_oe_begin_6 000000_00 pm_dq_stop_edge_6 000000_00 pm_dq_start_edge_6 0000000_0 pm_rddata_delay_6 0000000_0 pm_rddqs_lt_half_6 0000000_0 pm_wrdqs_lt_half_6 0000000_0 pm_wrdq_lt_half_6
MC3_DDR3_RDIMM_CTRL_0x0e8: .dword 0x0303000002010100
//0000_0000 pm_rd_oe_end_6 0000_0000 pm_rd_oe_begin_6 000000_00 pm_rd_stop_edge_6 000000_00 pm_rd_start_edge_6 0000_0000 pm_dqs_oe_end_6 0000_0000 pm_dqs_oe_begin_6 000000_00 pm_dqs_stop_edge_6 000000_00 pm_dqs_start_edge_6
MC3_DDR3_RDIMM_CTRL_0x0f0: .dword 0x0000000003020202
//hXXXXXX (RD) 0000000_0 pm_wrdq_clkdelay_6 0000_0000 pm_odt_oe_end_6 0000_0000 pm_odt_oe_begin_6 000000_00 pm_odt_stop_edge_6 000000_00 pm_odt_start_edge_6
MC3_DDR3_RDIMM_CTRL_0x0f8: .dword 0x0000042020056500
//hXXXXXX (RD) _00000000 pm_dll_rddqs_n_6 _00000000 pm_dll_rddqs_p_6 _00000000 pm_dll_wrdqs_6 _00000000 pm_dll_wrdata_6 _00000000 pm_dll_gate_6
MC3_DDR3_RDIMM_CTRL_0x100: .dword 0x0201000201000000
//0000_0000 pm_dq_oe_end_7 0000_0000 pm_dq_oe_begin_7 000000_00 pm_dq_stop_edge_7 000000_00 pm_dq_start_edge_7 0000000_0 pm_rddata_delay_7 0000000_0 pm_rddqs_lt_half_7 0000000_0 pm_wrdqs_lt_half_7 0000000_0 pm_wrdq_lt_half_7
MC3_DDR3_RDIMM_CTRL_0x108: .dword 0x0303000002010100
//0000_0000 pm_rd_oe_end_7 0000_0000 pm_rd_oe_begin_7 000000_00 pm_rd_stop_edge_7 000000_00 pm_rd_start_edge_7 0000_0000 pm_dqs_oe_end_7 0000_0000 pm_dqs_oe_begin_7 000000_00 pm_dqs_stop_edge_7 000000_00 pm_dqs_start_edge_7
MC3_DDR3_RDIMM_CTRL_0x110: .dword 0x0000000003020202
//hXXXXXX (RD) 0000000_0 pm_wrdq_clkdelay_7 0000_0000 pm_odt_oe_end_7 0000_0000 pm_odt_oe_begin_7 000000_00 pm_odt_stop_edge_7 000000_00 pm_odt_start_edge_7
MC3_DDR3_RDIMM_CTRL_0x118: .dword 0x0000042020056500
//hXXXXXX (RD) _00000000 pm_dll_rddqs_n_7 _00000000 pm_dll_rddqs_p_7 _00000000 pm_dll_wrdqs_7 _00000000 pm_dll_wrdata_7 _00000000 pm_dll_gate_7
MC3_DDR3_RDIMM_CTRL_0x120: .dword 0x0201000201000000
//0000_0000 pm_dq_oe_end_8 0000_0000 pm_dq_oe_begin_8 000000_00 pm_dq_stop_edge_8 000000_00 pm_dq_start_edge_8 0000000_0 pm_rddata_delay_8 0000000_0 pm_rddqs_lt_half_8 0000000_0 pm_wrdqs_lt_half_8 0000000_0 pm_wrdq_lt_half_8
MC3_DDR3_RDIMM_CTRL_0x128: .dword 0x0303000002010100
//0000_0000 pm_rd_oe_end_8 0000_0000 pm_rd_oe_begin_8 000000_00 pm_rd_stop_edge_8 000000_00 pm_rd_start_edge_8 0000_0000 pm_dqs_oe_end_8 0000_0000 pm_dqs_oe_begin_8 000000_00 pm_dqs_stop_edge_8 000000_00 pm_dqs_start_edge_8
MC3_DDR3_RDIMM_CTRL_0x130: .dword 0x0000000003020202
//hXXXXXX (RD) 0000000_0 pm_wrdq_clkdelay_8 0000_0000 pm_odt_oe_end_8 0000_0000 pm_odt_oe_begin_8 000000_00 pm_odt_stop_edge_8 000000_00 pm_odt_start_edge_8
MC3_DDR3_RDIMM_CTRL_0x138: .dword 0x00000020207f6000
//hXXXXXX (RD) _00000000 pm_dll_rddqs_n_8 _00000000 pm_dll_rddqs_p_8 _00000000 pm_dll_wrdqs_8 _00000000 pm_dll_wrdata_8 _00000000 pm_dll_gate_8
MC3_DDR3_RDIMM_CTRL_0x140: .dword 0x0403000001ff01ff
//00000_000 pm_pad_ocd_clk 00000_000 pm_pad_ocd_ctl 0000000_0 pm_pad_ocd_dqs 0000000_0 pm_pad_ocd_dq 0000000_0_00000000 pm_pad_enzi 0000000_0 pm_pad_en_ctl _00000000 pm_pad_en_clk
MC3_DDR3_RDIMM_CTRL_0x148: .dword 0x0000000000010100
//_0000 pm_pad_adj_ncode_dq _0000 pm_pad_adj_pcode_dq 00000 _0 pm_pad_outodt_dq _0 pm_pad_slewrate_dq _0 pm_pad_code_dq _0000 pm_pad_adj_ncode_dq _0000 pm_pad_adj_pcode_dq 00000 _0 pm_pad_outodt_dq _0 pm_pad_slewrate_dq _0 00000000 0000000_0 pm_pad_vref_internal 0000000_0 pm_pad_odt_se 0000000_0 pm_pad_modezi1v8
MC3_DDR3_RDIMM_CTRL_0x150: .dword 0x00020000f0020000
//hXXXX _0000 pm_pad_adj_ncode_clk _0000 pm_pad_adj_pcode_clk 00000 _0 pm_pad_outodt_clk _0 pm_pad_slewrate_clk _0 pm_pad_code_clk _0000 pm_pad_adj_ncode_cmd _0000 pm_pad_adj_pcode_cmd 00000 _0 pm_pad_outodt_cmd _0 pm_pad_slewrate_cmd _0 pm_pad_code_cmd _0000 pm_pad_adj_ncode_addr _0000 pm_pad_adj_pcode_addr 00000 _0 pm_pad_outodt_addr _0 pm_pad_slewrate_addr _0 pm_pad_code_addr
MC3_DDR3_RDIMM_CTRL_0x158: .dword 0x00000000f0000000
//hXXXXXXXX (RD) _0000 pm_pad_comp_ncode_i _0000 pm_pad_comp_pcode_i 0000000_0 pm_pad_comp_mode 0000000_0 pm_pad_comp_tm 0000000_0 pm_pad_comp_pd
MC3_DDR3_RDIMM_CTRL_0x160: .dword 0x0000000000010101
//MC3_DDR3_RDIMM_CTRL_0x160: .dword 0x0000000000000001
//0000000_0_00000000 pm_rdfifo_empty(RD) 0000000_0_00000000 pm_overflow(RD) 0000_0000 pm_dram_init(RD) 0000000_0 pm_rdfifo_valid 000000_00 pm_cmd_timing 0000000_0 pm_ddr3_mode
MC3_DDR3_RDIMM_CTRL_0x168: .dword 0x140a000707030101
//hXX (RD) 0000_0000 pm_addr_mirror 000000_00 pm_cmd_delay _00000000 pm_burst_length 00000_000 pm_bank 0000_0000 pm_cs_zq 0000_0000 pm_cs_mrs 0000_0000 pm_cs_enable
//MC3_DDR3_RDIMM_CTRL_0x170: .dword 0x0000000001ff01ff
MC3_DDR3_RDIMM_CTRL_0x170: .dword 0x8421050084120501
//_00000000_00000000 pm_odt_wr_cs_map 0000_0000 pm_odt_wr_length 0000_0000 pm_odt_wr_delay _00000000_00000000 pm_odt_rd_cs_map 0000_0000 pm_odt_rd_length 0000_0000 pm_odt_rd_delay
MC3_DDR3_RDIMM_CTRL_0x178: .dword 0x0000000000000000
//hXXXXXXXXXXXXXXXX (RD)
MC3_DDR3_RDIMM_CTRL_0x180: .dword 0x0000000001100000
//_00000000 pm_lvl_resp_0(RD) 0000000_0 pm_lvl_done(RD) 0000000_0 pm_lvl_ready(RD) 00000000 0000_0000 pm_lvl_cs _00000000 pm_tLVL_DELAY 0000000_0 pm_leveling_req(WR) 000000_00 pm_leveling_mode
MC3_DDR3_RDIMM_CTRL_0x188: .dword 0x0000000000000000
//_00000000 pm_lvl_resp_8(RD) _00000000 pm_lvl_resp_7(RD) _00000000 _pm_lvl_resp_6(RD) _00000000 pm_lvl_resp_5(RD) _00000000 pm_lvl_resp_4(RD) _00000000 pm_lvl_resp_3(RD) _00000000 pm_lvl_resp_2(RD) _00000000 pm_lvl_resp_1(RD)
//CMD CONFIG
MC3_DDR3_RDIMM_CTRL_0x190: .dword 0x0000000000000000
//_00000000_00000000 pm_cmd_a 00000_000 pm_cmd_ba 00000_000 pm_cmd_cmd 0000_0000 pm_cmd_cs 0000000_0 pm_status_cmd(RD) 0000000_0 pm_cmd_req(WR) 0000000_0 pm_command
MC3_DDR3_RDIMM_CTRL_0x198: .dword 0x0000000000000000
//00000000 00000000 0000_0000 pm_status_sref(RD) 0000_0000 pm_srefresh_req 0000000_0 pm_pre_all_done(RD) 0000000_0 pm_pre_all_req(WR) 0000000_0 pm_mrs_done(RD) 0000000_0 pm_mrs_req(WR)
MC3_DDR3_RDIMM_CTRL_0x1a0: .dword 0x0000001000060d40
//_00000000_00000000 pm_mr_3_cs_0 _00000000_00000000 pm_mr_2_cs_0 _00000000_00000000 pm_mr_1_cs_0 _00000000_00000000 pm_mr_0_cs_0
MC3_DDR3_RDIMM_CTRL_0x1a8: .dword 0x0000001000060d40
//_00000000_00000000 pm_mr_3_cs_1 _00000000_00000000 pm_mr_2_cs_1 _00000000_00000000 pm_mr_1_cs_1 _00000000_00000000 pm_mr_0_cs_1
MC3_DDR3_RDIMM_CTRL_0x1b0: .dword 0x0000001000060d40
//_00000000_00000000 pm_mr_3_cs_2 _00000000_00000000 pm_mr_2_cs_2 _00000000_00000000 pm_mr_1_cs_2 _00000000_00000000 pm_mr_0_cs_2
MC3_DDR3_RDIMM_CTRL_0x1b8: .dword 0x0000001000060d40
//_00000000_00000000 pm_mr_3_cs_3 _00000000_00000000 pm_mr_2_cs_3 _00000000_00000000 pm_mr_1_cs_3 _00000000_00000000 pm_mr_0_cs_3
MC3_DDR3_RDIMM_CTRL_0x1c0: .dword 0x3030c80c03042006
//_00000000 pm_tRESET _00000000 pm_tCKE _00000000 pm_tXPR _00000000 pm_tMOD _00000000 pm_tZQCL _00000000 pm_tZQ_CMD _00000000 pm_tWLDQSEN 000_00000 pm_tRDDATA
//MC3_DDR3_RDIMM_CTRL_0x1c8: .dword 0x11040b0b15904080
MC3_DDR3_RDIMM_CTRL_0x1c8: .dword 0x11040b0b22c34080
//00_000000 pm_tFAW 0000_0000 pm_tRRD 0000_0000 pm_tRCD _00000000 pm_tRP _00000000 pm_tREF _00000000 pm_tRFC _00000000 pm_tZQCS _00000000 pm_tZQperiod
MC3_DDR3_RDIMM_CTRL_0x1d0: .dword 0x0a020d0502000018
//0000_0000 pm_tODTL _00000000 pm_tXSRD 0000_0000 pm_tPHY_RDLAT 000_00000 pm_tPHY_WRLAT 000000_00_00000000_00000000 pm_tRAS_max 00_000000 pm_tRAS_min
MC3_DDR3_RDIMM_CTRL_0x1d8: .dword 0x14050c0408070405
//_00000000 pm_tXPDLL _00000000 pm_tXP 000_00000 pm_tWR 0000_0000 pm_tRTP 0000_0000 pm_tRL 0000_0000 pm_tWL 0000_0000 pm_tCCD 0000_0000 pm_tWTR
MC3_DDR3_RDIMM_CTRL_0x1e0: .dword 0x0503000000000000
//00_000000 pm_tW2R_diffcs_dly 00_000000 pm_tW2W_diffcs_adj_dly 00_000000 pm_tR2P_sameba_adj_dly 00_000000 pm_tW2P_sameba_adj_dly 00_000000 pm_tR2R_sameba_adj_dly 00_000000 pm_tR2W_sameba_adj_dly 00_000000 pm_tW2R_sameba_adj_dly 00_000000 pm_tW2W_sameba_adj_dly
MC3_DDR3_RDIMM_CTRL_0x1e8: .dword 0x030a000000010000
//00_000000 pm_tR2R_diffcs_adj_dly 00_000000 pm_tR2W_diffcs_dly 00_000000 pm_tR2P_samecs_dly 00_000000 pm_tW2P_samecs_dly 00_000000 pm_tR2R_samecs_adj_dly 00_000000 pm_tR2W_samecs_adj_dly 00_000000 pm_tW2R_samecs_adj_dly 00_000000 pm_tW2W_samecs_adj_dly
MC3_DDR3_RDIMM_CTRL_0x1f0: .dword 0x000801e4ff000101
//0000_0000 pm_power_up _00000000 pm_age_step _00000000 pm_tCPDED _00000000 pm_cs_map _00000000 pm_bs_config 00000_000 pm_channel_32 pm_channel_16 pm_nc 0000_0000 pm_pr_r2w 0000000_0 pm_placement_en
MC3_DDR3_RDIMM_CTRL_0x1f8: .dword 0x0000000004081001
//0000_0000 pm_hardware_pd_3 0000_0000 pm_hardware_pd_2 0000_0000 pm_hardware_pd_1 0000_0000 pm_hardware_pd_0 00_000000 pm_credit_16 00_000000 pm_credit_32 00_000000 pm_credit_64 0000000_0 pm_selection_en
MC3_DDR3_RDIMM_CTRL_0x200: .dword 0x0c000c000c000c00
//0000_0000_00000000 pm_cmdq_age_16 0000_0000_00000000 pm_cmdq_age_32 0000_0000_00000000 pm_cmdq_age_64 _00000000 pm_tCKESR _00000000 pm_tRDPDEN
MC3_DDR3_RDIMM_CTRL_0x208: .dword 0x0c000c0000000000
//0000_0000_00000000 pm_wrfifo_age 0000_0000_00000000 pm_rdfifo_age 0000_0000 pm_power_status_3 0000_0000 pm_power_status_2 0000_0000 pm_power_status_1 0000_0000 pm_power_status_0
MC3_DDR3_RDIMM_CTRL_0x210: .dword 0x0008010f00030006
//_00000000_00000000 pm_active_age 0000000_0 pm_cs_place_0 0000_0000 pm_addr_win_0 000000_00 pm_cs_diff_0 00000_000 pm_row_diff_0 000000_00 pm_ba_diff_0 00000_000 pm_col_diff_0
MC3_DDR3_RDIMM_CTRL_0x218: .dword 0x0008000b00030106
//_00000000_00000000 pm_fastpd_age 0000000_0 pm_cs_place_1 0000_0000 pm_addr_win_1 000000_00 pm_cs_diff_1 00000_000 pm_row_diff_1 000000_00 pm_ba_diff_1 00000_000 pm_col_diff_1
MC3_DDR3_RDIMM_CTRL_0x220: .dword 0x0008000b00030106
//_00000000_00000000 pm_slowpd_age 0000000_0 pm_cs_place_2 0000_0000 pm_addr_win_2 000000_00 pm_cs_diff_2 00000_000 pm_row_diff_2 000000_00 pm_ba_diff_2 00000_000 pm_col_diff_2
MC3_DDR3_RDIMM_CTRL_0x228: .dword 0x0008000b00030106
//_00000000_00000000 pm_selfref_age 0000000_0 pm_cs_place_3 0000_0000 pm_addr_win_3 000000_00 pm_cs_diff_3 00000_000 pm_row_diff_3 000000_00 pm_ba_diff_3 00000_000 pm_col_diff_3
MC3_DDR3_RDIMM_CTRL_0x230: .dword 0x0fff000000000000
//0000_0000_00000000_00000000_00000000 pm_addr_mask_0 0000_0000_00000000_00000000_00000000 pm_addr_base_0
MC3_DDR3_RDIMM_CTRL_0x238: .dword 0x0ffffe000000ff00
//0000_0000_00000000_00000000_00000000 pm_addr_mask_1 0000_0000_00000000_00000000_00000000 pm_addr_base_1
MC3_DDR3_RDIMM_CTRL_0x240: .dword 0x0ffffe000000ff00
//0000_0000_00000000_00000000_00000000 pm_addr_mask_2 0000_0000_00000000_00000000_00000000 pm_addr_base_2
MC3_DDR3_RDIMM_CTRL_0x248: .dword 0x0ffffe000000ff00
//0000_0000_00000000_00000000_00000000 pm_addr_mask_3 0000_0000_00000000_00000000_00000000 pm_addr_base_3
MC3_DDR3_RDIMM_CTRL_0x250: .dword 0x0000000000000000
//00000000 _00_00_00_00 pm_cmd_monitor_3_2_1_0 000000_00_00000000 pm_axi_monitor _00000000 pm_ecc_code(RD) 0000_0_000 pm_int_trigger pm_ecc_enable 000000_00 pm_int_vector 000000_00 pm_int_enable
MC3_DDR3_RDIMM_CTRL_0x258: .dword 0x0000000000000000
//XXXXXXXXXXXXXXXX (RD)
MC3_DDR3_RDIMM_CTRL_0x260: .dword 0x0000000000000000
//_XXXXXXXXXXXXXXXX pm_ecc_addr(RD)
MC3_DDR3_RDIMM_CTRL_0x268: .dword 0x0000000000000000
//_XXXXXXXXXXXXXXXX pm_ecc_data(RD)
MC3_DDR3_RDIMM_CTRL_0x270: .dword 0x0000001000000000
//000000_00 pm_lpbk_ecc_mask(RD) 0_0000000_00000000_00000000 pm_prbs_init 0000000_0 pm_lpbk_error(RD) 0000000_0 pm_prbs_23 0000000_0 pm_lpbk_start 0000000_0 pm_lpbk_en
MC3_DDR3_RDIMM_CTRL_0x278: .dword 0x0000000000000000
//_00000000_00000000 pm_lpbk_ecc(RD) _00000000_00000000 pm_lpbk_data_mask(RD) _00000000_00000000 pm_lpbk_correct(RD) _00000000_00000000 pm_lpbk_counter(RD)
MC3_DDR3_RDIMM_CTRL_0x280: .dword 0x0000000000000000
//_XXXXXXXXXXXXXXXX pm_lpbk_data[ 63: 0](RD)
MC3_DDR3_RDIMM_CTRL_0x288: .dword 0x0000000000000000
//_XXXXXXXXXXXXXXXX pm_lpbk_data[127:64](RD)
//Monitor fbck
MC3_DDR3_RDIMM_CTRL_0x290: .dword 0x0000000000000000
//_XXXXXXXXXXXXXXXX pm_axi0_fbck[ 63: 0](RD)
MC3_DDR3_RDIMM_CTRL_0x298: .dword 0x0000000000000000
//_XXXXXXXXXXXXXXXX pm_axi0_fbck[127:64](RD)
MC3_DDR3_RDIMM_CTRL_0x2a0: .dword 0x0000000000000000
//_XXXXXXXXXXXXXXXX pm_axi1_fbck[ 63: 0](RD)
MC3_DDR3_RDIMM_CTRL_0x2a8: .dword 0x0000000000000000
//_XXXXXXXXXXXXXXXX pm_axi1_fbck[127:64](RD)
MC3_DDR3_RDIMM_CTRL_0x2b0: .dword 0x0000000000000000
//_XXXXXXXXXXXXXXXX pm_axi2_fbck[ 63: 0](RD)
MC3_DDR3_RDIMM_CTRL_0x2b8: .dword 0x0000000000000000
//_XXXXXXXXXXXXXXXX pm_axi2_fbck[127:64](RD)
MC3_DDR3_RDIMM_CTRL_0x2c0: .dword 0x0000000000000000
//_XXXXXXXXXXXXXXXX pm_axi3_fbck[ 63: 0](RD)
MC3_DDR3_RDIMM_CTRL_0x2c8: .dword 0x0000000000000000
//_XXXXXXXXXXXXXXXX pm_axi3_fbck[127:64](RD)
MC3_DDR3_RDIMM_CTRL_0x2d0: .dword 0x0000000000000000
//_XXXXXXXXXXXXXXXX pm_axi4_fbck[ 63: 0](RD)
MC3_DDR3_RDIMM_CTRL_0x2d8: .dword 0x0000000000000000
//_XXXXXXXXXXXXXXXX pm_axi4_fbck[127:64](RD)
MC3_DDR3_RDIMM_CTRL_0x2e0: .dword 0x0000000000000000
//_XXXXXXXXXXXXXXXX pm_cmd_fbck0[ 63: 0](RD)
MC3_DDR3_RDIMM_CTRL_0x2e8: .dword 0x0000000000000000
//_XXXXXXXXXXXXXXXX pm_cmd_fbck0[127:64](RD)
MC3_DDR3_RDIMM_CTRL_0x2f0: .dword 0x0000000000000000
//_XXXXXXXXXXXXXXXX pm_cmd_fbck1[ 63: 0](RD)
MC3_DDR3_RDIMM_CTRL_0x2f8: .dword 0x0000000000000000
//_XXXXXXXXXXXXXXXX pm_cmd_fbck1[127:64](RD)
MC3_DDR3_RDIMM_CTRL_0x300: .dword 0x0000000000000000
//_XXXXXXXXXXXXXXXX pm_cmd_fbck2[ 63: 0](RD)
MC3_DDR3_RDIMM_CTRL_0x308: .dword 0x0000000000000000
//_XXXXXXXXXXXXXXXX pm_cmd_fbck2[127:64](RD)
MC3_DDR3_RDIMM_CTRL_0x310: .dword 0x0000000000000000
//_XXXXXXXXXXXXXXXX pm_cmd_fbck3[ 63: 0](RD)
MC3_DDR3_RDIMM_CTRL_0x318: .dword 0x0000000000000000
//_XXXXXXXXXXXXXXXX pm_cmd_fbck3[127:64](RD)
MC3_DDR3_RDIMM_CTRL_0x320: .dword 0x080830100000600a
//_XXXXXXXXXXXXXXXX 0000_0000 pm_REF_low
MC3_DDR3_RDIMM_CTRL_0x328: .dword 0x0000000000000000
//_XXXXXXXXXXXXXXXX (RD)
MC3_DDR3_RDIMM_CTRL_0x330: .dword 0x0000001000010400
//0000000_0 pm_stat_en 0_0000000 pm_rdbuffer_max(RD) 0000000_0 pm_retry 00_000000 pm_wr_pkg_num 0000000_0 pm_rwq_rb 0000000_0 pm_stb_en 000_00000 pm_addr_new 0000_0000 pm_tRDQidle
MC3_DDR3_RDIMM_CTRL_0x338: .dword 0x0000000000000000
//_XXXXXXXXXXXXXXXX 0000_0000 pm_fifo_depth 00000000_00000000_00000000_00000000 pm_retry_cnt(RD)
//MC3_DDR3_RDIMM_CTRL_0x340: .dword 0x02dc6c00000f0f01
MC3_DDR3_RDIMM_CTRL_0x340: .dword 0x0030d40000070f01
//00000000_00000000_00000000_00000000 pm_tREFretention 0000_0000 pm_ref_num 00000000 pm_tREF_IDLE 0000000_0 pm_ref_sch_en
MC3_DDR3_RDIMM_CTRL_0x348: .dword 0x0000000000000000
//_XXXXXXXXXXXXXXXX
MC3_DDR3_RDIMM_CTRL_0x350: .dword 0xffffffffffffffff
//_XXXXXXXXXXXXXXXX pm_lpbk_data_en
MC3_DDR3_RDIMM_CTRL_0x358: .dword 0x000000000001ffff
//0000000_0 pm_lpbk_ecc_mask_en 00000000 pm_lpbk_ecc_en 00000000 pm_lpbk_data_mask_en
MC3_DDR3_RDIMM_CTRL_0x360: .dword 0x0000000000000000
//00000000 pm_ecc_int_cnt_fatal 00000000 pm_ecc_int_cnt_error 00000000 pm_ecc_cnt_cs_3 00000000 pm_ecc_cnt_cs_2 00000000 pm_ecc_cnt_cs_1 00000000 pm_ecc_cnt_cs_0
MC3_DDR3_RDIMM_CTRL_0x368: .dword 0x0000000000000000
//_XXXXXXXXXXXXXXXX
MC3_DDR3_RDIMM_CTRL_0x370: .dword 0x0000000000000000
MC3_DDR3_RDIMM_CTRL_0x378: .dword 0x0000000000000001
MC3_DDR3_RDIMM_CTRL_0x380: .dword 0x0000000000000000
MC3_DDR3_RDIMM_CTRL_0x388: .dword 0x0000000000000000
MC3_DDR3_RDIMM_CTRL_0x390: .dword 0x0000000000000000
MC3_DDR3_RDIMM_CTRL_0x398: .dword 0x0000000000000000

6
Targets/Bonito3a3000_7a/Bonito/start.S
View File

@ -671,7 +671,9 @@ no_reboot:
//#define DISABLE_DDR_A15
//#define DEBUG_DDR
//#define DEBUG_DDR_PARAM
//#define DLL_DELAY_LOOP
//#define PRINT_DDR_LEVELING
//#define DLL_CK_DELAY_DEBUG
TTYDBG("\r\nStart Init Memory, wait a while......\r\n")
####################################
@ -1558,7 +1560,7 @@ idle1000:
#include "ddr_dir/ls7A_gmem_config.S"
#endif
#ifdef DDR3_DIMM
#include "loongson3C_ddr3_leveling.S"
#include "../../../pmon/arch/mips/mm/loongson3C_ddr3_leveling.S"
#endif
#ifdef ARB_LEVEL
#include "ddr_dir/ARB_level_new.S"

49
pmon/arch/mips/mm/ddr_leveling_define.h
View File

@ -1,5 +1,46 @@
//PCB DQ swap info, default no swap
#define WLVL_RESP_MAP 0x000000000
//(1+8)slice:ECC_B7_B6_B5_B4_B3_B2_B1_B0, each byte takes 4 bits(1 hex number)
//value = MC DQ offset that connected to DRAM DQ0 of each Byte
//for example, if PCB connect DRAM side DQ0 to CPU side DQ3, DRAM side DQ16 to CPU side DQ17,
//and others keep one to one, than you need modify this macro to 0x0_0000_0103
#define GET_LVL_BYTE_t2 \
dsubu a1, t2, t8; \
dsubu a1, a1, 0x180;
#define GET_WLVL_RESP_a0 \
dsll a1, a1, 2; \
dli a2, WLVL_RESP_MAP; \
dsrl a2, a2, a1; \
and a2, a2, 0x7; \
dsrl a0, a0, a2; \
and a0, a0, 0x1;
#define GET_GLVL_RESP_a0 \
and a0, a0, 0x1;
#define GET_GLVL_RESP_2BIT_a0 \
and a0, a0, 0x3;
#define GET_NUMBER_OF_SLICES \
li t0, 0x8;\
lb a0, 0x1f2(t8);\
beq a0, 0x3, 934f;\
nop;\
beq a0, 0x7, 935f;\
nop;\
b 936f;\
nop;\
934:;\
li t0, 0x2;\
b 936f;\
nop;\
935:;\
li t0, 0x4;\
b 936f;\
nop;\
936:;\
dli t1, 0x250;\
or t1, t1, t8;\
lb a0, 0x2(t1);\
@ -10,11 +51,13 @@
daddu t0, t0, 0x1;\
933:;
// GET_NODE_ID_a0;\
// dli t5, 0x90000e0040000000;\
// or t5, t5, a0;\
//
#define PRINT_THE_MC_PARAM \
dli t4, DDR_PARAM_NUM;\
GET_NODE_ID_a0;\
dli t5, 0x900000000ff00000;\
or t5, t5, a0;\
move t5, t8; \
1:;\
ld t6, 0x0(t5);\
move a0, t5;\

266
pmon/arch/mips/mm/loongson3C_ddr3_leveling.S
View File

@ -23,13 +23,16 @@
//#define SIGNAL_DEPICT_DEBUG
//#define LVL_DEBUG
#define CHANGE_DQ_WITH_DQS
#define NO_EDGE_CHECK
#define WLVL_CHKBIT 0x1
#define ORDER_OF_UDIMM 0x876543210
#define ORDER_OF_RDIMM 0x765401238
//#define ORDER_OF_UDIMM 0x847652013 //for SODIMM (2 cs and 8 chips per cs)
#define WRDQS_LTHF_STD 0x40
#define WRDQ_LTHF_STD 0x40 //less then STD1 and less then STD2 will be set1
#define RDDQS_LTHF_STD1 0x40 //greater then STD1 and less then STD2 will be set1
#define RDDQS_LTHF_STD2 0x0
#define WRDQ_LTHF_STD 0x40 //less then STD will be set1
#define RDDQS_LTHF_STD1 0x3a //greater then STD1 and less then STD2 will be set1
#define RDDQS_LTHF_STD2 0x10
#define DLL_WRDQ_SUB 0x20
#define DLL_GATE_SUB 0x20
#define WR_FILTER_LENGTH 0x6
@ -37,7 +40,7 @@
#define PREAMBLE_LENGTH_3A9 0x60
#define PREAMBLE_LENGTH_3A8 0x60
#define MDL_CNT 0x500
#define GCL_CNT 9
#define GCL_CNT 10
#define OFFSET_DLL_WRDQ 0x19 // from 0x20/40/....
#define OFFSET_DLL_WRDQS 0x1a
@ -94,17 +97,7 @@ ddr3_leveling:
/* identify wheather there is ecc slice */
li t0, 0x8
dli t1, 0x250
or t1, t1, t8
lb a0, 0x2(t1)
dli t1, 0x1
and a0, a0, t1
bne a0, t1, 1f //when rd_after_write enabled, the 9th device may don't need leveling
nop
daddu t0, t0, 0x1
1:
GET_NUMBER_OF_SLICES
dli t1, 0x28
or t1, t1, t8
@ -250,8 +243,8 @@ lvl_done_sampling0:
lvl_resp_set0:
lb a0, 0x7(t2)
dli t4, 0x1
and a0, a0, t4
GET_LVL_BYTE_t2
GET_WLVL_RESP_a0
beqz a0, resp_set0_done
nop
@ -315,6 +308,58 @@ resp_set0_done:
bnez t0, lvl_req_set0
nop
#if 1
//filter 0to1 giltch
GET_NUMBER_OF_SLICES
dli t1, 0x20
or t1, t1, t8
dli t2, 0x180
or t2, t2, t8
dll_wrdqs_add:
lb a0, OFFSET_DLL_WRDQS(t1)
daddu a0, a0, 0x10
dli t4, 0x7f
and a0, a0, t4
sb a0, OFFSET_DLL_WRDQS(t1)
#ifdef CHANGE_DQ_WITH_DQS
lb a0, OFFSET_DLL_WRDQS(t1) // get dll_wrdqs
blt a0, WRDQS_LTHF_STD, 1f
nop
li t4, 0x0
sb t4, OFFSET_WRDQS_LTHF(t1) //set wrdqs_lt_half
b 2f
nop
1:
li t4, 0x1
sb t4, OFFSET_WRDQS_LTHF(t1) //set wrdqs_lt_half
2:
dsubu a0, a0, 0x20
dli t4, 0x7f
and a0, a0, t4
sb a0, OFFSET_DLL_WRDQ(t1) // set dll_wrdata
blt a0, WRDQ_LTHF_STD, 1f
nop
li t4, 0x0
sb t4, OFFSET_WRDQ_LTHF(t1) //set wrdq_lt_half
b 2f
nop
1:
li t4, 0x1
sb t4, OFFSET_WRDQ_LTHF(t1) //set wrdq_lt_half
2:
#endif
daddu t1, t1, 0x20
dsubu t0, t0, 0x1
bnez t0, dll_wrdqs_add
nop
#endif
/* 0 to 1 */
GET_NUMBER_OF_SLICES
dli t1, 0x20
@ -343,8 +388,8 @@ lvl_done_sampling1:
lvl_resp_set1:
lb a0, 0x7(t2)
dli t4, 0x1
and a0, a0, t4
GET_LVL_BYTE_t2
GET_WLVL_RESP_a0
bnez a0, resp_set1_done
nop
@ -558,16 +603,9 @@ wrdq_lt_half_test:
GET_DIMM_TYPE
bnez a1, rdimm_wrdq_lt_half_test
nop
li t0, 0x7 //only loop 7 times
dli t1, 0x250
or t1, t1, t8
lb a0, 0x2(t1)
dli t1, 0x1
and a0, a0, t1
bne a0, t1, 1f //when rd_after_write enabled, the 9th device may don't need leveling
nop
daddu t0, t0, 0x1
1:
GET_NUMBER_OF_SLICES
dsubu t0, t0, 0x1 // onlt loop 7 times
dli t2, 0x0
wrdq_lt_half_test_loop:
dli a0, ORDER_OF_UDIMM
@ -1232,6 +1270,7 @@ glvl_ready_sampling:
#ifdef SIGNAL_DEPICT_DEBUG
PRINTSTR("\r\nthe signal depict begin:\r\n")
GET_NUMBER_OF_SLICES
dli t1, 0x28 // save the init para before signal depict
or t1, t1, t8
lb a0, 0x7(t1)
@ -1249,7 +1288,6 @@ glvl_ready_sampling:
or t1, t1, t8
dli t5, 0x180
or t5, t5, t8
dli t0, 0x8
dli t2, 0x0
dli s6, 0x0
dli s7, 0x0
@ -1286,8 +1324,7 @@ t_glvl_req_set:
nop
lb a0, 0x7(t5)
dli t4, 0x1
and a0, a0, t4
GET_GLVL_RESP_a0
move a1, a0
#if 1
dli t4, 0x180
@ -1305,8 +1342,7 @@ t_glvl_req_set:
nop
lb a0, 0x7(t5)
dli t4, 0x1
and a0, a0, t4
GET_GLVL_RESP_a0
or a0, a0, a1
move a1, a0
#endif
@ -1326,8 +1362,7 @@ t_glvl_req_set:
nop
lb a0, 0x7(t5)
dli t4, 0x1
and a0, a0, t4
GET_GLVL_RESP_a0
or a0, a0, a1
#endif
@ -1419,6 +1454,8 @@ reset_rd_oe:
or t1, t1, t8
dli t2, 0x180
or t2, t2, t8
dli t6, 0x0
glvl_req_set0:
dli a0, 0x1
sb a0, 0x181(t8)
@ -1430,11 +1467,9 @@ glvl_done_sampling0:
beqz a0, glvl_done_sampling0
nop
dli t6, 0x0
glvl_resp_set0:
lb a0, 0x7(t2)
dli t4, 0x3
and a0, a0, t4
GET_GLVL_RESP_2BIT_a0
beqz a0, glvl_resp_set0_done
nop
@ -1444,12 +1479,12 @@ dll_gate_add0:
dli t4, 0x7f
and a0, a0, t4
#ifdef DDR_DLL_BYPASS
lb t2, 0x4(t8)
daddu t2, t2, 0x2
lb t4, 0x4(t8)
daddu t4, t4, 0x2
1:
blt a0, t2, 2f
blt a0, t4, 2f
nop
dsubu a0, a0, t2
dsubu a0, a0, t4
b 1b
nop
2:
@ -1539,8 +1574,7 @@ glvl_done_sampling1:
glvl_resp_set1:
lb a0, 0x7(t2)
dli t4, 0x3
and a0, a0, t4
GET_GLVL_RESP_2BIT_a0
bnez a0, glvl_resp_set1_done
nop
dli s7, GATE_FILTER_LENGTH
@ -1663,16 +1697,8 @@ glvl_resp_set1_done:
#ifdef PREAMBLE_CHECK_DEBUG
dli s7, 0x8
dli t1, 0x250
or t1, t1, t8
lb a0, 0x2(t1)
dli t1, 0x1
and a0, a0, t1
bne a0, t1, 1f //when rd_after_write enabled, the 9th device may don't need leveling
nop
daddu s7, s7, 0x1
1:
GET_NUMBER_OF_SLICES
move s7, t0
// dli s7, 0x5
dli t1, 0x28
or t1, t1, t8
@ -1684,6 +1710,7 @@ preamble_check_init:
/* check the preamble exist */
PRINTSTR("\r\nPREAMBLE CHECK!!\r\n")
// set the gate signal 0.75 period before
dli a1, 0x0
dli s6, PREAMBLE_LENGTH_3A9 //s6 represents 0.75 period to be checked
dli a3, 0x80
dli t4, 0x0
@ -1788,9 +1815,7 @@ glvl_check_preamble:
1:
lb a0, 0x7(t2)
dli t4, 0x3
and a0, a0, t4
GET_GLVL_RESP_2BIT_a0
bnez a0, test_continuous5_0
nop
#ifdef LVL_DEBUG
@ -1844,10 +1869,11 @@ test_continuous5_0:
nop
1:
#ifdef PRINT_PREAMBLE_CHECK
PRINTSTR("The 1 found in preamble test@")
PRINTSTR("The 1 found in preamble test at position")
move a0, s6
bal hexserial
nop
PRINTSTR("\r\ncontinued 1 is found")
move a0, t6
bal hexserial
nop
@ -1889,11 +1915,11 @@ test_continuous5_0:
nop
glvl_check_preamble_fail:
PRINTSTR("\r\nThe preamble check failed @")
PRINTSTR("\r\nThe preamble check not found @")
move a0, s6
bal hexserial
nop
PRINTSTR("\r\n")
PRINTSTR("training again ... \r\n")
dli s6, 0x0
lb a0, 0x6(t1)
@ -1911,6 +1937,9 @@ glvl_check_preamble_fail:
dli t3, 0x0
glvl_redo_req_set_0:
bgt a1, MDL_CNT, leveling_failed
nop
daddu a1, a1, 0x1
dli t4, 0x180
or t4, t4, t8
dli a0, 0x1
@ -1963,8 +1992,7 @@ glvl_redo_req_set_0:
nop
#endif
lb a0, 0x7(t2)
dli t4, 0x3
and a0, a0, t4
GET_GLVL_RESP_2BIT_a0
beq a0, 0x0, glvl_redo_set0_end
nop
#ifdef LVL_DEBUG
@ -2023,8 +2051,7 @@ glvl_redo_resp_set1_0:
PRINTSTR("\r\nglvl redo resp set 1\r\n")
#endif
lb a0, 0x7(t2)
dli t4, 0x3
and a0, a0, t4
GET_GLVL_RESP_2BIT_a0
bnez a0, preamble_check_init
nop
@ -2078,7 +2105,7 @@ glvl_redo_resp_set1_0:
glvl_check_preamble_end:
#ifdef PRINT_PREAMBLE_CHECK //print registers
#if 0 //PRINT_PREAMBLE_CHECK //print registers
PRINTSTR("\r\nThe MC param after preamble check is:\r\n")
PRINT_THE_MC_PARAM
#endif
@ -2339,6 +2366,7 @@ gate_sub_end:
#ifdef NO_EDGE_CHECK
#else
#if 1
/* unknown reason to reset init_start */
dli t1, 0x18
@ -2366,7 +2394,11 @@ gate_sub_end:
nop
#endif
dli t0, 0x0
rd_oe_sub:
bgt t0, GCL_CNT, leveling_failed
nop
daddu t0, t0, 0x1
get_burst_length_half: //save in t9
dli t1, 0x168
@ -2819,14 +2851,14 @@ rd_oe_6_sub:
ld a0, 0x0(t1)
dli t2, 0x0101000000000000
dsubu a0, a0, t2
//sd a0, 0x0(t1)
sd a0, 0x0(t1)
dli t1, 0x0f0
or t1, t1, t8
ld a0, 0x0(t1)
dli t2, 0x0000000001010000
dsubu a0, a0, t2
//sd a0, 0x0(t1)
sd a0, 0x0(t1)
b glvl_resp_check_7
dli s7, 0x1
@ -2874,6 +2906,84 @@ rd_oe_8_sub:
#endif
gate_leveling_exit:
#if 1 //set odt
GET_NUMBER_OF_SLICES
dli t1, 0x0
or t1, t1, t8
odt_start_set:
daddu t1, t1, 0x20
lb a0, 0xe(t1)
bnez a0, 1f
nop
li a0, 0x0
sb a0, 0x12(t1)
sb a0, 0x10(t1)
b odt_end_set
nop
1:
lb a0, 0xc(t1)
bgeu a0, 0x2, 2f
nop
daddu a0, a0, 0x2
sb a0, 0x10(t1)
lb a0, 0xe(t1)
dsubu a0, a0, 0x1
sb a0, 0x12(t1)
b odt_end_set
nop
2:
lb a0, 0xc(t1)
dsubu a0, a0, 0x2
sb a0, 0x10(t1)
lb a0, 0xe(t1)
sb a0, 0x12(t1)
b odt_end_set
nop
odt_end_set:
lb a0, 0xf(t1)
bne a0, 0x3, 1f
nop
li a0, 0x3
sb a0, 0x13(t1)
sb a0, 0x11(t1)
b odt_set_loop
nop
1:
lb a0, 0xd(t1)
bgeu a0, 0x2, 2f
nop
daddu a0, a0, 0x2
sb a0, 0x11(t1)
lb a0, 0xf(t1)
sb a0, 0x13(t1)
b odt_set_loop
nop
2:
lb a0, 0xd(t1)
dsubu a0, a0, 0x2
sb a0, 0x11(t1)
lb a0, 0xf(t1)
daddu a0, a0, 0x1
sb a0, 0x13(t1)
b odt_set_loop
nop
odt_set_loop:
dsubu t0, t0, 0x1
bnez t0, odt_start_set
nop
#endif
dli t1, 0x180
or t1, t1, t8
ld a0, 0x0(t1)
dli t4, 0xffffffffffffff00
and a0, a0, t4
sd a0, 0x0(t1)
leveling_failed:
dli t1, 0x180
or t1, t1, t8
ld a0, 0x0(t1)
@ -2983,16 +3093,7 @@ wait_init_done3:
nop
/* identify wheather there is ecc slice */
li t0, 0x8
dli t1, 0x250
or t1, t1, t8
lb a0, 0x2(t1)
dli t1, 0x1
and a0, a0, t1
bne a0, t1, 1f //when rd_after_write enabled, the 9th device may don't need leveling
nop
daddu t0, t0, 0x1
GET_NUMBER_OF_SLICES
1:
dli t1, 0x20
@ -3070,6 +3171,7 @@ test_memory:
nop
4:
#endif
//set pm_dll_bypass
dli t1, 0x1
sb t1, 0x19(t8)
@ -3077,14 +3179,6 @@ test_memory:
dli t1, 0x0
sb t1, 0x7(t8)
leveling_failed:
dli t1, 0x180
or t1, t1, t8
ld a0, 0x0(t1)
dli t4, 0xffffffffffffff00
and a0, a0, t4
sd a0, 0x0(t1)
move ra, s5
jr ra
nop

89
pmon/arch/mips/mm/ls3A8_ddr_config.S
View File

@ -153,7 +153,7 @@ mc_init:
nop
dla a2, ddr3_RDIMM_reg_data_mc1
21:
#ifdef MULTI_NODE_DDR_PARAM
#if 1//def MULTI_NODE_DDR_PARAM
GET_NODE_ID_a1
beqz a1, 4f
nop
@ -237,7 +237,7 @@ mc_init:
sync
nop
nop
nop
no:p
nop
bal ARB_level
@ -277,6 +277,7 @@ mc_init:
sd s2, 0x350(t8)
sd s2, 0x358(t8)
#ifdef DLL_CK_DELAY_DEBUG
PRINTSTR("\r\nPlease input the min value of dllclkloop: ");
bal inputaddress
nop
@ -288,11 +289,15 @@ mc_init:
dli t6, 0x0
dsll t6, v0, 32 #v0 is the input value
or k1, t6, k1
#else
dli t6, 0x7f00000000
or k1, t6, k1
#endif
loop_test_leveling:
// dla a2, ddr3_RDIMM_reg_data
// beqz k0, mc0
// nop
dla a2, ddr3_RDIMM_reg_data
beqz k0, mc0
nop
dla a2, ddr3_RDIMM_reg_data_mc1
mc0:
ld t2, 0x350(t8)
@ -383,13 +388,18 @@ wait_dram_init_done1:
#ifdef DLL_DELAY_LOOP
/* test memory */
li t0, 0xbfe00180
lb a0, 0x0(t0)
and a0, a0, 0xef
sb a0, 0x0(t0)
sync
// li t0, 0xbfe10424
// lb a0, 0x1(t0)
// and a0, a0, 0xfd
// sb a0, 0x1(t0)
// sync
dmulou t6, s2, 0x100
GET_NODE_ID_a0
or t6, a0, t6
dli t0, 0x9000000000000000
or t0, t6, t0
li t0, 0xa0000000
dli a0, 0x5555555555555555
sd a0, 0x0(t0)
dli a0, 0xaaaaaaaaaaaaaaaa
@ -408,12 +418,12 @@ wait_dram_init_done1:
sd a0, 0x38(t0)
PRINTSTR("The uncache data is:\r\n")
dli t1, 8
dli t5, 0x9000000000000000
dli t1, 0x8
move t5, t0
1:
ld t6, 0x0(t5)
move a0, t5
and a0, a0, 0xfff
and a0, a0, 0xffff
bal hexserial
nop
PRINTSTR(": ")
@ -489,11 +499,11 @@ wait_dram_init_done1:
testfail:
PRINTSTR("The uncached test failed\r\n")
li t0, 0xbfe00180 //enable memory access
lb a0, 0x0(t0)
or a0, a0, 0x10
sb a0, 0x0(t0)
sync
// li t6, 0xbfe10424
// lb a0, 0x1(t6)
// or a0, a0, 0x02
// sb a0, 0x1(t6)
// sync
b 1f
nop
@ -502,11 +512,11 @@ testok:
daddiu t5, t5, 8
bnez t1, 1b
nop
li t0, 0xbfe10424
lb a0, 0x1(t0)
or a0, a0, 0x02
sb a0, 0x1(t0)
sync
// li t6, 0xbfe10424
// lb a0, 0x1(t6)
// or a0, a0, 0x02
// sb a0, 0x1(t6)
// sync
or s2, s2, 0x100
1:
@ -592,9 +602,9 @@ testok:
nop
PRINTSTR("\r\n")
// dla a2, ddr3_RDIMM_reg_data
// beqz k0, mc0_1
// nop
dla a2, ddr3_RDIMM_reg_data
beqz k0, mc0_1
nop
dla a2, ddr3_RDIMM_reg_data_mc1
mc0_1:
ld t2, 0x350(t8)
@ -761,18 +771,6 @@ exchange:
nop
calculate:
dsrl a0, s2, 32
bal hexserial
nop
move a0, s2
bal hexserial
nop
PRINTSTR("\r\n")
PRINTSTR("\r\n")
PRINTSTR("\r\n")
PRINTSTR("\r\n")
PRINTSTR("\r\n")
ld a0, 0x358(t8)
and a0, a0, 0x8000000000000000
beqz a0, 1f
@ -857,8 +855,8 @@ finish:
move a0, t1
bal hexserial
nop
PRINTSTR("\r\n")
PRINTSTR("\r\nPlease write the dll_clk param to corresponding place in loongson_mc2_param.S ,off set is 0x018!!!\r\n")
/*init start*/
dli t6, 0x1
ld t1, START_ADDR(t8)
@ -883,6 +881,14 @@ wait_dram_init_done2:
nop
move s2, k1
#if 1
ddlp:
dli a0, 0x0
b ddlp
nop
#endif
#endif
move t3, k0
@ -894,7 +900,8 @@ wait_dram_init_done2:
or t2, t2, a0
or t0, t0, a0
#ifdef PRINT_DDR_LEVELING //print registers
//#ifdef PRINT_DDR_LEVELING //print registers
#if 1
PRINTSTR("The MC param after leveling is:\r\n")
dli t1, DDR_PARAM_NUM
GET_NODE_ID_a0

Write Preview
Loading…
Cancel
Save