ls2k
/
pmon
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity
Browse Source

1. Add new leveling file to 3a92h 3a9780e and 3a84w 

2. Repair some old problem
3. Fixup the lthalf param for 3a92h
4. Support a kind of SODIMM

Change-Id: I2a4cc0c2d79c353f219e8bc32d5619c079e7cc65
master
liuzhijia 8 years ago
parent
1e17e46211
commit
2d24d34fb4
14 changed files with 6274 additions and 8992 deletions
Whitespace
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
Split View
Diff Options
Show Stats Download Patch File Download Diff File
  1. 151
      Targets/Bonito3a84w/Bonito/ddr_leveling_define.h
  2. 4369
      Targets/Bonito3a84w/Bonito/loongson3C_ddr3_leveling.S
  3. 2
      Targets/Bonito3a84w/Bonito/start.S
  4. 151
      Targets/Bonito3a92h/Bonito/ddr_leveling_define.h
  5. 4120
      Targets/Bonito3a92h/Bonito/loongson3C_ddr3_leveling.S
  6. 3
      Targets/Bonito3a92h/Bonito/loongson_mc2_param.S
  7. 4
      Targets/Bonito3a92h/Bonito/start.S
  8. 2
      Targets/Bonito3a92h/Bonito/tgt_machdep.c
  9. 151
      Targets/Bonito3a9780e/Bonito/ddr_leveling_define.h
  10. 4119
      Targets/Bonito3a9780e/Bonito/loongson3C_ddr3_leveling.S
  11. 2
      Targets/Bonito3a9780e/Bonito/start.S
  12. 2
      Targets/Bonito3c2h/Bonito/start.S
  13. 2
      Targets/Bonito3cserver/Bonito/start.S
  14. 32
      pmon/arch/mips/mm/lsmc_config_param.S

151
Targets/Bonito3a84w/Bonito/ddr_leveling_define.h
View File

@ -0,0 +1,151 @@
#define GET_NUMBER_OF_SLICES \
li t0, 0x8;\
dli t1, 0x250;\
or t1, t1, t8;\
lb a0, 0x2(t1);\
dli t1, 0x1;\
and a0, a0, t1;\
bne a0, t1, 933f ;\
nop;\
daddu t0, t0, 0x1;\
933:;
#define PRINT_THE_MC_PARAM \
dli t4, DDR_PARAM_NUM;\
GET_NODE_ID_a0;\
dli t5, 0x900000000ff00000;\
or t5, t5, a0;\
1:;\
ld t6, 0x0(t5);\
move a0, t5;\
and a0, a0, 0xfff;\
bal hexserial;\
nop;\
PRINTSTR(": ");\
dsrl a0, t6, 32;\
bal hexserial;\
nop;\
move a0, t6;\
bal hexserial;\
nop;\
PRINTSTR("\r\n");\
daddiu t4, t4, -1;\
daddiu t5, t5, 8;\
bnez t4, 1b;\
nop;
#define WRDQS_ADJUST_LOOP \
933:;\
subu t0, t0, 0x1;\
beq t0, 0x0, 936f;\
nop;\
daddu t1, t1, 0x20;\
lb a0, OFFSET_DLL_WRDQS(t1);\
bgeu a0, a2, 933b;\
nop;\
bleu a0, a3, 933b;\
nop;\
dli t4, 0x8;\
and t4, t4, a0;\
beqz t4, 934f;\
nop;\
sb a3, OFFSET_DLL_WRDQS(t1);\
b 935f;\
nop;\
934:;\
sb a2, OFFSET_DLL_WRDQS(t1);\
935:;\
lb a0, OFFSET_DLL_WRDQS(t1);\
blt a0, WRDQS_LTHF_STD, 937f;\
nop;\
li t4, 0x0;\
sb t4, OFFSET_WRDQS_LTHF(t1);\
b 938f;\
nop;\
937:;\
li t4, 0x1;\
sb t4, OFFSET_WRDQS_LTHF(t1);\
938:;\
dsubu a0, a0, 0x20;\
dli t4, 0x7f;\
and a0, a0, t4;\
sb a0, OFFSET_DLL_WRDQ(t1);\
blt a0, WRDQ_LTHF_STD, 937f;\
nop;\
li t4, 0x0;\
sb t4, OFFSET_WRDQ_LTHF(t1);\
b 938f;\
nop;\
937:;\
li t4, 0x1;\
sb t4, OFFSET_WRDQ_LTHF(t1);\
938:;\
b 933b;\
nop;\
936:;\
#define RDOE_SUB_TRDDATA_ADD \
bne a0, 0x4, 934f;\
nop;\
li a1, 0x8;\
dli t4, 0x250;\
or t4, t4, t8;\
lb a0, 0x2(t4);\
dli t4, 0x1;\
and a0, a0, t4;\
bne a0, t4, 932f ;\
nop;\
daddu a1, a1, 0x1;\
932: ;\
dli t4, 0x28;\
or t4, t4, t8;\
933: ;\
lb a0, 0x7(t4);\
dsubu a0, a0, 0x1;\
sb a0, 0x7(t4);\
lb a0, 0x6(t4);\
dsubu a0, a0, 0x1;\
sb a0, 0x6(t4);\
daddu t4, t4, 0x20;\
dsubu a1, a1, 0x1;\
bnez a1, 933b;\
nop;\
dli t4, 0x1c0;\
or t4, t4, t8;\
lb a0, 0x0(t4);\
daddu a0, a0, 0x1;\
sb a0, 0x0(t4);\
934: ;
#define RDOE_ADD_TRDDATA_SUB \
bne a0, 0x0, 934f;\
nop ;\
li a1, 0x8;\
dli t4, 0x250;\
or t4, t4, t8;\
lb a0, 0x2(t4);\
dli t4, 0x1;\
and a0, a0, t4;\
bne a0, t4, 932f ;\
nop;\
daddu a1, a1, 0x1;\
932: ;\
dli t4, 0x28;\
or t4, t4, t8;\
933: ;\
lb a0, 0x7(t4);\
daddu a0, a0, 0x1;\
sb a0, 0x7(t4);\
lb a0, 0x6(t4);\
daddu a0, a0, 0x1;\
sb a0, 0x6(t4);\
daddu t4, t4, 0x20;\
dsubu a1, a1, 0x1;\
bnez a1, 933b;\
nop;\
dli t4, 0x1c0;\
or t4, t4, t8;\
lb a0, 0x0(t4);\
dsubu a0, a0, 0x1;\
sb a0, 0x0(t4);\
934: ;

4369
Targets/Bonito3a84w/Bonito/loongson3C_ddr3_leveling.S
View File

File diff suppressed because it is too large

2
Targets/Bonito3a84w/Bonito/start.S
View File

@ -2195,7 +2195,7 @@ idle1000:
#######################################
#include "ddr_dir/ls3A8_ddr_config.S"
#ifdef DDR3_DIMM
#include "ddr_dir/loongson3C_ddr3_leveling.S"
#include "loongson3C_ddr3_leveling.S"
#endif
#ifdef ARB_LEVEL
#include "ddr_dir/ARB_level_new.S"

151
Targets/Bonito3a92h/Bonito/ddr_leveling_define.h
View File

@ -0,0 +1,151 @@
#define GET_NUMBER_OF_SLICES \
li t0, 0x8;\
dli t1, 0x250;\
or t1, t1, t8;\
lb a0, 0x2(t1);\
dli t1, 0x1;\
and a0, a0, t1;\
bne a0, t1, 933f ;\
nop;\
daddu t0, t0, 0x1;\
933:;
#define PRINT_THE_MC_PARAM \
dli t4, DDR_PARAM_NUM;\
GET_NODE_ID_a0;\
dli t5, 0x900000000ff00000;\
or t5, t5, a0;\
1:;\
ld t6, 0x0(t5);\
move a0, t5;\
and a0, a0, 0xfff;\
bal hexserial;\
nop;\
PRINTSTR(": ");\
dsrl a0, t6, 32;\
bal hexserial;\
nop;\
move a0, t6;\
bal hexserial;\
nop;\
PRINTSTR("\r\n");\
daddiu t4, t4, -1;\
daddiu t5, t5, 8;\
bnez t4, 1b;\
nop;
#define WRDQS_ADJUST_LOOP \
933:;\
subu t0, t0, 0x1;\
beq t0, 0x0, 936f;\
nop;\
daddu t1, t1, 0x20;\
lb a0, OFFSET_DLL_WRDQS(t1);\
bgeu a0, a2, 933b;\
nop;\
bleu a0, a3, 933b;\
nop;\
dli t4, 0x8;\
and t4, t4, a0;\
beqz t4, 934f;\
nop;\
sb a3, OFFSET_DLL_WRDQS(t1);\
b 935f;\
nop;\
934:;\
sb a2, OFFSET_DLL_WRDQS(t1);\
935:;\
lb a0, OFFSET_DLL_WRDQS(t1);\
blt a0, WRDQS_LTHF_STD, 937f;\
nop;\
li t4, 0x0;\
sb t4, OFFSET_WRDQS_LTHF(t1);\
b 938f;\
nop;\
937:;\
li t4, 0x1;\
sb t4, OFFSET_WRDQS_LTHF(t1);\
938:;\
dsubu a0, a0, 0x20;\
dli t4, 0x7f;\
and a0, a0, t4;\
sb a0, OFFSET_DLL_WRDQ(t1);\
blt a0, WRDQ_LTHF_STD, 937f;\
nop;\
li t4, 0x0;\
sb t4, OFFSET_WRDQ_LTHF(t1);\
b 938f;\
nop;\
937:;\
li t4, 0x1;\
sb t4, OFFSET_WRDQ_LTHF(t1);\
938:;\
b 933b;\
nop;\
936:;\
#define RDOE_SUB_TRDDATA_ADD \
bne a0, 0x4, 934f;\
nop;\
li a1, 0x8;\
dli t4, 0x250;\
or t4, t4, t8;\
lb a0, 0x2(t4);\
dli t4, 0x1;\
and a0, a0, t4;\
bne a0, t4, 932f ;\
nop;\
daddu a1, a1, 0x1;\
932: ;\
dli t4, 0x28;\
or t4, t4, t8;\
933: ;\
lb a0, 0x7(t4);\
dsubu a0, a0, 0x1;\
sb a0, 0x7(t4);\
lb a0, 0x6(t4);\
dsubu a0, a0, 0x1;\
sb a0, 0x6(t4);\
daddu t4, t4, 0x20;\
dsubu a1, a1, 0x1;\
bnez a1, 933b;\
nop;\
dli t4, 0x1c0;\
or t4, t4, t8;\
lb a0, 0x0(t4);\
daddu a0, a0, 0x1;\
sb a0, 0x0(t4);\
934: ;
#define RDOE_ADD_TRDDATA_SUB \
bne a0, 0x0, 934f;\
nop ;\
li a1, 0x8;\
dli t4, 0x250;\
or t4, t4, t8;\
lb a0, 0x2(t4);\
dli t4, 0x1;\
and a0, a0, t4;\
bne a0, t4, 932f ;\
nop;\
daddu a1, a1, 0x1;\
932: ;\
dli t4, 0x28;\
or t4, t4, t8;\
933: ;\
lb a0, 0x7(t4);\
daddu a0, a0, 0x1;\
sb a0, 0x7(t4);\
lb a0, 0x6(t4);\
daddu a0, a0, 0x1;\
sb a0, 0x6(t4);\
daddu t4, t4, 0x20;\
dsubu a1, a1, 0x1;\
bnez a1, 933b;\
nop;\
dli t4, 0x1c0;\
or t4, t4, t8;\
lb a0, 0x0(t4);\
dsubu a0, a0, 0x1;\
sb a0, 0x0(t4);\
934: ;

4120
Targets/Bonito3a92h/Bonito/loongson3C_ddr3_leveling.S
View File

File diff suppressed because it is too large

3
Targets/Bonito3a92h/Bonito/loongson_mc2_param.S
View File

@ -132,7 +132,8 @@ MC0_DDR3_CTRL_0x1b8: .dword 0x0000001000060d40
//_00000000_00000000 pm_mr_3_cs_3 _00000000_00000000 pm_mr_2_cs_3 _00000000_00000000 pm_mr_1_cs_3 _00000000_00000000 pm_mr_0_cs_3
MC0_DDR3_CTRL_0x1c0: .dword 0x3030c80b03042005
//_00000000 pm_tRESET _00000000 pm_tCKE _00000000 pm_tXPR _00000000 pm_tMOD _00000000 pm_tZQCL _00000000 pm_tZQ_CMD _00000000 pm_tWLDQSEN 000_00000 pm_tRDDATA
MC0_DDR3_CTRL_0x1c8: .dword 0x11040b0b0f804080
//MC0_DDR3_CTRL_0x1c8: .dword 0x11040b0b0f804080
MC0_DDR3_CTRL_0x1c8: .dword 0x11040b0b0fd04080
//00_000000 pm_tFAW 0000_0000 pm_tRRD 0000_0000 pm_tRCD _00000000 pm_tRP _00000000 pm_tREF _00000000 pm_tRFC _00000000 pm_tZQCS _00000000 pm_tZQperiod
MC0_DDR3_CTRL_0x1d0: .dword 0x0a020d0402000018
//0000_0000 pm_tODTL _00000000 pm_tXSRD 0000_0000 pm_tPHY_RDLAT 000_00000 pm_tPHY_WRLAT 000000_00_00000000_00000000 pm_tRAS_max 00_000000 pm_tRAS_min

4
Targets/Bonito3a92h/Bonito/start.S
View File

@ -628,7 +628,7 @@ soft_out:
#include "loongson3_HT_init_2h.S"
bal beep_on
nop
li a0, 0x800
li a0, 0x800000
1:
addiu a0, a0, -1
nop
@ -1531,7 +1531,7 @@ watchdog_enable:
#######################################
#include "ddr_dir/ls3A8_ddr_config.S"
#ifdef DDR3_DIMM
#include "ddr_dir/loongson3C_ddr3_leveling.S"
#include "loongson3C_ddr3_leveling.S"
#endif
#ifdef ARB_LEVEL
#include "ddr_dir/ARB_level_new.S"

2
Targets/Bonito3a92h/Bonito/tgt_machdep.c
View File

@ -295,7 +295,7 @@ initmips(unsigned long long raw_memsz)
/*
* Probe clock frequencys so delays will work properly.
*/
for (i = 0;i < 6;i++)
for (i = 0;i < 10;i++)
{
tgt_printf(" . ");
delay(0x200000);

151
Targets/Bonito3a9780e/Bonito/ddr_leveling_define.h
View File

@ -0,0 +1,151 @@
#define GET_NUMBER_OF_SLICES \
li t0, 0x8;\
dli t1, 0x250;\
or t1, t1, t8;\
lb a0, 0x2(t1);\
dli t1, 0x1;\
and a0, a0, t1;\
bne a0, t1, 933f ;\
nop;\
daddu t0, t0, 0x1;\
933:;
#define PRINT_THE_MC_PARAM \
dli t4, DDR_PARAM_NUM;\
GET_NODE_ID_a0;\
dli t5, 0x900000000ff00000;\
or t5, t5, a0;\
1:;\
ld t6, 0x0(t5);\
move a0, t5;\
and a0, a0, 0xfff;\
bal hexserial;\
nop;\
PRINTSTR(": ");\
dsrl a0, t6, 32;\
bal hexserial;\
nop;\
move a0, t6;\
bal hexserial;\
nop;\
PRINTSTR("\r\n");\
daddiu t4, t4, -1;\
daddiu t5, t5, 8;\
bnez t4, 1b;\
nop;
#define WRDQS_ADJUST_LOOP \
933:;\
subu t0, t0, 0x1;\
beq t0, 0x0, 936f;\
nop;\
daddu t1, t1, 0x20;\
lb a0, OFFSET_DLL_WRDQS(t1);\
bgeu a0, a2, 933b;\
nop;\
bleu a0, a3, 933b;\
nop;\
dli t4, 0x8;\
and t4, t4, a0;\
beqz t4, 934f;\
nop;\
sb a3, OFFSET_DLL_WRDQS(t1);\
b 935f;\
nop;\
934:;\
sb a2, OFFSET_DLL_WRDQS(t1);\
935:;\
lb a0, OFFSET_DLL_WRDQS(t1);\
blt a0, WRDQS_LTHF_STD, 937f;\
nop;\
li t4, 0x0;\
sb t4, OFFSET_WRDQS_LTHF(t1);\
b 938f;\
nop;\
937:;\
li t4, 0x1;\
sb t4, OFFSET_WRDQS_LTHF(t1);\
938:;\
dsubu a0, a0, 0x20;\
dli t4, 0x7f;\
and a0, a0, t4;\
sb a0, OFFSET_DLL_WRDQ(t1);\
blt a0, WRDQ_LTHF_STD, 937f;\
nop;\
li t4, 0x0;\
sb t4, OFFSET_WRDQ_LTHF(t1);\
b 938f;\
nop;\
937:;\
li t4, 0x1;\
sb t4, OFFSET_WRDQ_LTHF(t1);\
938:;\
b 933b;\
nop;\
936:;\
#define RDOE_SUB_TRDDATA_ADD \
bne a0, 0x4, 934f;\
nop;\
li a1, 0x8;\
dli t4, 0x250;\
or t4, t4, t8;\
lb a0, 0x2(t4);\
dli t4, 0x1;\
and a0, a0, t4;\
bne a0, t4, 932f ;\
nop;\
daddu a1, a1, 0x1;\
932: ;\
dli t4, 0x28;\
or t4, t4, t8;\
933: ;\
lb a0, 0x7(t4);\
dsubu a0, a0, 0x1;\
sb a0, 0x7(t4);\
lb a0, 0x6(t4);\
dsubu a0, a0, 0x1;\
sb a0, 0x6(t4);\
daddu t4, t4, 0x20;\
dsubu a1, a1, 0x1;\
bnez a1, 933b;\
nop;\
dli t4, 0x1c0;\
or t4, t4, t8;\
lb a0, 0x0(t4);\
daddu a0, a0, 0x1;\
sb a0, 0x0(t4);\
934: ;
#define RDOE_ADD_TRDDATA_SUB \
bne a0, 0x0, 934f;\
nop ;\
li a1, 0x8;\
dli t4, 0x250;\
or t4, t4, t8;\
lb a0, 0x2(t4);\
dli t4, 0x1;\
and a0, a0, t4;\
bne a0, t4, 932f ;\
nop;\
daddu a1, a1, 0x1;\
932: ;\
dli t4, 0x28;\
or t4, t4, t8;\
933: ;\
lb a0, 0x7(t4);\
daddu a0, a0, 0x1;\
sb a0, 0x7(t4);\
lb a0, 0x6(t4);\
daddu a0, a0, 0x1;\
sb a0, 0x6(t4);\
daddu t4, t4, 0x20;\
dsubu a1, a1, 0x1;\
bnez a1, 933b;\
nop;\
dli t4, 0x1c0;\
or t4, t4, t8;\
lb a0, 0x0(t4);\
dsubu a0, a0, 0x1;\
sb a0, 0x0(t4);\
934: ;

4119
Targets/Bonito3a9780e/Bonito/loongson3C_ddr3_leveling.S
View File

File diff suppressed because it is too large

2
Targets/Bonito3a9780e/Bonito/start.S
View File

@ -1743,7 +1743,7 @@ idle1000:
#######################################
#include "ddr_dir/ls3A8_ddr_config.S"
#ifdef DDR3_DIMM
#include "ddr_dir/loongson3C_ddr3_leveling.S"
#include "loongson3C_ddr3_leveling.S"
#endif
#ifdef ARB_LEVEL
#include "ddr_dir/ARB_level_new.S"

2
Targets/Bonito3c2h/Bonito/start.S
View File

@ -3234,7 +3234,7 @@ idle1000:
#######################################
#include "ddr_dir/ls3B5_ddr_config.S"
#include "ddr_dir/loongson3C_ddr3_leveling.S"
#include "loongson3C_ddr3_leveling.S"
#ifdef DEBUG_DDR
#include "ddr_dir/Test_Mem.S"
#endif

2
Targets/Bonito3cserver/Bonito/start.S
View File

@ -2429,7 +2429,7 @@ idle1000:
#######################################
#include "ddr_dir/ls3B5_ddr_config.S"
#include "ddr_dir/loongson3C_ddr3_leveling.S"
#include "loongson3C_ddr3_leveling.S"
#ifdef DEBUG_DDR
#include "ddr_dir/Test_Mem.S"
#endif

32
pmon/arch/mips/mm/lsmc_config_param.S
View File

@ -329,38 +329,6 @@ set_tRTP:
daddu a2, a2, a1
sd a2, TPHY_WRLAT(t8)
1:
//rewrite eight_bank_mode
//rewrite pm_bank_diff_0 and pm_bank
//for UDIMM 4cs,open 2T mode
GET_DIMM_TYPE
bnez a1, 1f
nop
//UDIMM
GET_MC_CS_MAP
dli a2, 0xf
bne a1, a2, 1f
nop
//add cmd_timing ,trddata and tphy_wrlat by one
ld a2, CMD_TIMING(t8)
dli a1, 0x1
dsll a1, a1, CMD_TIMING_OFFSET
daddu a2, a2, a1
sd a2, CMD_TIMING(t8)
ld a2, TRDDATA(t8)
dli a1, 0x1
dsll a1, a1, TRDDATA_OFFSET
daddu a2, a2, a1
sd a2, TRDDATA(t8)
ld a2, TPHY_WRLAT(t8)
dli a1, 0x1
dsll a1, a1, TPHY_WRLAT_OFFSET
daddu a2, a2, a1
sd a2, TPHY_WRLAT(t8)
1:
//rewrite eight_bank_mode
//rewrite pm_bank_diff_0 and pm_bank

Write Preview
Loading…
Cancel
Save