lixuefeng
8 years ago
14 changed files with 4928 additions and 52 deletions
File diff suppressed because it is too large
@ -0,0 +1,198 @@ |
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#ifndef _GMAC_H_ |
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#define _GMAC_H_ |
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|
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#define u16 unsigned short |
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#if 0 |
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#define GMAC0_MAC_REG_ADDR 0xffffffffbbe10000 |
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#define GMAC0_DMA_REG_ADDR 0xffffffffbbe11000 |
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#define GMAC1_MAC_REG_ADDR 0xffffffffbbe18000 |
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#define GMAC1_DMA_REG_ADDR 0xffffffffbbe19000 |
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|
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#define GMAC0_RX_DESC_BASE 0x9000000000060000 |
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#define GMAC1_RX_DESC_BASE 0x9000000000060200 |
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#define GMAC0_RX_DESC_BASE_PHY 0x60000 |
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|
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#define GMAC0_RDES0_VALUE 0x80000000 |
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#define GMAC0_RDES1_VALUE 0x4110 |
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#define GMAC0_RDES1_END_VALUE 0x8100 |
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|
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#define GMAC0_TX_DESC_BASE 0x9000000000040000 |
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#define GMAC1_TX_DESC_BASE 0x9000000000040200 |
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#define GMAC0_TX_DESC_BASE_PHY 0x40000 |
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#else |
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#define GMAC0_MAC_REG_ADDR 0xffffffffbbe10000 |
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#define GMAC0_DMA_REG_ADDR 0xffffffffbbe11000 |
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#define GMAC1_MAC_REG_ADDR 0xffffffffbbe18000 |
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#define GMAC1_DMA_REG_ADDR 0xffffffffbbe19000 |
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|
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#define GMAC0_RX_DESC_BASE 0xa0060000 |
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#define GMAC1_RX_DESC_BASE 0xa0060200 |
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#define GMAC0_RX_DESC_BASE_PHY 0x60000 |
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|
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#define GMAC0_RDES0_VALUE 0x80000000 |
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#define GMAC0_RDES1_VALUE 0x4110 |
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#define GMAC0_RDES1_END_VALUE 0x8100 |
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|
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#define GMAC0_TX_DESC_BASE 0xa0040000 |
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#define GMAC1_TX_DESC_BASE 0xa0040200 |
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#define GMAC0_TX_DESC_BASE_PHY 0x40000 |
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#endif |
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#define GMAC0_TDES0_VALUE 0xb0100000 |
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#define GMAC0_TDES0_VALUE_END 0xb0200000 |
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#define GMAC0_TDES1_VALUE 0x100 |
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|
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#define DmaBusMode_SWR 0x1 |
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#define DmaBusMode_PBL 0X400 |
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#define GmacConfig_DM (1 << 11) |
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#define GmacConfig_IFG 0xc000 |
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#define GmacFrameFilter_RA (1 << 31) |
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#define GmacConfig_RE (1 << 2) |
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#define GmacConfig_TE (1 << 3) |
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#define DmaControl_SR (1 << 1) |
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#define DmaControl_ST (1 << 13) |
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#define DmaControl_TSF (1 << 21) |
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#define DmaControl_RSF (1 << 25) |
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|
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#define SGMII_STATUS 0xd8 |
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#define SGMII_STATUS_LINK_STATUS (1 << 3) |
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|
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/*RTL8211E REG*/ |
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#define PHY_BMCR 0x0 |
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#define PHY_BMCR_LOOPBACK (1 << 14) |
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#define PHY_BMCR_SPEED (0X2000) |
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#define PHY_BMCR_DUPLEX (1 << 8) |
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#define PHY_PHYSR 0x11 |
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#define PHY_PHYSR_LINK_STATUS (1 << 10) |
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|
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#define TX_BUF_SIZE 0xc00 |
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|
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#define ls_readl(x) (*(volatile u32*)(x)) |
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|
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#define DEFAULT_DELAY_VARIABLE 10 |
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#define DEFAULT_LOOP_VARIABLE 10000 |
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#define SYNOP_PHY_LOOPBACK 1 |
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|
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/* Error Codes */ |
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#define ESYNOPGMACNOERR 0 |
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#define ESYNOPGMACNOMEM 1 |
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#define ESYNOPGMACPHYERR 2 |
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#define ESYNOPGMACBUSY 3 |
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|
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enum GmacRegisters |
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{ |
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GmacConfig = 0x0000, /* Mac config Register */ |
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GmacFrameFilter = 0x0004, /* Mac frame filtering controls */ |
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GmacHashHigh = 0x0008, /* Multi-cast hash table high */ |
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GmacHashLow = 0x000C, /* Multi-cast hash table low */ |
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GmacGmiiAddr = 0x0010, /* GMII address Register(ext. Phy) */ |
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GmacGmiiData = 0x0014, /* GMII data Register(ext. Phy) */ |
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GmacFlowControl = 0x0018, /* Flow control Register */ |
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GmacVlan = 0x001C, /* VLAN tag Register (IEEE 802.1Q) */ |
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|
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GmacVersion = 0x0020, /* GMAC Core Version Register */ |
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GmacWakeupAddr = 0x0028, /* GMAC wake-up frame filter adrress reg */ |
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GmacPmtCtrlStatus = 0x002C, /* PMT control and status register */ |
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|
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GmacInterruptStatus = 0x0038, /* Mac Interrupt ststus register */ |
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GmacInterruptMask = 0x003C, /* Mac Interrupt Mask register */ |
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|
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GmacAddr0High = 0x0040, /* Mac address0 high Register */ |
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GmacAddr0Low = 0x0044, /* Mac address0 low Register */ |
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GmacAddr1High = 0x0048, /* Mac address1 high Register */ |
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GmacAddr1Low = 0x004C, /* Mac address1 low Register */ |
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GmacAddr2High = 0x0050, /* Mac address2 high Register */ |
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GmacAddr2Low = 0x0054, /* Mac address2 low Register */ |
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GmacAddr3High = 0x0058, /* Mac address3 high Register */ |
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GmacAddr3Low = 0x005C, /* Mac address3 low Register */ |
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GmacAddr4High = 0x0060, /* Mac address4 high Register */ |
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GmacAddr4Low = 0x0064, /* Mac address4 low Register */ |
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GmacAddr5High = 0x0068, /* Mac address5 high Register */ |
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GmacAddr5Low = 0x006C, /* Mac address5 low Register */ |
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GmacAddr6High = 0x0070, /* Mac address6 high Register */ |
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GmacAddr6Low = 0x0074, /* Mac address6 low Register */ |
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GmacAddr7High = 0x0078, /* Mac address7 high Register */ |
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GmacAddr7Low = 0x007C, /* Mac address7 low Register */ |
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GmacAddr8High = 0x0080, /* Mac address8 high Register */ |
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GmacAddr8Low = 0x0084, /* Mac address8 low Register */ |
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GmacAddr9High = 0x0088, /* Mac address9 high Register */ |
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GmacAddr9Low = 0x008C, /* Mac address9 low Register */ |
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GmacAddr10High = 0x0090, /* Mac address10 high Register */ |
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GmacAddr10Low = 0x0094, /* Mac address10 low Register */ |
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GmacAddr11High = 0x0098, /* Mac address11 high Register */ |
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GmacAddr11Low = 0x009C, /* Mac address11 low Register */ |
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GmacAddr12High = 0x00A0, /* Mac address12 high Register */ |
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GmacAddr12Low = 0x00A4, /* Mac address12 low Register */ |
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GmacAddr13High = 0x00A8, /* Mac address13 high Register */ |
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GmacAddr13Low = 0x00AC, /* Mac address13 low Register */ |
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GmacAddr14High = 0x00B0, /* Mac address14 high Register */ |
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GmacAddr14Low = 0x00B4, /* Mac address14 low Register */ |
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GmacAddr15High = 0x00B8, /* Mac address15 high Register */ |
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GmacAddr15Low = 0x00BC, /* Mac address15 low Register */ |
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|
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/*Time Stamp Register Map*/ |
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GmacTSControl = 0x0700, /* Controls the Timestamp update logic : only when IEEE 1588 time stamping is enabled in corekit */ |
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|
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GmacTSSubSecIncr = 0x0704, /* 8 bit value by which sub second register is incremented : only when IEEE 1588 time stamping without external timestamp input */ |
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GmacTSHigh = 0x0708, /* 32 bit seconds(MS) : only when IEEE 1588 time stamping without external timestamp input */ |
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GmacTSLow = 0x070C, /* 32 bit nano seconds(MS) : only when IEEE 1588 time stamping without external timestamp input */ |
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|
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GmacTSHighUpdate = 0x0710, /* 32 bit seconds(MS) to be written/added/subtracted : only when IEEE 1588 time stamping without external timestamp input */ |
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GmacTSLowUpdate = 0x0714, /* 32 bit nano seconds(MS) to be writeen/added/subtracted : only when IEEE 1588 time stamping without external timestamp input */ |
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|
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GmacTSAddend = 0x0718, /* Used by Software to readjust the clock frequency linearly : only when IEEE 1588 time stamping without external timestamp input */ |
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|
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GmacTSTargetTimeHigh = 0x071C, /* 32 bit seconds(MS) to be compared with system time : only when IEEE 1588 time stamping without external timestamp input */ |
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GmacTSTargetTimeLow = 0x0720, /* 32 bit nano seconds(MS) to be compared with system time : only when IEEE 1588 time stamping without external timestamp input */ |
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|
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GmacTSHighWord = 0x0724, /* Time Stamp Higher Word Register (Version 2 only); only lower 16 bits are valid */ |
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//GmacTSHighWordUpdate = 0x072C, /* Time Stamp Higher Word Update Register (Version 2 only); only lower 16 bits are valid */
|
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|
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GmacTSStatus = 0x0728, /* Time Stamp Status Register */ |
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}; |
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/**********************************************************
|
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* GMAC DMA registers |
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* For Pci based system address is BARx + GmaDmaBase |
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* For any other system translation is done accordingly |
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**********************************************************/ |
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|
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enum DmaRegisters |
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{ |
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DmaBusMode = 0x0000, /* CSR0 - Bus Mode Register */ |
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DmaTxPollDemand = 0x0004, /* CSR1 - Transmit Poll Demand Register */ |
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DmaRxPollDemand = 0x0008, /* CSR2 - Receive Poll Demand Register */ |
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DmaRxBaseAddr = 0x000C, /* CSR3 - Receive Descriptor list base address */ |
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DmaTxBaseAddr = 0x0010, /* CSR4 - Transmit Descriptor list base address */ |
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DmaStatus = 0x0014, /* CSR5 - Dma status Register */ |
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DmaControl = 0x0018, /* CSR6 - Dma Operation Mode Register */ |
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DmaInterrupt = 0x001C, /* CSR7 - Interrupt enable */ |
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DmaMissedFr = 0x0020, /* CSR8 - Missed Frame & Buffer overflow Counter */ |
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DmaTxCurrDesc = 0x0048, /* - Current host Tx Desc Register */ |
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DmaRxCurrDesc = 0x004C, /* - Current host Rx Desc Register */ |
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DmaTxCurrAddr = 0x0050, /* CSR20 - Current host transmit buffer address */ |
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DmaRxCurrAddr = 0x0054, /* CSR21 - Current host receive buffer address */ |
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}; |
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|
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|
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enum GmacGmiiAddrReg |
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{ |
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GmiiDevMask = 0x0000F800, /* (PA)GMII device address 15:11 RW 0x00 */ |
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GmiiDevShift = 11, |
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|
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GmiiRegMask = 0x000007C0, /* (GR)GMII register in selected Phy 10:6 RW 0x00 */ |
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GmiiRegShift = 6, |
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GmiiCsrClkMask = 0x0000001C, /*CSR Clock bit Mask 4:2 */ |
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GmiiCsrClk5 = 0x00000014, /* (CR)CSR Clock Range 250-300 MHz 4:2 RW 000 */ |
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GmiiCsrClk4 = 0x00000010, /* 150-250 MHz */ |
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GmiiCsrClk3 = 0x0000000C, /* 35-60 MHz */ |
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GmiiCsrClk2 = 0x00000008, /* 20-35 MHz */ |
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GmiiCsrClk1 = 0x00000004, /* 100-150 MHz */ |
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GmiiCsrClk0 = 0x00000000, /* 60-100 MHz */ |
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GmiiWrite = 0x00000002, /* (GW)Write to register 1 RW */ |
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GmiiRead = 0x00000000, /* Read from register 0 */ |
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GmiiBusy = 0x00000001, /* (GB)GMII interface is busy 0 RW 0 */ |
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}; |
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#endif /*_GMAC_H_*/ |
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@ -0,0 +1,130 @@ |
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//cpu fan pwm1 output,pwm2 intput.
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#include <stdio.h> |
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#include <pmon.h> |
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#define LS2H_PWM_REG_BASE 0xbbea0000 //2H 0x1fea0000
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#define PWM_LOWBUF_OFFSET 0x4 |
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#define PWM_FULLBUF_OFFSET 0x8 |
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#define PWM_CTRL_OFFSET 0xc |
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#define PWM_CTRL_EN (1 << 0) |
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#define PWM_CTRL_CAPTE (1 << 8) |
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|
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#define LS2H_GPIOCFG 0xbbd000c0 //2H gpiocfg
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#define read_w(x) (*(volatile unsigned int*)(x)) |
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#define write_w(x,val) (*(volatile unsigned int*)(x) = val) |
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//#define DEBUG
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#ifdef DEBUG |
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#define dbg(format, arg...) printf(format, ## arg) |
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#else |
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#define dbg(format, arg...) |
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#endif |
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|
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static int fan_speed(ac,av) |
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int ac; |
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char *av[]; |
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{ |
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unsigned int tmp, tmp1, tmp_speed, total_val = 0, i; |
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read_w(LS2H_GPIOCFG) |= ((0xf << 12) | (1 << 17));//pwm enable,pwm2 output
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dbg("gpiocfg->%x\n", read_w(LS2H_GPIOCFG)); |
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delay(0x400000);//wait for the pwm intput value valide.
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for (i = 0;i < 20;i++) { |
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read_w(LS2H_PWM_REG_BASE + (0x10 * 2) + PWM_CTRL_OFFSET) |= (PWM_CTRL_CAPTE | PWM_CTRL_EN); |
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dbg("pwm2 ctrl->%x\n", read_w(LS2H_GPIOCFG)); |
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speed_read: |
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tmp = read_w(LS2H_PWM_REG_BASE + (0x10 * 2) + PWM_LOWBUF_OFFSET); |
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dbg("tmp->%x\n", tmp); |
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tmp1 = read_w(LS2H_PWM_REG_BASE + (0x10 * 2) + PWM_FULLBUF_OFFSET); |
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dbg("tmp1->%x\n", tmp1); |
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if ((tmp > tmp1) || (tmp < 0x1000) || (tmp < 0x1000)) |
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goto speed_read; |
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// tmp_speed = (1000000000 * 60)/((1000 / 125) * tmp1 * 2); //this code is overflow.
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tmp_speed = (62500000 * 6)/(tmp1 / 10); |
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dbg("fan speed -> %d\n", tmp_speed); |
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total_val += tmp_speed; |
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} |
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dbg("total fan speed -> %d\n", total_val); |
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tmp_speed = total_val / 20; |
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if(ac == 1) |
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printf("fan speed -> %d\n", tmp_speed); |
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return tmp_speed; |
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} |
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static int fan_set(ac, av) |
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int ac; |
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char *av[]; |
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{ |
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unsigned int speed, tmp_speed, tmp_speed1, goal_speed, tmp_reg; |
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int i; |
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if (ac < 2) { |
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printf("parameter is error!\n"); |
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return -1; |
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} |
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if (read_w(LS2H_PWM_REG_BASE + (0x10 * 1) + PWM_FULLBUF_OFFSET) == 0) { |
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read_w(LS2H_GPIOCFG) |= ((0xf << 12) | (1 << 17));//pwm enable
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dbg("gpiocfg->%x\n", read_w(LS2H_GPIOCFG)); |
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write_w(LS2H_PWM_REG_BASE + (0x10 * 1) + PWM_FULLBUF_OFFSET,0x1000); |
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write_w(LS2H_PWM_REG_BASE + (0x10 * 1) + PWM_LOWBUF_OFFSET,0x800); |
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write_w(LS2H_PWM_REG_BASE + (0x10 * 1) + PWM_CTRL_OFFSET,PWM_CTRL_EN); |
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} |
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goal_speed = atoi(av[1]); |
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printf("goal fan speed %d\n",goal_speed); |
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if ((goal_speed > 4700) && (goal_speed < 2200)) { |
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printf("goal speed can not complete!The fan speed is (2200 - 4600)\n"); |
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return -2; |
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} |
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speed = fan_speed(); |
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tmp_reg = read_w(LS2H_PWM_REG_BASE + (0x10 * 1) + PWM_LOWBUF_OFFSET); |
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|
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if (goal_speed > speed){ |
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for (i = tmp_reg;i > 0x80; i -= 0x40) { |
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dbg("value 0x%x\n",i); |
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write_w(LS2H_PWM_REG_BASE + (0x10 * 1) + PWM_LOWBUF_OFFSET, i); |
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speed = fan_speed(); |
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if (speed > goal_speed) { |
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tmp_speed1 = speed - goal_speed; |
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dbg("tmp_speed1 %d tmp_speed %d\n",tmp_speed1,tmp_speed); |
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if(tmp_speed1 > tmp_speed) |
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write_w(LS2H_PWM_REG_BASE + (0x10 * 1) + PWM_LOWBUF_OFFSET, i + 0x40); |
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break; |
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} |
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tmp_speed = goal_speed - speed; |
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} |
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} else if (goal_speed < speed) { |
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for (i = tmp_reg;i < 0x1000; i += 0x40) { |
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dbg("2 value 0x%x\n",i); |
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write_w(LS2H_PWM_REG_BASE + (0x10 * 1) + PWM_LOWBUF_OFFSET, i); |
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speed = fan_speed(); |
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if (speed < goal_speed) { |
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tmp_speed1 = goal_speed - speed; |
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dbg("2 tmp_speed1 %d tmp_speed %d\n",tmp_speed1,tmp_speed); |
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if(tmp_speed1 > tmp_speed) |
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write_w(LS2H_PWM_REG_BASE + (0x10 * 1) + PWM_LOWBUF_OFFSET, i - 0x40); |
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break; |
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} |
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tmp_speed = speed - goal_speed; |
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} |
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} |
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printf("ctual fan speed %d\n",fan_speed()); |
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return 0; |
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} |
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|
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static const Cmd Cmds[] = |
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{ |
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{"Misc"}, |
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{"fan_speed", "", 0, "3a2h fan speed test ", fan_speed, 1, 99, 0}, |
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{"fan_set", "", 0, "3a2h set fan speed test ", fan_set, 1, 99, 0}, |
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{0, 0} |
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}; |
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|
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static void init_cmd __P((void)) __attribute__ ((constructor)); |
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|
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void |
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init_cmd() |
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{ |
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cmdlist_expand(Cmds, 1); |
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} |
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@ -0,0 +1,597 @@ |
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/* $Id: fan.c,v 1.1.1.1 2006/09/14 01:59:08 xqch Exp $ */ |
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/*
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* Copyright (c) 2001 Opsycon AB (www.opsycon.se) |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. All advertising materials mentioning features or use of this software |
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* must display the following acknowledgement: |
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* This product includes software developed by Opsycon AB, Sweden. |
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* 4. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS |
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* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY |
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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*/ |
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|
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#include <stdio.h> |
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#include <string.h> |
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#include <stdlib.h> |
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#include <sys/device.h> |
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#include <sys/queue.h> |
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#include <pmon.h> |
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|
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#include "gmac.h" |
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#define read32(x) (*(volatile unsigned int *)(x)) |
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#define read8(x) (*(volatile unsigned char *)(x)) |
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unsigned char |
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cmd_usbtest(ac, av) |
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int ac; |
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char *av[]; |
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{ |
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unsigned int base = 0xbbe00000; |
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int port,test_mode; |
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if (ac != 3){ |
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printf("Usage:usbtest <port > <T> \n"); |
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printf("port0: 0\n"); |
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printf("port1: 1\n"); |
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printf("port2: 2\n"); |
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printf("port3: 3\n"); |
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printf("port4: 4\n"); |
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printf("port5: 5\n"); |
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printf("<T> 1: J_STATE\n"); |
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printf("<T> 2: K_STATE\n"); |
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printf("<T> 3: SE0_NAK\n"); |
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printf("<T> 4: Packet\n"); |
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printf("<T> 5: FORCE_ENABLE\n"); |
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printf("For example:usbtest 1 1 \n"); |
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return 0; |
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} |
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port = atoi(av[1]); |
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test_mode = atoi(av[2]); |
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read32(0xbbe00010) = 0x2; |
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switch (port) { |
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case 0: |
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read32(base | 0x54) = ((test_mode << 16) | 0x3084); |
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break; |
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case 1: |
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read32(base | 0x58) = ((test_mode << 16) | 0x3084); |
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break; |
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case 2: |
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read32(base | 0x5c) = ((test_mode << 16) | 0x3084); |
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break; |
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case 3: |
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read32(base | 0x60) = ((test_mode << 16) | 0x3084); |
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break; |
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case 4: |
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read32(base | 0x64) = ((test_mode << 16) | 0x3084); |
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break; |
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case 5: |
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read32(base | 0x68) = ((test_mode << 16) | 0x3084); |
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break; |
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default: |
|||
printf("the port number is error!\n"); |
|||
break; |
|||
} |
|||
|
|||
if (test_mode == 5) |
|||
read8(0xbBe00010) = 0x1; |
|||
|
|||
return(1); |
|||
} |
|||
|
|||
cmd_satatest(ac, av) |
|||
int ac; |
|||
char *av[]; |
|||
{ |
|||
|
|||
unsigned int port, gen; |
|||
unsigned int base; |
|||
int test_mode; |
|||
if (ac != 4){ |
|||
printf("Usage:satatest <port > <gen> <test_mode>\n"); |
|||
printf("port0: 0\n"); |
|||
printf("port1: 1\n"); |
|||
printf("gen1: 1\n"); |
|||
printf("gen2: 2\n"); |
|||
printf("test_mode: 0x0 SSOP( Simultaneous switching outputs pattern)\n"); |
|||
printf("test_mode: 0x1 HTDP( High transition density pattern) \n"); |
|||
printf("test_mode: 0x2 LTDP( Low transition density pattern) \n"); |
|||
printf("test_mode: 0x3 LFSCP( Low frequency spectral component pattern)\n"); |
|||
printf("test_mode: 0x4 COMP( Composite pattern) \n"); |
|||
printf("test_mode: 0x5 LBP( Lone bit pattern) \n"); |
|||
printf("test_mode: 0x6 MFTP( Mid frequency test pattern)\n"); |
|||
printf("test_mode: 0x7 HFTP( High frequency test pattern)\n"); |
|||
printf("test_mode: 0x8 LFTP( Low frequency test pattern)\n"); |
|||
|
|||
return 0; |
|||
} |
|||
|
|||
port = atoi(av[1]); |
|||
gen = atoi(av[2]); |
|||
test_mode = atoi(av[3]); |
|||
|
|||
base = (0xbbe38000 + port * 0x100); |
|||
// printf(" -> 0x%x\n", (gen == 1 ? 0x0 : 0x9));
|
|||
if (gen == 1) |
|||
read8(base | 0x12) = 0x0; |
|||
else if (gen == 2) |
|||
read8(base | 0x12) = 0x9; |
|||
|
|||
read8(base | 0x10) = 0x1; |
|||
read32(0xbbe300f4) = port * 0x10000; |
|||
read32(0xbbe300a4) = (0x10000 | test_mode); |
|||
|
|||
return(1); |
|||
|
|||
} |
|||
|
|||
unsigned char |
|||
cmd_pcietest(ac, av) |
|||
int ac; |
|||
char *av[]; |
|||
{ |
|||
unsigned int port, gen; |
|||
unsigned int base,test_mode; |
|||
unsigned int pcie_clock_source; |
|||
|
|||
if (ac < 2){ |
|||
|
|||
printf("if test gen1:pcietest <gen1>\n"); |
|||
printf("if test gen2:pcietest <gen2> <gen2_test_mode> \n"); |
|||
printf("gen1: 1\n"); |
|||
printf("gen2: 2\n"); |
|||
printf("gen2_test_mode: 1 ->0xf052, -3.5db De-emphasis \n"); |
|||
printf("gen2_test_mode: 2 ->0xf012, -6db De-emphasis \n"); |
|||
printf("gen2_test_mode: 3 ->0xf452, -3.5db De-emphasis, modified compliance \n"); |
|||
printf("gen2_test_mode: 4 ->0xf412, -6db De-emphasis, modified compliance \n"); |
|||
printf("gen2_test_mode: 5 ->0xfc12, -6db De-emphasis, modified compliance, compliance \n"); |
|||
printf("gen2_test_mode: 6 ->0xfc52, -3.5db De-emphasis, modified compliance, compliance SOS \n"); |
|||
printf("For example:pcietest 2 1 \n"); |
|||
return 0; |
|||
} |
|||
gen = atoi(av[1]); |
|||
if (gen == 2) { |
|||
test_mode = atoi(av[2]); |
|||
read32(0xb811407c) = 0x533c42;// the low 4 bit must be 2.
|
|||
} |
|||
|
|||
base = 0xb8110000; |
|||
read32(base | 0x480c) = 0x2040f; |
|||
for (port = 0;port < 4;port++) { |
|||
read8(base | (port * 0x100) | 0x11) = 0x21; |
|||
read8(base | (port * 0x100) | 0x10) = 0xb; |
|||
} |
|||
|
|||
if (gen == 2) { |
|||
for (port = 0;port < 4;port++) |
|||
read8(base | (port * 0x100) | 0x12) = 0xa; |
|||
} |
|||
|
|||
read32(base | 0x8000) = 0xff204c; |
|||
if (gen == 0x1) { |
|||
read32(base | 0x40a0) = 0xfc51; |
|||
} else if (gen == 0x2){ |
|||
switch (test_mode) { |
|||
case 1: |
|||
read32(base | 0x40a0) = 0xf052; |
|||
break; |
|||
case 2: |
|||
read32(base | 0x40a0) = 0xf012; |
|||
break; |
|||
case 3: |
|||
read32(base | 0x40a0) = 0xf452; |
|||
break; |
|||
case 4: |
|||
read32(base | 0x40a0) = 0xf412; |
|||
break; |
|||
case 5: |
|||
read32(base | 0x40a0) = 0xfc52; |
|||
break; |
|||
case 6: |
|||
read32(base | 0x40a0) = 0xfc12; |
|||
break; |
|||
default: |
|||
printf("The test mode is error!\n"); |
|||
break; |
|||
} |
|||
printf("test_mode = 0x%lx\n",test_mode); |
|||
} |
|||
|
|||
read32(base | 0x4708) = 0x7028004; |
|||
|
|||
return(1); |
|||
} |
|||
|
|||
#define u64 unsigned long |
|||
#define u32 unsigned int |
|||
#define u16 unsigned short |
|||
#define u8 unsigned char |
|||
#define GMAC0_MAC_REG_ADDR 0xffffffffbbe10000 |
|||
#define GMAC0_DMA_REG_ADDR 0xffffffffbbe11000 |
|||
#define GMAC1_MAC_REG_ADDR 0xffffffffbbe18000 |
|||
#define GMAC1_DMA_REG_ADDR 0xffffffffbbe19000 |
|||
|
|||
#define PHY_REG20 20 |
|||
#define PHY_REG0 0 |
|||
#define PHY_REG16 16 |
|||
#define PHY_LOOPBACK (1 << 14) |
|||
#define PHY_SPEED0 (1 << 13) |
|||
#define PHY_DUMPLEX_FULL (1 << 8) |
|||
#define PHY_SPEED1 (1 << 6) |
|||
#define PHY_MODE_100M (PHY_SPEED0 & ~PHY_SPEED1) |
|||
|
|||
static u32 gmac_read(u64 base, u32 reg) |
|||
{ |
|||
u64 addr; |
|||
u32 data; |
|||
|
|||
addr = base + (u64)reg; |
|||
data = ls_readl(addr); |
|||
return data; |
|||
} |
|||
|
|||
static void gmac_write(u64 base, u32 reg, u32 data) |
|||
{ |
|||
u64 addr; |
|||
|
|||
addr = base + (u64)reg; |
|||
ls_readl(addr) = data; |
|||
return; |
|||
} |
|||
|
|||
static signed int gmac_phy_read(u64 base,u32 PhyBase, u32 reg, u16 * data ) |
|||
{ |
|||
u32 addr; |
|||
u32 loop_variable; |
|||
addr = ((PhyBase << GmiiDevShift) & GmiiDevMask) | ((reg << GmiiRegShift) & GmiiRegMask) | GmiiCsrClk3; |
|||
addr = addr | GmiiBusy ; |
|||
|
|||
gmac_write(base,GmacGmiiAddr,addr); |
|||
|
|||
for(loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++){ |
|||
if (!(gmac_read(base,GmacGmiiAddr) & GmiiBusy)){ |
|||
break; |
|||
} |
|||
int i = DEFAULT_DELAY_VARIABLE; |
|||
while (i--); |
|||
} |
|||
if(loop_variable < DEFAULT_LOOP_VARIABLE) |
|||
* data = (u16)(gmac_read(base,GmacGmiiData) & 0xFFFF); |
|||
else{ |
|||
tgt_printf("\rError::: PHY not responding Busy bit didnot get cleared !!!!!!\n"); |
|||
return -ESYNOPGMACPHYERR; |
|||
} |
|||
|
|||
return -ESYNOPGMACNOERR; |
|||
} |
|||
|
|||
static signed int gmac_phy_write(u64 base, u32 PhyBase, u32 reg, u16 data) |
|||
{ |
|||
u32 addr; |
|||
u32 loop_variable; |
|||
gmac_write(base,GmacGmiiData,data); |
|||
|
|||
addr = ((PhyBase << GmiiDevShift) & GmiiDevMask) | ((reg << GmiiRegShift) & GmiiRegMask) | GmiiWrite | GmiiCsrClk3; |
|||
|
|||
addr = addr | GmiiBusy ; |
|||
gmac_write(base,GmacGmiiAddr,addr); |
|||
for(loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++){ |
|||
if (!(gmac_read(base,GmacGmiiAddr) & GmiiBusy)){ |
|||
break; |
|||
} |
|||
int i = DEFAULT_DELAY_VARIABLE; |
|||
while (i--); |
|||
} |
|||
|
|||
if(loop_variable < DEFAULT_LOOP_VARIABLE){ |
|||
return -ESYNOPGMACNOERR; |
|||
} |
|||
else{ |
|||
tgt_printf("\rError::: PHY not responding Busy bit didnot get cleared !!!!!!\n"); |
|||
return -ESYNOPGMACPHYERR; |
|||
} |
|||
} |
|||
|
|||
unsigned char |
|||
cmd_lantest(ac, av) |
|||
int ac; |
|||
char *av[]; |
|||
{ |
|||
unsigned int base,test_mode,id; |
|||
unsigned short data; |
|||
u64 mac_base; |
|||
if (ac < 2){ |
|||
printf("lantest: lantest <testmode>\n"); |
|||
printf("testmode1: 1\n"); |
|||
printf("testmode2: 2\n"); |
|||
printf("testmode3: 3\n"); |
|||
printf("testmode4: 4\n"); |
|||
printf("For example:lantest 1 \n"); |
|||
return 0; |
|||
} |
|||
test_mode = atoi(av[1]); |
|||
|
|||
for (id = 0;id < 2;id++) { |
|||
if (id == 0) |
|||
mac_base = GMAC0_MAC_REG_ADDR; |
|||
else if (id == 1) |
|||
mac_base = GMAC1_MAC_REG_ADDR; |
|||
|
|||
switch (test_mode) { |
|||
case 1: |
|||
gmac_phy_read(mac_base,16,9,&data); |
|||
printf("phy 9 register value = 0x%lx\n",data); |
|||
gmac_phy_read(mac_base,16,10,&data); |
|||
printf("phy 10 register value = 0x%lx\n",data); |
|||
gmac_phy_write(mac_base,16,9,(1 << 13)); |
|||
gmac_phy_read(mac_base,16,9,&data); |
|||
printf("changed phy 9 register value = 0x%lx\n",data); |
|||
gmac_phy_read(mac_base,16,10,&data); |
|||
printf("changed phy 10 register value = 0x%lx\n",data); |
|||
break; |
|||
case 2: |
|||
gmac_phy_read(mac_base,16,9,&data); |
|||
printf("phy 9 register value = 0x%lx\n",data); |
|||
gmac_phy_read(mac_base,16,10,&data); |
|||
printf("phy 10 register value = 0x%lx\n",data); |
|||
gmac_phy_write(mac_base,16,9, (0x2 << 13)); |
|||
gmac_phy_read(mac_base,16,9,&data); |
|||
printf("changed phy 9 register value = 0x%lx\n",data); |
|||
gmac_phy_read(mac_base,16,10,&data); |
|||
printf("changed phy 10 register value = 0x%lx\n",data); |
|||
break; |
|||
case 3: |
|||
gmac_phy_read(mac_base,16,9,&data); |
|||
printf("phy 9 register value = 0x%lx\n",data); |
|||
gmac_phy_read(mac_base,16,10,&data); |
|||
printf("phy 10 register value = 0x%lx\n",data); |
|||
gmac_phy_write(mac_base,16,9,(0x3 << 13)); |
|||
gmac_phy_read(mac_base,16,9,&data); |
|||
printf("changed phy 9 register value = 0x%lx\n",data); |
|||
gmac_phy_read(mac_base,16,10,&data); |
|||
printf("changed phy 10 register value = 0x%lx\n",data); |
|||
break; |
|||
case 4: |
|||
gmac_phy_read(mac_base,16,9,&data); |
|||
printf("phy 9 register value = 0x%lx\n",data); |
|||
gmac_phy_read(mac_base,16,10,&data); |
|||
printf("phy 10 register value = 0x%lx\n",data); |
|||
gmac_phy_write(mac_base,16,9, (0x4 << 13)); |
|||
gmac_phy_read(mac_base,16,9,&data); |
|||
printf("changed phy 9 register value = 0x%lx\n",data); |
|||
gmac_phy_read(mac_base,16,10,&data); |
|||
printf("changed phy 10 register value = 0x%lx\n",data); |
|||
break; |
|||
default: |
|||
printf("Test mode is error!\n"); |
|||
break; |
|||
} |
|||
} |
|||
|
|||
return(1); |
|||
} |
|||
int gmac_w18(void) |
|||
{ |
|||
unsigned char offset; |
|||
unsigned char id; |
|||
unsigned long long mac_base; |
|||
unsigned short data; |
|||
for (id = 0;id < 2;id++) { |
|||
if (id == 0) { |
|||
mac_base = GMAC0_MAC_REG_ADDR; |
|||
} else if (id == 1){ |
|||
mac_base = GMAC1_MAC_REG_ADDR; |
|||
} |
|||
/*
|
|||
gmac_phy_read(mac_base,16,16,&data); |
|||
data |= 0x300; |
|||
gmac_phy_write(mac_base,16,16,data); |
|||
gmac_phy_read(mac_base,16,16,&data); |
|||
*/ |
|||
gmac_phy_read(mac_base,16,19,&data); |
|||
data = 0x10; |
|||
gmac_phy_write(mac_base,16,18,data); |
|||
gmac_phy_read(mac_base,16,18,&data); |
|||
|
|||
gmac_phy_read(mac_base,16,19,&data); |
|||
|
|||
gmac_phy_read(mac_base,16,24,&data); |
|||
data = data | 0x800; |
|||
gmac_phy_write(mac_base,16,24,data); |
|||
|
|||
gmac_phy_read(mac_base,16,27,&data); |
|||
data = data & (~(1 << 10)); |
|||
gmac_phy_write(mac_base,16,27,data); |
|||
|
|||
gmac_phy_read(mac_base,16,0,&data); |
|||
data = data | 0x8000; |
|||
gmac_phy_write(mac_base,16,0,data); |
|||
} |
|||
return 0; |
|||
} |
|||
int gmac_w(ac, av) |
|||
int ac; |
|||
char *av[]; |
|||
{ |
|||
unsigned char offset; |
|||
unsigned char id; |
|||
unsigned long long mac_base; |
|||
unsigned short data; |
|||
if (ac == 3) { |
|||
data = 0x1e1; |
|||
printf("data 0x%lx\n",data); |
|||
for (id = 0;id < 2;id++) { |
|||
if (id == 0) { |
|||
mac_base = GMAC0_MAC_REG_ADDR; |
|||
gmac_phy_write(mac_base,16,4,data); |
|||
gmac_phy_read(mac_base,16,4,&data); |
|||
printf("gmac0 4 0x%lx\n",data); |
|||
gmac_phy_read(mac_base,16,0x00,&data); |
|||
gmac_phy_write(mac_base,16,0x00,data); |
|||
} else if (id == 1){ |
|||
data = 0xffff; |
|||
mac_base = GMAC1_MAC_REG_ADDR; |
|||
gmac_phy_write(mac_base,16,4,data); |
|||
gmac_phy_read(mac_base,16,4,&data); |
|||
printf("gmac1 4 0x%lx\n",data); |
|||
gmac_phy_read(mac_base,16,0x00,&data); |
|||
data = data | 0x8000; |
|||
gmac_phy_write(mac_base,16,0x00,data); |
|||
} |
|||
|
|||
} |
|||
} |
|||
if (ac == 1) { |
|||
printf("data 0x%lx\n",data); |
|||
for (id = 0;id < 2;id++) { |
|||
if (id == 0) { |
|||
data = 0x10; |
|||
mac_base = GMAC0_MAC_REG_ADDR; |
|||
gmac_phy_write(mac_base,16,18,data); |
|||
gmac_phy_read(mac_base,16,18,&data); |
|||
printf("gmac0 4 0x%lx\n",data); |
|||
gmac_phy_read(mac_base,16,0,&data); |
|||
data = data | 0x8000; |
|||
gmac_phy_write(mac_base,16,0,data); |
|||
} else if (id == 1){ |
|||
data = 0x10; |
|||
mac_base = GMAC1_MAC_REG_ADDR; |
|||
gmac_phy_write(mac_base,16,18,data); |
|||
gmac_phy_read(mac_base,16,18,&data); |
|||
printf("gmac1 4 0x%lx\n",data); |
|||
gmac_phy_read(mac_base,16,0,&data); |
|||
data = data | 0x8000; |
|||
gmac_phy_write(mac_base,16,0,data); |
|||
} |
|||
|
|||
} |
|||
} |
|||
if (ac == 2) { |
|||
for (id = 0;id < 2;id++) { |
|||
if (id == 0) |
|||
mac_base = GMAC0_MAC_REG_ADDR; |
|||
else if (id == 1) |
|||
mac_base = GMAC1_MAC_REG_ADDR; |
|||
|
|||
data = 0x40; |
|||
gmac_phy_write(mac_base,16,18,data); |
|||
gmac_phy_read(mac_base,16,0x00,&data); |
|||
data = data | 0x8000; |
|||
gmac_phy_write(mac_base,16,0x00,data); |
|||
} |
|||
} |
|||
return 0; |
|||
} |
|||
int gmacphy_write(ac, av) |
|||
int ac; |
|||
char *av[]; |
|||
{ |
|||
unsigned char offset; |
|||
if (ac != 3) { |
|||
printf("the parameters is error!\n"); |
|||
printf("gmacphy_write <offset> <data>\n"); |
|||
return -1; |
|||
} |
|||
|
|||
offset = atoi(av[1]); |
|||
|
|||
unsigned char id; |
|||
unsigned long long mac_base; |
|||
unsigned short data; |
|||
data = atoi(av[2]); |
|||
printf("data 0x%lx\n",data); |
|||
for (id = 0;id < 2;id++) { |
|||
if (id == 0) |
|||
mac_base = GMAC0_MAC_REG_ADDR; |
|||
else if (id == 1) |
|||
mac_base = GMAC1_MAC_REG_ADDR; |
|||
|
|||
gmac_phy_write(mac_base,16,offset,data); |
|||
} |
|||
return 0; |
|||
} |
|||
int gmacphy_read(ac, av) |
|||
int ac; |
|||
char *av[]; |
|||
{ |
|||
unsigned char offset; |
|||
unsigned char id; |
|||
unsigned long long mac_base; |
|||
unsigned short data; |
|||
if (ac == 1) { |
|||
for (id = 0;id < 2;id++) { |
|||
if (id == 0) |
|||
mac_base = GMAC0_MAC_REG_ADDR; |
|||
else if (id == 1) |
|||
mac_base = GMAC1_MAC_REG_ADDR; |
|||
|
|||
for (offset = 0;offset < 32;offset++) { |
|||
gmac_phy_read(mac_base,16,offset,&data); |
|||
printf("gmac%d reg(%d) %lx\n",id,offset,data); |
|||
} |
|||
} |
|||
|
|||
return -1; |
|||
} |
|||
|
|||
offset = atoi(av[1]); |
|||
|
|||
for (id = 0;id < 2;id++) { |
|||
if (id == 0) |
|||
mac_base = GMAC0_MAC_REG_ADDR; |
|||
else if (id == 1) |
|||
mac_base = GMAC1_MAC_REG_ADDR; |
|||
|
|||
gmac_phy_read(mac_base,16,offset,&data); |
|||
printf("gmac%d reg(%d) %lx\n",id,offset,data); |
|||
} |
|||
return 0; |
|||
} |
|||
/*
|
|||
* |
|||
* Command table registration |
|||
* ========================== |
|||
*/ |
|||
|
|||
static const Cmd Cmds[] = |
|||
{ |
|||
{"Misc"}, |
|||
{"usbtest", "", 0, "3a2h usbtest : usbtest ", cmd_usbtest, 1, 99, 0}, |
|||
{"gmacphy_read", "", 0, "read gmac phy reg", gmacphy_read, 1, 99, 0}, |
|||
{"gmacphy_write", "", 0, "read gmac phy reg", gmacphy_write, 1, 99, 0}, |
|||
{"gmac_w", "", 0, "read gmac phy reg", gmac_w, 1, 99, 0}, |
|||
{"lantest", "", 0, "3a2h lantest : lantest ", cmd_lantest, 1, 99, 0}, |
|||
{"pcietest", "", 0, "3a2h pcietest: pcietest ", cmd_pcietest, 1, 99, 0}, |
|||
{"satatest", "", 0, "3a2h satatest: satatest ", cmd_satatest, 1, 99, 0}, |
|||
{0, 0} |
|||
}; |
|||
|
|||
static void init_cmd __P((void)) __attribute__ ((constructor)); |
|||
|
|||
void |
|||
init_cmd() |
|||
{ |
|||
cmdlist_expand(Cmds, 1); |
|||
} |
|||
Loading…
Reference in new issue