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Fix PCIE device found fail problem by correct the PHY cfg code. 

Change-Id: Id5add3f844d171beda181cd88f51acbfcc86f342
master
Chen Xinke 7 years ago
committed by zhangbaoqi
parent
e726734c54
commit
2f75caf73e
4 changed files with 356 additions and 224 deletions
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  1. 2
      Targets/Bonito3a3000_7a/Bonito/start.S
  2. 56
      pmon/arch/mips/ls7a/ls7a_config.S
  3. 4
      pmon/arch/mips/ls7a/ls7a_dbg.S
  4. 518
      pmon/arch/mips/ls7a/ls7a_init.S

2
Targets/Bonito3a3000_7a/Bonito/start.S
View File

@ -1497,7 +1497,7 @@ idle1000:
#######################################
#include "ls3a7a_setup_ht_link.S"
#include "ls3a7a_ht_init.S"
#include "../../../pmon/arch/mips/ls7a/ls7a_config_one_pll.S"
#include "../../../pmon/arch/mips/ls7a/ls7a_config.S"
#include "ddr_dir/ls3A8_ddr_config.S"
#ifdef LS7A_GMEM_CFG
#include "ddr_dir/ls7A_gmem_config.S"

56
pmon/arch/mips/ls7a/ls7a_config_one_pll.S → pmon/arch/mips/ls7a/ls7a_config.S
View File

@ -1,5 +1,5 @@
//func: ls7a_config_one_pll
//func: subroutine for LS7A related ops
//author: Chen Xinke
//date: 2017.8.17
@ -82,3 +82,57 @@ ls7a_config_one_pll:
jr ra
nop
.end ls7a_config_one_pll
.global ls7a_phy_cfg_write
.ent ls7a_phy_cfg_write
.set noreorder
.set mips3
ls7a_phy_cfg_write:
//a0: confreg address
//a1: [phy_cfg_data, phy_cfg_addr]
//wait cfg ready first
1:
lw v0, 0x4(a0)
and v0, v0, 0x4
beqz v0, 1b
nop
sw a1, 0x0(a0)
li v0, 0x1
sw v0, 0x4(a0)
jr ra
nop
.end ls7a_phy_cfg_write
.global ls7a_phy_cfg_read
.ent ls7a_phy_cfg_read
.set noreorder
.set mips3
ls7a_phy_cfg_read:
//a0: confreg address
//a1: [phy_cfg_addr]
//wait cfg ready first
1:
lw v0, 0x4(a0)
and v0, v0, 0x4
beqz v0, 1b
nop
sw a1, 0x0(a0)
sw $0, 0x4(a0)
//wait read data ready
1:
lw v0, 0x4(a0)
and v0, v0, 0x4
beqz v0, 1b
nop
lw v0, 0x0(a0)
jr ra
nop
.end ls7a_phy_cfg_read

4
pmon/arch/mips/ls7a/ls7a_dbg.S
View File

@ -14,10 +14,10 @@
PRINTSTR("local cache compare fail!\r\n")
daddu t4, t4, 1
1:
PRINTSTR("Read node0 7A times: 0x100000 ..\r\n")
PRINTSTR("Read node0 7A times: 0x10000 ..\r\n")
dli t1, 0x90000e000f000000
dli t7, 0x100000
dli t7, 0x10000
2:
ld a1, 0x0(t1)
beq t6, a1, 1f

518
pmon/arch/mips/ls7a/ls7a_init.S
View File

@ -26,7 +26,7 @@
#endif
TTYDBG("config 7A dma route done.\r\n")
#if 0 //ndef LS7A_2WAY_CONNECT
#ifndef LS7A_2WAY_CONNECT
//shut down LS7A HT Hi
lw t1, CONF_HT_CLKEN_OFFSET(t0)
li t2, (0x1 << 1)
@ -266,9 +266,9 @@
sw t1, CONF_NB_OFFSET(t0)
//delay a while
li t1, 0x1000
dli t1, 0x4000000
1:
subu t1, t1, 1
dsubu t1, t1, 1
bnez t1, 1b
nop
@ -309,6 +309,13 @@
not t2, t2
and t1, t1, t2
sw t1, CONF_NB_OFFSET(t0)
//delay a while
dli t1, 0x4000000
1:
dsubu t1, t1, 1
bnez t1, 1b
nop
#endif
//enable access
@ -319,315 +326,380 @@
TTYDBG("PCIE enabled\r\n")
#if (!(LS7A_PCIE_F0_P0_DISABLE && LS7A_PCIE_F0_P1_DISABLE && LS7A_PCIE_F0_P2_DISABLE && LS7A_PCIE_F0_P3_DISABLE))
dli t1, 0x1403f1002
sd t1, 0x590(t0)
dli t1, 0x1403f1102
sd t1, 0x590(t0)
dli t1, 0x1403f1202
sd t1, 0x590(t0)
dli t1, 0x1403f1302
sd t1, 0x590(t0)
//DO not destroy a0, a1, for example, do not add print between these code
daddu a0, t0, 0x590
li a1, 0x403f1002
bal ls7a_phy_cfg_write
nop
addu a1, a1, 0x100
bal ls7a_phy_cfg_write
nop
addu a1, a1, 0x100
bal ls7a_phy_cfg_write
nop
addu a1, a1, 0x100
bal ls7a_phy_cfg_write
nop
#endif
#if (!(LS7A_PCIE_F1_P0_DISABLE && LS7A_PCIE_F1_P1_DISABLE))
dli t1, 0x1403f1002
sd t1, 0x5b0(t0)
dli t1, 0x1403f1102
sd t1, 0x5b0(t0)
dli t1, 0x1403f1202
sd t1, 0x5b0(t0)
dli t1, 0x1403f1302
sd t1, 0x5b0(t0)
daddu a0, t0, 0x5b0
li a1, 0x403f1002
bal ls7a_phy_cfg_write
nop
addu a1, a1, 0x100
bal ls7a_phy_cfg_write
nop
addu a1, a1, 0x100
bal ls7a_phy_cfg_write
nop
addu a1, a1, 0x100
bal ls7a_phy_cfg_write
nop
#endif
#if (!(LS7A_PCIE_G0_P0_DISABLE && LS7A_PCIE_G0_P1_DISABLE))
dli t1, 0x1403f1002
sd t1, 0x5d0(t0)
dli t1, 0x1403f1102
sd t1, 0x5d0(t0)
dli t1, 0x1403f1202
sd t1, 0x5d0(t0)
dli t1, 0x1403f1302
sd t1, 0x5d0(t0)
dli t1, 0x1403f1002
sd t1, 0x5d8(t0)
dli t1, 0x1403f1102
sd t1, 0x5d8(t0)
dli t1, 0x1403f1202
sd t1, 0x5d8(t0)
dli t1, 0x1403f1302
sd t1, 0x5d8(t0)
daddu a0, t0, 0x5d0
li a1, 0x403f1002
bal ls7a_phy_cfg_write
nop
addu a1, a1, 0x100
bal ls7a_phy_cfg_write
nop
addu a1, a1, 0x100
bal ls7a_phy_cfg_write
nop
addu a1, a1, 0x100
bal ls7a_phy_cfg_write
nop
daddu a0, t0, 0x5d8
li a1, 0x403f1002
bal ls7a_phy_cfg_write
nop
addu a1, a1, 0x100
bal ls7a_phy_cfg_write
nop
addu a1, a1, 0x100
bal ls7a_phy_cfg_write
nop
addu a1, a1, 0x100
bal ls7a_phy_cfg_write
nop
#endif
#if (!(LS7A_PCIE_G1_P0_DISABLE && LS7A_PCIE_G1_P1_DISABLE))
dli t1, 0x1403f1002
sd t1, 0x5f0(t0)
dli t1, 0x1403f1102
sd t1, 0x5f0(t0)
dli t1, 0x1403f1202
sd t1, 0x5f0(t0)
dli t1, 0x1403f1302
sd t1, 0x5f0(t0)
dli t1, 0x1403f1002
sd t1, 0x5f8(t0)
dli t1, 0x1403f1102
sd t1, 0x5f8(t0)
dli t1, 0x1403f1202
sd t1, 0x5f8(t0)
dli t1, 0x1403f1302
sd t1, 0x5f8(t0)
daddu a0, t0, 0x5f0
li a1, 0x403f1002
bal ls7a_phy_cfg_write
nop
addu a1, a1, 0x100
bal ls7a_phy_cfg_write
nop
addu a1, a1, 0x100
bal ls7a_phy_cfg_write
nop
addu a1, a1, 0x100
bal ls7a_phy_cfg_write
nop
daddu a0, t0, 0x5f8
li a1, 0x403f1002
bal ls7a_phy_cfg_write
nop
addu a1, a1, 0x100
bal ls7a_phy_cfg_write
nop
addu a1, a1, 0x100
bal ls7a_phy_cfg_write
nop
addu a1, a1, 0x100
bal ls7a_phy_cfg_write
nop
#endif
#if (!(LS7A_PCIE_H_P0_DISABLE && LS7A_PCIE_H_P1_DISABLE))
dli t1, 0x1403f1002
sd t1, 0x610(t0)
dli t1, 0x1403f1102
sd t1, 0x610(t0)
dli t1, 0x1403f1202
sd t1, 0x610(t0)
dli t1, 0x1403f1302
sd t1, 0x610(t0)
dli t1, 0x1403f1002
sd t1, 0x618(t0)
dli t1, 0x1403f1102
sd t1, 0x618(t0)
dli t1, 0x1403f1202
sd t1, 0x618(t0)
dli t1, 0x1403f1302
sd t1, 0x618(t0)
daddu a0, t0, 0x610
li a1, 0x403f1002
bal ls7a_phy_cfg_write
nop
addu a1, a1, 0x100
bal ls7a_phy_cfg_write
nop
addu a1, a1, 0x100
bal ls7a_phy_cfg_write
nop
addu a1, a1, 0x100
bal ls7a_phy_cfg_write
nop
daddu a0, t0, 0x618
li a1, 0x403f1002
bal ls7a_phy_cfg_write
nop
addu a1, a1, 0x100
bal ls7a_phy_cfg_write
nop
addu a1, a1, 0x100
bal ls7a_phy_cfg_write
nop
addu a1, a1, 0x100
bal ls7a_phy_cfg_write
nop
#endif
#define PCIE_GEN_CFG 0x1
#if (!LS7A_PCIE_F0_P0_DISABLE)
dli t0, 0x90000efe08004800
li t1, 0xfff9ffff
li a0, 0xfff9ffff
lw t2, 0xc(t0)
and t1, t1, t2
or t1, (PCIE_GEN_CFG << 17)
sw t1, 0xc(t0)
and a0, a0, t2
or a0, (PCIE_GEN_CFG << 17)
sw a0, 0xc(t0)
dli t0, 0x90000efe00004800
li t1, 0x60000000
sw t1, 0x10(t0)
dli t0, 0x90000e0000000000
li t1, 0x60000000
or t0, t0, t1
dli t1, 0xff204c
sw t1, 0x0(t0)
li a0, 0x60000000
sw a0, 0x10(t0)
dli t1, 0x90000e0000000000
li a0, 0x60000000
or t1, t1, a0
li a0, 0xff204c
sw a0, 0x0(t1)
sw $0, 0x10(t0)
#endif
#if (!LS7A_PCIE_F0_P1_DISABLE)
dli t0, 0x90000efe08005000
li t1, 0xfff9ffff
li a0, 0xfff9ffff
lw t2, 0xc(t0)
and t1, t1, t2
or t1, (PCIE_GEN_CFG << 17)
sw t1, 0xc(t0)
and a0, a0, t2
or a0, (PCIE_GEN_CFG << 17)
sw a0, 0xc(t0)
dli t0, 0x90000efe00005000
li t1, 0x60100000
sw t1, 0x10(t0)
dli t0, 0x90000e0000000000
li t1, 0x60100000
or t0, t0, t1
dli t1, 0xff204c
sw t1, 0x0(t0)
li a0, 0x60100000
sw a0, 0x10(t0)
dli t1, 0x90000e0000000000
li a0, 0x60100000
or t1, t1, a0
li a0, 0xff204c
sw a0, 0x0(t1)
sw $0, 0x10(t0)
#endif
#if (!LS7A_PCIE_F0_P2_DISABLE)
dli t0, 0x90000efe08005800
li t1, 0xfff9ffff
li a0, 0xfff9ffff
lw t2, 0xc(t0)
and t1, t1, t2
or t1, (PCIE_GEN_CFG << 17)
sw t1, 0xc(t0)
and a0, a0, t2
or a0, (PCIE_GEN_CFG << 17)
sw a0, 0xc(t0)
dli t0, 0x90000efe00005800
li t1, 0x60200000
sw t1, 0x10(t0)
dli t0, 0x90000e0000000000
li t1, 0x60200000
or t0, t0, t1
dli t1, 0xff204c
sw t1, 0x0(t0)
li a0, 0x60200000
sw a0, 0x10(t0)
dli t1, 0x90000e0000000000
li a0, 0x60200000
or t1, t1, a0
li a0, 0xff204c
sw a0, 0x0(t1)
sw $0, 0x10(t0)
#endif
#if (!LS7A_PCIE_F0_P3_DISABLE)
dli t0, 0x90000efe08006000
li t1, 0xfff9ffff
li a0, 0xfff9ffff
lw t2, 0xc(t0)
and t1, t1, t2
or t1, (PCIE_GEN_CFG << 17)
sw t1, 0xc(t0)
and a0, a0, t2
or a0, (PCIE_GEN_CFG << 17)
sw a0, 0xc(t0)
dli t0, 0x90000efe00006000
li t1, 0x60300000
sw t1, 0x10(t0)
dli t0, 0x90000e0000000000
li t1, 0x60300000
or t0, t0, t1
dli t1, 0xff204c
sw t1, 0x0(t0)
li a0, 0x60300000
sw a0, 0x10(t0)
dli t1, 0x90000e0000000000
li a0, 0x60300000
or t1, t1, a0
li a0, 0xff204c
sw a0, 0x0(t1)
sw $0, 0x10(t0)
#endif
#if (!LS7A_PCIE_F1_P0_DISABLE)
dli t0, 0x90000efe08006800
li t1, 0xfff9ffff
li a0, 0xfff9ffff
lw t2, 0xc(t0)
and t1, t1, t2
or t1, (PCIE_GEN_CFG << 17)
sw t1, 0xc(t0)
and a0, a0, t2
or a0, (PCIE_GEN_CFG << 17)
sw a0, 0xc(t0)
dli t0, 0x90000efe00006800
li t1, 0x61000000
sw t1, 0x10(t0)
dli t0, 0x90000e0000000000
li t1, 0x61000000
or t0, t0, t1
dli t1, 0xff204c
sw t1, 0x0(t0)
li a0, 0x61000000
sw a0, 0x10(t0)
dli t1, 0x90000e0000000000
li a0, 0x61000000
or t1, t1, a0
li a0, 0xff204c
sw a0, 0x0(t1)
sw $0, 0x10(t0)
#endif
#if (!LS7A_PCIE_F1_P1_DISABLE)
dli t0, 0x90000efe08007000
li t1, 0xfff9ffff
li a0, 0xfff9ffff
lw t2, 0xc(t0)
and t1, t1, t2
or t1, (PCIE_GEN_CFG << 17)
sw t1, 0xc(t0)
and a0, a0, t2
or a0, (PCIE_GEN_CFG << 17)
sw a0, 0xc(t0)
dli t0, 0x90000efe00007000
li t1, 0x61100000
sw t1, 0x10(t0)
dli t0, 0x90000e0000000000
li t1, 0x61100000
or t0, t0, t1
dli t1, 0xff204c
sw t1, 0x0(t0)
li a0, 0x61100000
sw a0, 0x10(t0)
dli t1, 0x90000e0000000000
li a0, 0x61100000
or t1, t1, a0
li a0, 0xff204c
sw a0, 0x0(t1)
sw $0, 0x10(t0)
#endif
#if (!LS7A_PCIE_G0_P0_DISABLE)
dli t0, 0x90000efe08007800
li t1, 0xfff9ffff
li a0, 0xfff9ffff
lw t2, 0xc(t0)
and t1, t1, t2
or t1, (PCIE_GEN_CFG << 17)
sw t1, 0xc(t0)
and a0, a0, t2
or a0, (PCIE_GEN_CFG << 17)
sw a0, 0xc(t0)
dli t0, 0x90000efe00007800
li t1, 0x62000000
sw t1, 0x10(t0)
dli t0, 0x90000e0000000000
li t1, 0x62000000
or t0, t0, t1
dli t1, 0xff204c
sw t1, 0x0(t0)
li a0, 0x62000000
sw a0, 0x10(t0)
dli t1, 0x90000e0000000000
li a0, 0x62000000
or t1, t1, a0
li a0, 0xff204c
sw a0, 0x0(t1)
sw $0, 0x10(t0)
#endif
#if (!LS7A_PCIE_G0_P1_DISABLE)
dli t0, 0x90000efe08008000
li t1, 0xfff9ffff
li a0, 0xfff9ffff
lw t2, 0xc(t0)
and t1, t1, t2
or t1, (PCIE_GEN_CFG << 17)
sw t1, 0xc(t0)
and a0, a0, t2
or a0, (PCIE_GEN_CFG << 17)
sw a0, 0xc(t0)
dli t0, 0x90000efe00008000
li t1, 0x62100000
sw t1, 0x10(t0)
dli t0, 0x90000e0000000000
li t1, 0x62100000
or t0, t0, t1
dli t1, 0xff204c
sw t1, 0x0(t0)
li a0, 0x62100000
sw a0, 0x10(t0)
dli t1, 0x90000e0000000000
li a0, 0x62100000
or t1, t1, a0
li a0, 0xff204c
sw a0, 0x0(t1)
sw $0, 0x10(t0)
#endif
#if (!LS7A_PCIE_G1_P0_DISABLE)
dli t0, 0x90000efe08008800
li t1, 0xfff9ffff
li a0, 0xfff9ffff
lw t2, 0xc(t0)
and t1, t1, t2
or t1, (PCIE_GEN_CFG << 17)
sw t1, 0xc(t0)
and a0, a0, t2
or a0, (PCIE_GEN_CFG << 17)
sw a0, 0xc(t0)
dli t0, 0x90000efe00008800
li t1, 0x63000000
sw t1, 0x10(t0)
dli t0, 0x90000e0000000000
li t1, 0x63000000
or t0, t0, t1
dli t1, 0xff204c
sw t1, 0x0(t0)
li a0, 0x63000000
sw a0, 0x10(t0)
dli t1, 0x90000e0000000000
li a0, 0x63000000
or t1, t1, a0
li a0, 0xff204c
sw a0, 0x0(t1)
sw $0, 0x10(t0)
#endif
#if (!LS7A_PCIE_G1_P1_DISABLE)
dli t0, 0x90000efe08009000
li t1, 0xfff9ffff
li a0, 0xfff9ffff
lw t2, 0xc(t0)
and t1, t1, t2
or t1, (PCIE_GEN_CFG << 17)
sw t1, 0xc(t0)
and a0, a0, t2
or a0, (PCIE_GEN_CFG << 17)
sw a0, 0xc(t0)
dli t0, 0x90000efe00009000
li t1, 0x63100000
sw t1, 0x10(t0)
dli t0, 0x90000e0000000000
li t1, 0x63100000
or t0, t0, t1
dli t1, 0xff204c
sw t1, 0x0(t0)
li a0, 0x63100000
sw a0, 0x10(t0)
dli t1, 0x90000e0000000000
li a0, 0x63100000
or t1, t1, a0
li a0, 0xff204c
sw a0, 0x0(t1)
sw $0, 0x10(t0)
#endif
#if (!LS7A_PCIE_H_P0_DISABLE)
dli t0, 0x90000efe08009800
li t1, 0xfff9ffff
li a0, 0xfff9ffff
lw t2, 0xc(t0)
and t1, t1, t2
or t1, (PCIE_GEN_CFG << 17)
sw t1, 0xc(t0)
and a0, a0, t2
or a0, (PCIE_GEN_CFG << 17)
sw a0, 0xc(t0)
dli t0, 0x90000efe00009800
li t1, 0x64000000
sw t1, 0x10(t0)
dli t0, 0x90000e0000000000
li t1, 0x64000000
or t0, t0, t1
dli t1, 0xff204c
sw t1, 0x0(t0)
li a0, 0x64000000
sw a0, 0x10(t0)
dli t1, 0x90000e0000000000
li a0, 0x64000000
or t1, t1, a0
li a0, 0xff204c
sw a0, 0x0(t1)
sw $0, 0x10(t0)
#endif
#if (!LS7A_PCIE_H_P1_DISABLE)
dli t0, 0x90000efe0800a000
li t1, 0xfff9ffff
li a0, 0xfff9ffff
lw t2, 0xc(t0)
and t1, t1, t2
or t1, (PCIE_GEN_CFG << 17)
sw t1, 0xc(t0)
and a0, a0, t2
or a0, (PCIE_GEN_CFG << 17)
sw a0, 0xc(t0)
dli t0, 0x90000efe0000a000
li t1, 0x64100000
sw t1, 0x10(t0)
dli t0, 0x90000e0000000000
li t1, 0x64100000
or t0, t0, t1
dli t1, 0xff204c
sw t1, 0x0(t0)
li a0, 0x64100000
sw a0, 0x10(t0)
dli t1, 0x90000e0000000000
li a0, 0x64100000
or t1, t1, a0
li a0, 0xff204c
sw a0, 0x0(t1)
sw $0, 0x10(t0)
#endif
//disable clock of unused PCIE ports
@ -697,8 +769,10 @@
sw t1, (CONF_SB_OFFSET+4)(t0)
//configure phy
dli t1, 0x1403f1002
sd t1, 0x748(t0)
daddu a0, t0, 0x748
li a1, 0x403f1002
bal ls7a_phy_cfg_write
nop
TTYDBG("SATA0 enabled\r\n")
#else
//disable clock
@ -766,8 +840,10 @@
sw t1, (CONF_SB_OFFSET+4)(t0)
//configure phy
dli t1, 0x1403f1002
sd t1, 0x758(t0)
daddu a0, t0, 0x758
li a1, 0x403f1002
bal ls7a_phy_cfg_write
nop
TTYDBG("SATA1 enabled\r\n")
#else
//disable clock
@ -835,8 +911,10 @@
sw t1, (CONF_SB_OFFSET+4)(t0)
//configure phy
dli t1, 0x1403f1002
sd t1, 0x768(t0)
daddu a0, t0, 0x768
li a1, 0x403f1002
bal ls7a_phy_cfg_write
nop
TTYDBG("SATA2 enabled\r\n")
#else
//disable clock

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