diff --git a/Targets/Bonito3a84w/Bonito/loongson3_fixup.S b/Targets/Bonito3a84w/Bonito/loongson3_fixup.S
index 59305d2d..a7eef297 100644
--- a/Targets/Bonito3a84w/Bonito/loongson3_fixup.S
+++ b/Targets/Bonito3a84w/Bonito/loongson3_fixup.S
@@ -6,12 +6,7 @@ ATTENTION: NO 16BIT mode when using HT1
 
 */
 #define HT0_RECONNECT
-//#define INTERCONNECTION_HT1 //USE HT1.0 on Ring
-#define INTERCONNECTION_X_HT1 //USE HT1.0 on X
-#define X_HT1_800M
-#define USE_HT_RESET //Only in HT3 mode
-#define RESET_AGAIN_WHEN_FAIL
-//#define HT0_16BIT //NO 16Bit mode in 4 chip interconnection
+//#define INTERCONNECTION_HT0_1_0 //USE HT1.0 on Ring
 //#define HT0_3200M
 //#define HT0_2400M
 //#define HT0_2200M
@@ -19,7 +14,16 @@ ATTENTION: NO 16BIT mode when using HT1
 //#define HT0_1800M
 #define HT0_1600M
 //#define HT0_200M
+
 #define ENABLE_X
+//#define INTERCONNECTION_X_HT1_1_0 //USE HT1.0 on X
+#define HT1_X_1600M
+#define HT1_X_800M //Only in HT1.0 mode
+
+//#define HT0_16BIT //NO 16Bit mode in 4 chip interconnection
+#define USE_HT_RESET
+#define RESET_AGAIN_WHEN_FAIL
+#define ENABLE_RDinterleave
 
 
 #if 1 //Fix L2XBAR
@@ -87,6 +91,23 @@ ATTENTION: NO 16BIT mode when using HT1
 	nop
 #endif
 
+#if 1
+	TTYDBG("Shut down CPU1\r\n")
+	dli	a0, 0x900010001fe001d0
+	li	a1, 0x0
+	sw	a1, 0x0(a0)
+
+	TTYDBG("Shut down CPU2\r\n")
+	dli	a0, 0x900020001fe001d0
+	li	a1, 0x0
+	sw	a1, 0x0(a0)
+
+	TTYDBG("Shut down CPU3\r\n")
+	dli	a0, 0x900030001fe001d0
+	li	a1, 0x0
+	sw	a1, 0x0(a0)
+#endif
+
 
 #ifdef ENABLE_X
 	TTYDBG("Begin to enable X routing\r\n")
@@ -138,7 +159,7 @@ ATTENTION: NO 16BIT mode when using HT1
 	or  	a0, a1;
 	sw  	a0, 0x00(t0);
 
-#ifdef INTERCONNECTION_X_HT1
+#ifdef INTERCONNECTION_X_HT1_1_0
 	TTYDBG("X HT1.0 used \r\n")
 #########TEST CLKSEL[15]
 	li	t2, 0xbfe00194
@@ -186,7 +207,7 @@ ATTENTION: NO 16BIT mode when using HT1
 no_softconfig_x_ht1:
 ###################### HT_HI@CPU1
 	dli	a0, 0x90001ffdfb000000
-#ifdef X_HT1_800M
+#ifdef HT1_X_800M
 	//set 800 Mhz HT HOST
 	lw  	a1, 0x48(a0)
 	li  	a2, 0x500 ##800Mhz
@@ -202,7 +223,7 @@ no_softconfig_x_ht1:
 
 ###################### HT_HI@CPU0
 	dli	a0, 0x90000ffdfb000000
-#ifdef X_HT1_800M
+#ifdef HT1_X_800M
 	//set 800 Mhz HT HOST
 	lw  	a1, 0x48(a0)
 	li  	a2, 0x500 ##800Mhz
@@ -218,7 +239,7 @@ no_softconfig_x_ht1:
 
 ###################### HT_HI@CPU3
 	dli	a0, 0x90003ffdfb000000
-#ifdef X_HT1_800M
+#ifdef HT1_X_800M
 	//set 800 Mhz HT HOST
 	lw  	a1, 0x48(a0)
 	li  	a2, 0x500 ##800Mhz
@@ -234,7 +255,7 @@ no_softconfig_x_ht1:
 
 ###################### HT_HI@CPU2
 	dli	a0, 0x90002ffdfb000000
-#ifdef X_HT1_800M
+#ifdef HT1_X_800M
 	//set 800 Mhz HT HOST
 	lw  	a1, 0x48(a0)
 	li  	a2, 0x500 ##800Mhz
@@ -248,6 +269,258 @@ no_softconfig_x_ht1:
 	and 	a1, a1, a2            ##set to 8 bit mode
 	sw  	a1, 0x44(a0)
 
+#else
+	TTYDBG("HT3.0 used on X \r\n")
+
+#####HT3.0 reconnection
+
+###################### HT_HI@CPU0
+	dli 	a0, 0x90000ffdfb000000
+	//set 8 bit HT HOST
+	lw  	a1, 0x44(a0)
+	li  	a2, 0x88ffffff        ##8bit mode
+	and 	a1, a1, a2            ##set to 8 bit mode
+	sw  	a1, 0x44(a0)
+
+###################### HT_HI@CPU1
+	dli 	a0, 0x90001ffdfb000000
+	//set 8 bit HT HOST
+	lw  	a1, 0x44(a0)
+	li  	a2, 0x88ffffff        ##8bit mode
+	and 	a1, a1, a2            ##set to 8 bit mode
+	sw  	a1, 0x44(a0)
+
+###################### HT_HI@CPU2
+	dli 	a0, 0x90002ffdfb000000
+	//set 8 bit HT HOST
+	lw  	a1, 0x44(a0)
+	li  	a2, 0x88ffffff        ##8bit mode
+	and 	a1, a1, a2            ##set to 8 bit mode
+	sw  	a1, 0x44(a0)
+
+###################### HT_HI@CPU3
+	dli 	a0, 0x90003ffdfb000000
+	//set 8 bit HT HOST
+	lw  	a1, 0x44(a0)
+	li  	a2, 0x88ffffff        ##8bit mode
+	and 	a1, a1, a2            ##set to 8 bit mode
+	sw  	a1, 0x44(a0)
+
+
+#########TEST CLKSEL[15]
+	li	t2,0xbfe00194
+	lw	t1, 0x0(t2)
+	andi	t1, 0x8000
+	bnez	t1, no_softconfig_x_ht
+	nop
+
+
+#ifdef HT1_X_2400M
+	TTYDBG("Setting CPU0/1/2/3 HyperTransport Controller to be soft config 2400\r\n")
+	li	t0, 0x00466083
+#else
+#ifdef HT1_X_2200M
+	TTYDBG("Setting CPU0/1/2/3 HyperTransport Controller to be soft config 2200\r\n")
+	li	t0, 0x00465883
+#else
+#ifdef HT1_X_2000M
+	TTYDBG("Setting CPU0/1/2/3 HyperTransport Controller to be soft config 2000\r\n")
+	li	t0, 0x00465083
+#else
+#ifdef HT1_X_1800M
+	TTYDBG("Setting CPU0/1/2/3 HyperTransport Controller to be soft config 1800\r\n")
+	li	t0, 0x00464883
+#else
+#ifdef HT1_X_1600M
+	TTYDBG("Setting CPU0/1/2/3 HyperTransport Controller to be soft config 1600\r\n")
+	li	t0, 0x00464083
+#else
+#ifdef HT1_X_1200M
+	TTYDBG("Setting CPU0/1/2/3 HyperTransport Controller to be soft config 1200\r\n")
+	li	t0, 0x00463083
+#else
+#ifdef HT1_X_200M
+	TTYDBG("Setting CPU0/1/2/3 HyperTransport Controller to be soft config 200\r\n")
+	li	t0, 0x00460883
+#endif
+#endif
+#endif
+#endif
+#endif
+#endif
+#endif
+
+	dli	t2, 0x90000ffdfb000000
+	sw 	t0, 0x178(t2)
+	dli	t2, 0x90001ffdfb000000
+	sw 	t0, 0x178(t2)
+	dli	t2, 0x90002ffdfb000000
+	sw 	t0, 0x178(t2)
+	dli	t2, 0x90003ffdfb000000
+	sw 	t0, 0x178(t2)
+
+
+no_softconfig_x_ht:
+
+#ifdef HT1_X_3200M
+	TTYDBG("Setting CPU0/1 HyperTransport Controller to be 3200Mhz\r\n")
+	li	t0, 0xf //Frequency: 2400 Mhz
+#else
+#ifdef HT1_X_2400M
+	TTYDBG("Setting CPU0/1 HyperTransport Controller to be 2400Mhz\r\n")
+	li	t0, 0xd //Frequency: 2400 Mhz
+#else
+#ifdef HT1_X_2200M
+	TTYDBG("Setting CPU0/1 HyperTransport Controller to be 2200Mhz\r\n")
+	li	t0, 0xc //Frequency: 2200 Mhz
+#else
+#ifdef HT1_X_2000M
+	TTYDBG("Setting CPU0/1 HyperTransport Controller to be 2000Mhz\r\n")
+	li	t0, 0xb //Frequency: 2000 Mhz
+#else
+#ifdef HT1_X_1800M
+	TTYDBG("Setting CPU0/1 HyperTransport Controller to be 1800Mhz\r\n")
+	li	t0, 0xa //Frequency: 1800 Mhz
+#else
+#ifdef HT1_X_1600M
+	TTYDBG("Setting CPU0/1 HyperTransport Controller to be 1600Mhz\r\n")
+	li	t0, 0x9 //Frequency: 1600 Mhz
+#else
+#ifdef HT1_X_1200M
+	TTYDBG("Setting CPU0/1 HyperTransport Controller to be 1200Mhz\r\n")
+	li	t0, 0x7 //Frequency: 1200 Mhz
+#else
+#ifdef HT1_X_200M
+	TTYDBG("Setting CPU0/1 HyperTransport Controller to be 200Mhz\r\n")
+	#li	t0, 0x2 //Frequency: 400 Mhz
+	#li	t0, 0x0 //Frequency: 1200 Mhz
+	li	t0, 0x1 //Frequency: 200 Mhz
+#endif
+#endif
+#endif
+#endif
+#endif
+#endif
+#endif
+#endif
+
+	dli	t2, 0x90000ffdfb000000
+	sb 	t0, 0x49(t2)
+	dli	t2, 0x90001ffdfb000000
+	sb 	t0, 0x49(t2)
+	dli	t2, 0x90002ffdfb000000
+	sb 	t0, 0x49(t2)
+	dli	t2, 0x90003ffdfb000000
+	sb 	t0, 0x49(t2)
+
+	TTYDBG("Setting CPU0 HT1 HI HyperTransport Controller to be GEN3 mode\r\n")
+	dli	t2, 0x90000ffdfb000000
+	li 	t0, 0x88600000
+	sw 	t0, 0x110(t2)
+	lw      a0, 0x110(t2)
+	bal	hexserial
+	nop
+	TTYDBG("\r\n")
+
+	TTYDBG("Setting CPU0 HT1 HI HyperTransport Controller to be retry mode\r\n")
+	dli	t2, 0x90000ffdfb000000
+	li 	t0, 0x81
+	sb 	t0, 0x118(t2)
+	lw      a0, 0x118(t2)
+	bal	hexserial
+	nop
+	TTYDBG("\r\n")
+
+	TTYDBG("Enable CPU0 HT1 HI HyperTransport Controller scrambling\r\n")
+	dli	t2, 0x90000ffdfb000000
+	li 	t0, 0x78
+	sb 	t0, 0x130(t2)
+	lw      a0, 0x130(t2)
+	bal	hexserial
+	nop
+	TTYDBG("\r\n")
+
+	TTYDBG("Setting CPU1 HT1 HI HyperTransport Controller to be GEN3 mode\r\n")
+	dli	t2, 0x90001ffdfb000000
+	li 	t0, 0x88600000
+	sw 	t0, 0x110(t2)
+	lw      a0, 0x110(t2)
+	bal	hexserial
+	nop
+	TTYDBG("\r\n")
+
+	TTYDBG("Setting CPU1 HT1 HI HyperTransport Controller to be retry mode\r\n")
+	dli	t2, 0x90001ffdfb000000
+	li 	t0, 0x81
+	sb 	t0, 0x118(t2)
+	lw      a0, 0x118(t2)
+	bal	hexserial
+	nop
+	TTYDBG("\r\n")
+
+	TTYDBG("Enable CPU1 HT1 HI HyperTransport Controller scrambling\r\n")
+	dli	t2, 0x90001ffdfb000000
+	li 	t0, 0x78
+	sb 	t0, 0x130(t2)
+	lw      a0, 0x130(t2)
+	bal	hexserial
+	nop
+	TTYDBG("\r\n")
+
+	TTYDBG("Setting CPU2 HT1 HI HyperTransport Controller to be GEN3 mode\r\n")
+	dli	t2, 0x90002ffdfb000000
+	li 	t0, 0x88600000
+	sw 	t0, 0x110(t2)
+	lw      a0, 0x110(t2)
+	bal	hexserial
+	nop
+	TTYDBG("\r\n")
+
+	TTYDBG("Setting CPU2 HT1 HI HyperTransport Controller to be retry mode\r\n")
+	dli	t2, 0x90002ffdfb000000
+	li 	t0, 0x81
+	sb 	t0, 0x118(t2)
+	lw      a0, 0x118(t2)
+	bal	hexserial
+	nop
+	TTYDBG("\r\n")
+
+	TTYDBG("Enable CPU2 HT1 HI HyperTransport Controller scrambling\r\n")
+	dli	t2, 0x90002ffdfb000000
+	li 	t0, 0x78
+	sb 	t0, 0x130(t2)
+	lw      a0, 0x130(t2)
+	bal	hexserial
+	nop
+	TTYDBG("\r\n")
+
+	TTYDBG("Setting CPU3 HT1 HI HyperTransport Controller to be GEN3 mode\r\n")
+	dli	t2, 0x90003ffdfb000000
+	li 	t0, 0x88600000
+	sw 	t0, 0x110(t2)
+	lw      a0, 0x110(t2)
+	bal	hexserial
+	nop
+	TTYDBG("\r\n")
+
+	TTYDBG("Setting CPU3 HT1 HI HyperTransport Controller to be retry mode\r\n")
+	dli	t2, 0x90003ffdfb000000
+	li 	t0, 0x81
+	sb 	t0, 0x118(t2)
+	lw      a0, 0x118(t2)
+	bal	hexserial
+	nop
+	TTYDBG("\r\n")
+
+	TTYDBG("Enable CPU3 HT1 HI HyperTransport Controller scrambling\r\n")
+	dli	t2, 0x90003ffdfb000000
+	li 	t0, 0x78
+	sb 	t0, 0x130(t2)
+	lw      a0, 0x130(t2)
+	bal	hexserial
+	nop
+	TTYDBG("\r\n")
+
 #endif
 
 //reset links
@@ -537,7 +810,7 @@ no_softconfig_x_ht1:
 #ifdef HT0_RECONNECT
 	TTYDBG("HT0 frequency reconfig \r\n")
 
-#ifdef INTERCONNECTION_HT1
+#ifdef INTERCONNECTION_HT0_1_0
 	TTYDBG("HT1.0 used \r\n")
 
 #########TEST CLKSEL[15]
@@ -699,7 +972,7 @@ no_softconfig_ht1:
 #else
 
 	TTYDBG("HT3.0 used \r\n")
-
+#if 0
 	TTYDBG("Shut down CPU1\r\n")
 	dli	a0, 0x900010001fe001d0
 	li	a1, 0x0
@@ -714,6 +987,7 @@ no_softconfig_ht1:
 	dli	a0, 0x900030001fe001d0
 	li	a1, 0x0
 	sw	a1, 0x0(a0)
+#endif
 #####HT3.0 reconnection
 
 ###################### HT_HI@CPU1
@@ -1907,6 +2181,7 @@ reset_ht3:
 	TTYDBG("\r\n")
 #endif
 
+#if 0
 //////Enable others
 	TTYDBG("Enable CPU1\r\n")
 	dli	a0, 0x900010001fe001d0
@@ -1921,6 +2196,7 @@ reset_ht3:
 	li	a1, 0xffffffff
 	sw	a1, 0x0(a0)
 #endif
+#endif
 
 
 ##################################################
@@ -2094,3 +2370,44 @@ reset_ht3:
 
 	sd  	$0, 0x90(t2)
 
+#if 1
+//////Enable others
+	TTYDBG("Enable CPU1\r\n")
+	dli	a0, 0x900010001fe001d0
+	li	a1, 0xffffffff
+	sw	a1, 0x0(a0)
+	TTYDBG("Enable CPU2\r\n")
+	dli	a0, 0x900020001fe001d0
+	li	a1, 0xffffffff
+	sw	a1, 0x0(a0)
+	TTYDBG("Enable CPU3\r\n")
+	dli	a0, 0x900030001fe001d0
+	li	a1, 0xffffffff
+	sw	a1, 0x0(a0)
+#endif
+
+
+#ifdef ENABLE_RDinterleave
+	TTYDBG("Enable MC read interleave\r\n")
+
+	dli	t2, 0x900000003ff00400
+	lw	t1, 0x0(t2)
+	li	t0, 0x00000010
+	or	t1, t1, t0
+	sw	t1, 0x0(t2)
+	dli	t2, 0x900010003ff00400
+	lw	t1, 0x0(t2)
+	li	t0, 0x00000010
+	or	t1, t1, t0
+	sw	t1, 0x0(t2)
+	dli	t2, 0x900020003ff00400
+	lw	t1, 0x0(t2)
+	li	t0, 0x00000010
+	or	t1, t1, t0
+	sw	t1, 0x0(t2)
+	dli	t2, 0x900030003ff00400
+	lw	t1, 0x0(t2)
+	li	t0, 0x00000010
+	or	t1, t1, t0
+	sw	t1, 0x0(t2)
+#endif
diff --git a/Targets/Bonito3a84w/Bonito/start.S b/Targets/Bonito3a84w/Bonito/start.S
index 99a03eb5..f66c521d 100644
--- a/Targets/Bonito3a84w/Bonito/start.S
+++ b/Targets/Bonito3a84w/Bonito/start.S
@@ -343,25 +343,6 @@ boot_entry:
         bal     initserial1
         nop
 
-//#define SHUT_SLAVES
-#ifdef SHUT_SLAVES
-	PRINTSTR("Shut down other cores\r\n")
-	li      a0, 0xbfe001d0
-	li	a1, BOOTCORE_ID
-	sll	a1, 2
-	li      t1, 0xf
-	sll	a1, t1, a1
-	li	t1, 0x88888888
-	or	t1, a1, t1
-	sw      t1, 0x0(a0)
-	li      t1, 0x00000000
-	or	t1, a1, t1
-	sw      t1, 0x0(a0)
-
-#else
-	PRINTSTR("NOT Shut down other cores\r\n")
-#endif
-
 
 bsp_start:
 	PRINTSTR("\r\nPMON2000 MIPS Initializing. Standby...\r\n")
@@ -422,6 +403,25 @@ gs_2f_v3_ddr2_cfg:
 
 #include "loongson3_fixup.S"
 
+//#define SHUT_SLAVES
+#ifdef SHUT_SLAVES
+	PRINTSTR("Shut down other cores\r\n")
+	li      a0, 0xbfe001d0
+	li	a1, BOOTCORE_ID
+	sll	a1, 2
+	li      t1, 0xf
+	sll	a1, t1, a1
+	li	t1, 0x88888888
+	or	t1, a1, t1
+	sw      t1, 0x0(a0)
+	li      t1, 0x00000000
+	or	t1, a1, t1
+	sw      t1, 0x0(a0)
+
+#else
+	PRINTSTR("NOT Shut down other cores\r\n")
+#endif
+
 	dli	s1, 0x0000100000000000
 #include "loongson3_clksetting.S"