Change Xbar1 windows back to the old method used by lemete and dawning

1. Modify Xbar1 windows.
2. Modify some Macro definitions.

result: rtl8139 works and IDE does not work.

Targets/Bonito3adawning/Bonito/loongson3_HT_init.S

@@ -20,6 +20,7 @@
     dli t2, 0x900000003ff02400
 
 1:
+#if 0
  //map HT: PCI IO : 0x90000efd_fc000000 --> 0x18000000
  //map              0x90000efd_fd000000 --> 0x19000000
  //map HT: PCI CFG: 0x90000efd_fe000000 --> 0x1a000000
@@ -74,6 +75,73 @@
     nop
 
 #endif
+/******************************************/
+##################################### LEVEL-1 XBAR : CPU #########################################
+###HT CFG : TYPE 0: 
+###map 0x90000efd_fe000000 --> 0x1fe80000, size 0x00080000 
+	dli t1, 0x000000001fe80000
+	sd  t1, 0x0(t0)
+	dli t1, 0xfffffffffff80000
+	sd  t1, 0x40(t0)
+	dli t1, 0x00000efdfe0000f7
+	sd  t1, 0x80(t0)
+###HT CFG : TYPE 1:
+###map 0x90000efd_ff000000 --> 0x1e000000, size 0x01000000
+	dli t1, 0x000000001e000000
+	sd  t1, 0x8(t0)
+	dli t1, 0xffffffffff000000
+	sd  t1, 0x48(t0)
+	dli t1, 0x00000efdff0000f7
+	sd  t1, 0x88(t0)
+
+###HT LOW MEM
+###map 0x90000e00_00000000 --> 0x10000000, size 0x04000000
+	dli t1, 0x0000000010000000
+	sd  t1, 0x10(t0)
+	dli t1, 0xfffffffffc000000
+	sd  t1, 0x50(t0)
+	dli t1, 0x00000e00000000f7
+	sd  t1, 0x90(t0)
+
+###HT HIGH MEM
+###map 0x90000e00_10000000 --> 0x14000000, size 0x04000000
+	dli t1, 0x0000000014000000
+	sd  t1, 0x18(t0)
+	dli t1, 0xfffffffffc000000
+	sd  t1, 0x58(t0)
+	dli t1, 0x00000e00140000f7
+	sd  t1, 0x98(t0)
+
+###HT IO 
+###map 0x90000efd_fc000000 --> 0x1fd00000, size 0x01000000
+	dli t1, 0x000000001fd00000
+	sd  t1, 0x20(t0)
+	dli t1, 0xfffffffffff00000
+	sd  t1, 0x60(t0)
+	dli t1, 0x00000efdfc0000f7
+	sd  t1, 0xa0(t0)
+
+###HT BRIDGE CFG
+###map 0x90000efd_fb000000 --> 0x1b000000, size 0x01000000
+	dli t1, 0x000000001b000000
+	sd  t1, 0x28(t0)
+	dli t1, 0xffffffffff000000
+	sd  t1, 0x68(t0)
+	dli t1, 0x00000efdfb0000f7
+	sd  t1, 0xa8(t0)
+
+### ANY ELSE DEFAULY MEMORY 
+### Mapping 0x0 ---> 0x0, size 0x00001000_00000000
+
+	daddiu	t0, t0, 0x100
+	bne	t0, t2, 1b
+	nop
+
+
+/******************************************/
+#endif
+
+
 
 //////////////////
 #if	0
@@ -293,6 +361,25 @@ ht_next_id :
 
 #endif
 
+//lycheng
+#if 0
+        TTYDBG("-------------------HT HOST mode enable\r\n")
+        li      t2, 0xbb000040
+        lw      a0, 0x0(t2)
+        bal     hexserial
+        nop
+
+        li      t1, 0xfbffffff
+        and     a0, a0, t1
+        sw      a0, 0x0(t2)
+
+        lw      a0, 0x0(t2)
+        bal     hexserial
+        nop
+        TTYDBG("\r\n")
+        TTYDBG("-------------------HT HOST mode enable done\r\n")
+#endif
+
 #ifdef HT_16bit//Set HT bridge to be 16-bit width
 	TTYDBG("Setting HyperTransport Controller to be 16-bit width\r\n")
 	dli	    t2, 0x90000efdfb000000
@@ -949,7 +1036,7 @@ crc_checking:
 
 #endif
 
-#if 1//Enable the LPC on the Southbridge, including SuperIO, LED....
+#if 0//Enable the LPC on the Southbridge, including SuperIO, LED....
 	TTYDBG("Check the LPC on the Southbridge\r\n")
 	//li	t0, 0xba000800
     dli	    t0, 0x90000efdfe000800

Targets/Bonito3adawning/include/bonito.h

@@ -41,8 +41,8 @@ extern char           *heaptop;
 #define GS3_UART1_BASE 0xbfe001e8
 #define GS3_UART_BASE   GS3_UART0_BASE
 #ifdef LS3_HT
-#define COM1_BASE_ADDR	0xb80003f8
-#define COM2_BASE_ADDR	0xb80002f8
+#define COM1_BASE_ADDR	0xbfd003f8
+#define COM2_BASE_ADDR	0xbfd002f8
 #else
 #define COM1_BASE_ADDR	0xbfd003f8
 #define COM2_BASE_ADDR	0xbfd002f8
@@ -137,8 +137,8 @@ extern char           *heaptop;
 //#define BONITO_PCIHI_TOP		(BONITO_PCIHI_BASE+BONITO_PCIHI_SIZE-1)
 //#define BONITO_PCIIO_BASE		0x1fd00000
 //#define BONITO_PCIIO_BASE_VA		0xbfd00000
-#define BONITO_PCIIO_BASE		0x18000000
-#define BONITO_PCIIO_BASE_VA    0xb8000000
+#define BONITO_PCIIO_BASE		0x1fd00000
+#define BONITO_PCIIO_BASE_VA    0xbfd00000
 #define BONITO_PCIIO_SIZE		0x02000000
 #else
 #define BONITO_PCILO2_BASE		0x18000000

Targets/Bonito3adawning/pci/amd_780e.c

@@ -329,7 +329,7 @@ void sb700_devices_por_init(void)
 	/* clear any lingering errors, so the transaction will run */
 	printk_info("IO Address Enable\n");
 	//OUTB(INB(0xba000000 + SMBUS_IO_BASE + SMBHSTSTAT), 0xba000000 + SMBUS_IO_BASE + SMBHSTSTAT);
-	OUTB(INB(0xb8000000 + SMBUS_IO_BASE + SMBHSTSTAT), 0xb8000000 + SMBUS_IO_BASE + SMBHSTSTAT);
+	OUTB(INB(0xbfd00000 + SMBUS_IO_BASE + SMBHSTSTAT), 0xbfd00000 + SMBUS_IO_BASE + SMBHSTSTAT);
 #endif
 	/* IDE Device, BDF:0-20-1 */
 	printk_info("sb700_devices_por_init(): IDE Device, BDF:0-20-1\n");

Targets/Bonito3adawning/pci/rs780_cmn.c

@@ -21,8 +21,8 @@
 #include "rs780_cmn.h"
 
 #define HT_CONF_TYPE0_ADDR 0x90000efdfe000000
-//#define HT_MAP_TYPE0_CONF_ADDR  0xbfe80000
-#define HT_MAP_TYPE0_CONF_ADDR  0xba000000
+#define HT_MAP_TYPE0_CONF_ADDR  0xbfe80000
+//#define HT_MAP_TYPE0_CONF_ADDR  0xba000000
 
 
 typedef unsigned long long u64;
@@ -51,8 +51,8 @@ void pci_write_type0_config32(u32 dev, u32 func, u32 reg, u32 val){
 
 
 #define HT_CONF_TYPE1_ADDR 0x90000efdff000000
-//#define HT_MAP_TYPE1_CONF_ADDR  0xbe000000
-#define HT_MAP_TYPE1_CONF_ADDR  0xbb000000
+#define HT_MAP_TYPE1_CONF_ADDR  0xbe000000
+//#define HT_MAP_TYPE1_CONF_ADDR  0xbb000000
 
 u32 pci_read_type1_config32(u32 bus, u32 dev, u32 func, u32 reg){
     //u64 addr = 0x90000efdff000000;

Targets/Bonito3adawning/pci/sb700.h

@@ -38,10 +38,10 @@ extern void     _pci_break_tag(device_t, int *, int *, int *);
 #define PM2_INDEX	0xba000cd0
 #define PM2_DATA	0xba000cd1
 #endif
-#define PM_INDEX	0xb8000cd6
-#define PM_DATA		0xb8000cd7
-#define PM2_INDEX	0xb8000cd0
-#define PM2_DATA	0xb8000cd1
+#define PM_INDEX	0xbfd00cd6
+#define PM_DATA		0xbfd00cd7
+#define PM2_INDEX	0xbfd00cd0
+#define PM2_DATA	0xbfd00cd1
 
 extern void pm_iowrite(u8 reg, u8 value);
 extern u8 pm_ioread(u8 reg);

Targets/Bonito3adawning/pci/sb700_smbus.h

@@ -43,7 +43,7 @@
 
 //#define AB_INDX   0xCD8
 //#define AB_INDX   0xba000CD8
-#define AB_INDX   0xb8000CD8
+#define AB_INDX   0xbfd00CD8
 #define AB_DATA   (AB_INDX+4)
 
 /* Between 1-10 seconds, We should never timeout normally