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@ -8,6 +8,7 @@ |
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#define HT_32bit_TRANS |
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#define WITH_HT |
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#define HT_800M |
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//#define HT_1600M |
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//#define HT_16bit |
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#define HT_RECONNECT |
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//#define HT_REG_TRANS |
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@ -373,6 +374,57 @@ ht_next_id : |
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TTYDBG("\r\n") |
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#endif |
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#ifdef HT_1600M//Set HT bridge to be 1600Mhz |
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TTYDBG("Setting CPU HyperTransport Controller to be soft config 1600\r\n") |
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dli t2, 0x90000efdfb000000 |
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li t0, 0x00464083 |
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dli t2, 0x90000efdfb000000 |
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sw t0, 0x178(t2) |
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lw a0, 0x178(t2) |
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bal hexserial |
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nop |
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TTYDBG("\r\n") |
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TTYDBG("Setting HyperTransport Controller to be 1600Mhz\r\n") |
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dli t2, 0x90000efdfb000000 |
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#li t0, 0x2 //Frequency: 400 Mhz |
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li t0, 0x9 //Frequency: 1600 Mhz |
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sb t0, 0x49(t2) |
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lw a0, 0x48(t2) |
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bal hexserial |
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nop |
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TTYDBG("\r\n") |
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TTYDBG("Setting HyperTransport Controller to be GEN3 mode\r\n") |
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dli t2, 0x90000efdfb000000 |
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li t0, 0x88600000 |
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sw t0, 0x110(t2) |
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lw a0, 0x110(t2) |
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bal hexserial |
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nop |
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TTYDBG("\r\n") |
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TTYDBG("Setting HyperTransport Controller to be retry mode\r\n") |
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dli t2, 0x90000efdfb000000 |
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li t0, 0x81 |
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sb t0, 0x118(t2) |
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lw a0, 0x118(t2) |
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bal hexserial |
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nop |
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TTYDBG("\r\n") |
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TTYDBG("Enable HyperTransport Controller scrambling\r\n") |
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dli t2, 0x90000efdfb000000 |
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li t0, 0x78 |
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sb t0, 0x130(t2) |
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lw a0, 0x130(t2) |
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bal hexserial |
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nop |
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TTYDBG("\r\n") |
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#endif |
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#endif |
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