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ls2k add param DDR_PARAM_1e8 in loongson_mc2_param.S. 

Change-Id: I65a384162092501dc59b6b624530563ea6207bb1
Signed-off-by: QiaoChong <qiaochong@loongson.cn>
master
QiaoChong 7 years ago
committed by Chong Qiao
parent
9c15c2ade1
commit
4e975d8fec
1 changed files with 12 additions and 0 deletions
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  1. 12
      Targets/LS2K/ls2k/loongson_mc2_param.S

12
Targets/LS2K/ls2k/loongson_mc2_param.S
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@ -146,7 +146,11 @@ MC0_DDR3_CTRL_0x1d8: .dword 0x14050c0607070406
//_00000000 pm_tXPDLL _00000000 pm_tXP 000_00000 pm_tWR 0000_0000 pm_tRTP 0000_0000 pm_tRL 0000_0000 pm_tWL 0000_0000 pm_tCCD 0000_0000 pm_tWTR
MC0_DDR3_CTRL_0x1e0: .dword 0x0503000000000000
//00_000000 pm_tW2R_diffcs_dly 00_000000 pm_tW2W_diffcs_adj_dly 00_000000 pm_tR2P_sameba_adj_dly 00_000000 pm_tW2P_sameba_adj_dly 00_000000 pm_tR2R_sameba_adj_dly 00_000000 pm_tR2W_sameba_adj_dly 00_000000 pm_tW2R_sameba_adj_dly 00_000000 pm_tW2W_sameba_adj_dly
#ifdef DDR_PARAM_1e8
MC0_DDR3_CTRL_0x1e8: .dword DDR_PARAM_1e8
#else
MC0_DDR3_CTRL_0x1e8: .dword 0x0309000000000000
#endif
//00_000000 pm_tR2R_diffcs_adj_dly 00_000000 pm_tR2W_diffcs_dly 00_000000 pm_tR2P_samecs_dly 00_000000 pm_tW2P_samecs_dly 00_000000 pm_tR2R_samecs_adj_dly 00_000000 pm_tR2W_samecs_adj_dly 00_000000 pm_tW2R_samecs_adj_dly 00_000000 pm_tW2W_samecs_adj_dly
MC0_DDR3_CTRL_0x1f0: .dword 0x000801e4ff000101
//0000_0000 pm_power_up _00000000 pm_age_step _00000000 pm_tCPDED _00000000 pm_cs_map _00000000 pm_bs_config 00000_000 pm_channel_32 pm_channel_16 pm_nc 0000_0000 pm_pr_r2w 0000000_0 pm_placement_en
@ -257,7 +261,11 @@ MC0_DDR3_RDIMM_CTRL_0x010: .dword 0x0000000000000000
//XXXX pm_dll_value_8(RD) XXXX pm_dll_value_7 (RD) XXXX pm_dll_value_6(RD) XXXX pm_dll_value_5(RD)
//MC0_DDR3_RDIMM_CTRL_0x018: .dword 0x5252525216100000
//MC0_DDR3_RDIMM_CTRL_0x018: .dword 0x4040404016100000
#ifdef DDR_PARAM_018
MC0_DDR3_RDIMM_CTRL_0x018: .dword DDR_PARAM_018
#else
MC0_DDR3_RDIMM_CTRL_0x018: .dword 0x4545454516100000
#endif
//MC0_DDR3_RDIMM_CTRL_0x018: .dword 0x2525252516100000
//_00000000 pm_dll_ck_3 _00000000 pm_dll_ck_2 _00000000 pm_dll_ck_1 _00000000 pm_dll_ck_0 _00000000 pm_dll_increment _00000000 pm_dll_start_point _0000000_0 pm_dll_bypass _0000000_0 pm_init_start
MC0_DDR3_RDIMM_CTRL_0x020: .dword 0x0201000201000000
@ -379,7 +387,11 @@ MC0_DDR3_RDIMM_CTRL_0x1d8: .dword 0x14050c0608070406
//_00000000 pm_tXPDLL _00000000 pm_tXP 000_00000 pm_tWR 0000_0000 pm_tRTP 0000_0000 pm_tRL 0000_0000 pm_tWL 0000_0000 pm_tCCD 0000_0000 pm_tWTR
MC0_DDR3_RDIMM_CTRL_0x1e0: .dword 0x0503000000000000
//00_000000 pm_tW2R_diffcs_dly 00_000000 pm_tW2W_diffcs_adj_dly 00_000000 pm_tR2P_sameba_adj_dly 00_000000 pm_tW2P_sameba_adj_dly 00_000000 pm_tR2R_sameba_adj_dly 00_000000 pm_tR2W_sameba_adj_dly 00_000000 pm_tW2R_sameba_adj_dly 00_000000 pm_tW2W_sameba_adj_dly
#ifdef DDR_PARAM_1e8
MC0_DDR3_RDIMM_CTRL_0x1e8: .dword DDR_PARAM_1e8
#else
MC0_DDR3_RDIMM_CTRL_0x1e8: .dword 0x0309000000000000
#endif
//00_000000 pm_tR2R_diffcs_adj_dly 00_000000 pm_tR2W_diffcs_dly 00_000000 pm_tR2P_samecs_dly 00_000000 pm_tW2P_samecs_dly 00_000000 pm_tR2R_samecs_adj_dly 00_000000 pm_tR2W_samecs_adj_dly 00_000000 pm_tW2R_samecs_adj_dly 00_000000 pm_tW2W_samecs_adj_dly
MC0_DDR3_RDIMM_CTRL_0x1f0: .dword 0x000801e4ff000101
//0000_0000 pm_power_up _00000000 pm_age_step _00000000 pm_tCPDED _00000000 pm_cs_map _00000000 pm_bs_config 00000_000 pm_channel_32 pm_channel_16 pm_nc 0000_0000 pm_pr_r2w 0000000_0 pm_placement_en

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