3a82h make slave stay on ram when wait smp boot.

Change-Id: I78750c6de468d5a6687dbf5ae58bf110d3bb63a8
Signed-off-by: QiaoChong <qiaochong@loongson.cn>

Targets/Bonito3a82h/Bonito/start.S

@@ -590,8 +590,8 @@ after_ht:
 	//dli     s1, 0x00000000c1a18400 
 	//dli     s1, 0x00000000c1a18204 
 	//dli	s1, 0xc1a18404c1a18404
-	//dli	s1, 0xc0a18404
-	dli	s1, 0xc0a18400c0a18400
+	dli	s1, 0xc0a18404
+	//dli	s1, 0xc0a18400c0a18400
 #endif
 #include "ddr_dir/loongson3_ddr2_config.S"
 //#include "ddr_dir/loongson3_ddr2_config.S"
@@ -1339,6 +1339,7 @@ wait_scache_allover:
 
 	bal	clear_mailbox
 	nop
+.global waitforinit;
 waitforinit:
 
 	li      a0, 0x1000
@@ -1350,6 +1351,7 @@ idle1000:
 	lw      t2, FN_OFF(t1)
 	beqz    t2, waitforinit
 	nop
+	sw      zero, FN_OFF(t1)
 
 	dli     t3, 0xffffffff00000000 
 	or      t2, t3

Targets/Bonito3a82h/Bonito/tgt_machdep.c

@@ -276,12 +276,29 @@ void movinv1(int iter, ulong p1, ulong p2);
 pcireg_t _pci_allocate_io(struct pci_device *dev, vm_size_t size);
 static void superio_reinit();
 
+extern char waitforinit[];
 void
 initmips(unsigned long long raw_memsz)
 {
 	int i;
 	int* io_addr;
 	unsigned long long memsz;
+	//core1-3 run waitdorinit function in ram
+	asm volatile(
+	".set push;\n"
+	".set noreorder\n"
+        ".set mips64;\n"
+	"dli $2,0x900000003ff01100;\n"
+	"dli $3, 3;\n"
+        "1:sd %0,0x20($2);"
+	"daddiu $2,0x100;\n"
+	"addiu $3,-1;\n"
+	"bnez $3, 1b;\n"
+	"nop;\n"
+	".set reorder;\n"
+        ".set mips0;\n"
+	".set pop;\n"
+         ::"r"(&waitforinit):"$2","$3");
 
 	tgt_fpuenable();
 	/*enable float*/

Targets/Bonito3a82h/conf/Bonito.3a82h

@@ -23,10 +23,10 @@ option		TARGETNAME="\"Bonito\""
 option      loongson3A3
 option	    LSMC_2
 option      DDR3_DIMM
-#option      ARB_LEVEL
-option      AUTO_DDR_CONFIG
+option      ARB_LEVEL
+#option      AUTO_DDR_CONFIG
 option      USE_LS2H_I2C
-option	    FIX_3A82H_DDR
+#option	    FIX_3A82H_DDR
 
 option		BONITOEL
 option      DEVBD2F
@@ -203,6 +203,7 @@ pci*		at ppb? bus ?
 #fxp0        at pci? dev ? function ?        # Intel 82559 Device
 #inphy*      at mii? phy ?                   # Intel 82555 PHYs
 igb*		at pci? dev ? function ?	# Intel 82576
+select igb1
 # rtl*        at pci? dev ? function ?
 #rte*		at pci? dev ? function ?
 #rtk*		at pci? dev ? function ?
@@ -274,3 +275,5 @@ select tcp
 select inet
 select tftpd
 #select e100
+option PCIVERBOSE=5
+#option DISABLE_HARD_LEVELING

Targets/Bonito3a82h/pci/ls2h_pci.c

@@ -422,11 +422,13 @@ void ls2h_pcie_port_init(int port)
 {
 	unsigned reg, data;
 
+#if 0
 	reg = LS2H_PCIE_PORT_HEAD_BASE_PORT(port) | 0x7c;
 	data = ls2h_readl(reg);
 	data &= ~0xf;
 	data |=1;
 	ls2h_writel(data, reg);
+#endif
 
 	reg = LS2H_PCIE_REG_BASE_PORT(port) | LS2H_PCIE_PORT_REG_CTR0;
 	ls2h_writel(0xff204c, reg);