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3a82w pci config ext access.

43291_rs780_rpr_nda_1.05.pdf
5.9.8
Program PCIE Memory Mapped Configuration Space

Change-Id: Ica689e95ebab962c94c1ffe1c283e060db8114ab
Signed-off-by: QiaoChong <qiaochong@loongson.cn>
master
QiaoChong 7 years ago
committed by Chong Qiao
parent
commit
557912e5b6
  1. 2
      Targets/Bonito3a82w/pci/rs780.h
  2. 6
      Targets/Bonito3a82w/pci/rs780_cmn.c
  3. 13
      Targets/Bonito3a82w/pci/rs780_pcie.c

2
Targets/Bonito3a82w/pci/rs780.h

@ -27,7 +27,7 @@
#define NBHTIU_INDEX 0xA8
#define NBMC_INDEX 0xE8
#define NBPCIE_INDEX 0xE0
#define EXT_CONF_BASE_ADDRESS 0x17000000
#define EXT_CONF_BASE_ADDRESS 0x70000000
#define TEMP_MMIO_BASE_ADDRESS 0xC0000000
typedef struct __PCIE_CFG__ {

6
Targets/Bonito3a82w/pci/rs780_cmn.c

@ -298,9 +298,8 @@ u16 pci_ext_read_config16(device_t nb_tag, device_t tag, u32 reg)
_pci_break_tag(tag, &bus, &dev, &func);
/*get BAR3 base address for nbcfg0x1c */
addr = (_pci_conf_read(bar3_tag, 0x1c) & ~(0x0f))| 0x80000000;
addr = (_pci_conf_read(bar3_tag, 0x1c) & ~(0x0f))| 0xc0000000;
addr |= bus << 20 | dev << 15 | func << 12 | reg;
addr |= 0x0e000000; //added by oldtai for the cpu win changed maybe cause ide not passing
//printf("ext =========== addr=%x,bus=%x,dev=%x, fn=%x\n", addr, bus, dev, func);
return *((volatile u16 *) addr);
@ -314,9 +313,8 @@ void pci_ext_write_config16(device_t nb_tag, device_t tag, u32 reg_pos, u32 mask
_pci_break_tag(tag, &bus, &dev, &func);
/*get BAR3 base address for nbcfg0x1c */
addr = (_pci_conf_read(bar3_tag, 0x1c) & ~(0x0f))| 0x80000000;
addr = (_pci_conf_read(bar3_tag, 0x1c) & ~(0x0f))| 0xc0000000;
addr |= bus << 20 | dev << 15 | func << 12 | reg_pos;
addr |= 0x0e000000; //added by oldtai for the cpu win changed
//printf("addr=%x,bus=%x,dev=%x, fn=%x\n", addr, bus, dev, func);
*((volatile u16 *) addr) = val;

13
Targets/Bonito3a82w/pci/rs780_pcie.c

@ -227,12 +227,21 @@ static void switching_gpp_configurations(device_t nb_dev, device_t sb_dev)
*****************************************************************/
void enable_pcie_bar3(device_t nb_dev)
{
/*
43291_rs780_rpr_nda_1.05.pdf
5.9.8
Program PCIE Memory Mapped Configuration Space
43734_rs780_bdg_nda_1.06.pdf
2.3
HTIU Indirect Register Space (HTIUIND)
*/
set_nbcfg_enable_bits(nb_dev, 0x7C, 1 << 30, 1 << 30); /* Enables writes to the BAR3 register. */
set_nbcfg_enable_bits(nb_dev, 0x84, 7 << 16, 0 << 16);
pci_write_config32(nb_dev, 0x1C, EXT_CONF_BASE_ADDRESS); /* PCIEMiscInit */
pci_write_config32(nb_dev, 0x20, 0x00000000);
set_htiu_enable_bits(nb_dev, 0x32, 1 << 28, 1 << 28); /* PCIEMiscInit */
//set_htiu_enable_bits(nb_dev, 0x32, 1 << 28, 1 << 28); /* PCIEMiscInit */
htiu_write_indexN(nb_dev, 0x32, htiu_read_indexN(nb_dev, 0x32) | (1<<28));
}
/*****************************************************************
@ -245,6 +254,8 @@ void disable_pcie_bar3(device_t nb_dev)
pci_write_config32(nb_dev, 0x1C, 0); /* clear BAR3 address */
printk_info("Disable writes to the BAR3\n");
set_nbcfg_enable_bits(nb_dev, 0x7C, 1 << 30, 0 << 30); /* Disable writes to the BAR3. */
//set_htiu_enable_bits(nb_dev, 0x32, 1 << 28, 0 << 28); /* PCIEMiscInit */
htiu_write_indexN(nb_dev, 0x32, htiu_read_indexN(nb_dev, 0x32) & ~(1<<28));
}
/*****************************************

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