Reduce 7A HT core frequency and fix 3A HT hardware configuration frequency error

Change-Id: I9c6ae0c2eb2d79f12dca52ece8110ec40ab506b4

Targets/Bonito3a4000_7a/Bonito/loongson3_fixup.S

@@ -199,7 +199,7 @@
 #define SET_HARD_FREQ(node, ht, freq) \
 	li	t0, freq; \
 	dli	t2, 0x900000fdfb000000 | node << 44 | ht << 40; \
-	sb	t0, 0x49(t2);
+	sb	t0, (LS3A_HT_FREQ+1)(t2);
 
 #define SET_GEN3_MODE(node, ht) \
 	dli	t2, 0x900000fdfb000000 | node << 44 | ht << 40; \

pmon/arch/mips/ls7a/ht.h

@@ -68,8 +68,8 @@
 #define LS7A_HT_PLL_400M   ((4 << LS7A_HT_PLL_DIV_LO) | (4 << LS7A_HT_PLL_DIV_HI) | (3 << LS7A_HT_PLL_DIV_REFC) | (16*4 << LS7A_HT_PLL_LOOPC) | (4 << LS7A_HT_PLL_DIV_CTRL))
 #define LS7A_HT_PLL_200M   ((8 << LS7A_HT_PLL_DIV_LO) | (8 << LS7A_HT_PLL_DIV_HI) | (3 << LS7A_HT_PLL_DIV_REFC) | (16*4 << LS7A_HT_PLL_LOOPC) | (4 << LS7A_HT_PLL_DIV_CTRL))
 
-#define LS7A_C_HT_PLL_2000M  ((1 << LS7A_HT_PLL_DIV_LO) | (1 << LS7A_HT_PLL_DIV_HI) | (2 << LS7A_HT_PLL_DIV_REFC) | (20*2 << LS7A_HT_PLL_LOOPC) | (3 << LS7A_HT_PLL_DIV_CTRL))
+#define LS7A_C_HT_PLL_2000M  ((1 << LS7A_HT_PLL_DIV_LO) | (1 << LS7A_HT_PLL_DIV_HI) | (2 << LS7A_HT_PLL_DIV_REFC) | (20*2 << LS7A_HT_PLL_LOOPC) | (4 << LS7A_HT_PLL_DIV_CTRL))
-#define LS7A_C_HT_PLL_1600M  ((2 << LS7A_HT_PLL_DIV_LO) | (2 << LS7A_HT_PLL_DIV_HI) | (2 << LS7A_HT_PLL_DIV_REFC) | (32*2 << LS7A_HT_PLL_LOOPC) | (5 << LS7A_HT_PLL_DIV_CTRL))
+#define LS7A_C_HT_PLL_1600M  ((2 << LS7A_HT_PLL_DIV_LO) | (2 << LS7A_HT_PLL_DIV_HI) | (2 << LS7A_HT_PLL_DIV_REFC) | (32*2 << LS7A_HT_PLL_LOOPC) | (8 << LS7A_HT_PLL_DIV_CTRL))
 #ifdef LOONGSON3A4000
 #define LS3A_HT_RX_CACHE_WIN0_OFFSET    0x140
 #define LS3A_HT_RX_CACHE_WIN1_OFFSET    0x148