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@ -1073,10 +1073,29 @@ cal_one_pcie_x8: |
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or a0, ((PCIE_TRY_GEN2 << 17) | (PCIE_TX_FULL_SWING << 18)) |
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sw a0, 0xc(t3) |
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dli t3, 0x90000efe0700481c |
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lw a1, 0x0(t3) |
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li a0, (0x1 << 26) |
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not a0, a0 |
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and a1, a1, a0 |
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sw a1, 0x0(t3) |
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dli t3, 0x90000efe00004800 |
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li a0, 0x60000000 |
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sw a0, 0x10(t3) |
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dli t1, 0x90000e0060000000 |
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li t3, (0x1<<18) |
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not t3, t3 |
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lw a0, 0x54(t1) |
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and a0, a0, t3 |
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sw a0, 0x54(t1) |
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lw a0, 0x58(t1) |
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and a0, a0, t3 |
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sw a0, 0x58(t1) |
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dli t1, 0x90000e0060000000 |
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li a0, 0xff204c |
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sw a0, 0x0(t1) |
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@ -1116,10 +1135,28 @@ cal_one_pcie_x8: |
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or a0, ((PCIE_TRY_GEN2 << 17) | (PCIE_TX_FULL_SWING << 18)) |
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sw a0, 0xc(t3) |
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dli t3, 0x90000efe0700501c |
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lw a1, 0x0(t3) |
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li a0, (0x1 << 26) |
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not a0, a0 |
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and a1, a1, a0 |
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sw a1, 0x0(t3) |
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dli t3, 0x90000efe00005000 |
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li a0, 0x60100000 |
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sw a0, 0x10(t3) |
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dli t1, 0x90000e0060100000 |
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li t3, (0x1<<18) |
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not t3, t3 |
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lw a0, 0x54(t1) |
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and a0, a0, t3 |
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sw a0, 0x54(t1) |
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lw a0, 0x58(t1) |
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and a0, a0, t3 |
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sw a0, 0x58(t1) |
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dli t1, 0x90000e0060100000 |
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li a0, 0xff204c |
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sw a0, 0x0(t1) |
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@ -1147,10 +1184,28 @@ cal_one_pcie_x8: |
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or a0, ((PCIE_TRY_GEN2 << 17) | (PCIE_TX_FULL_SWING << 18)) |
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sw a0, 0xc(t3) |
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dli t3, 0x90000efe0700581c |
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lw a1, 0x0(t3) |
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li a0, (0x1 << 26) |
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not a0, a0 |
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and a1, a1, a0 |
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sw a1, 0x0(t3) |
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dli t3, 0x90000efe00005800 |
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li a0, 0x60200000 |
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sw a0, 0x10(t3) |
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dli t1, 0x90000e0060200000 |
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li t3, (0x1<<18) |
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not t3, t3 |
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lw a0, 0x54(t1) |
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and a0, a0, t3 |
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sw a0, 0x54(t1) |
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lw a0, 0x58(t1) |
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and a0, a0, t3 |
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sw a0, 0x58(t1) |
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dli t1, 0x90000e0060200000 |
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li a0, 0xff204c |
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sw a0, 0x0(t1) |
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@ -1178,10 +1233,28 @@ cal_one_pcie_x8: |
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or a0, ((PCIE_TRY_GEN2 << 17) | (PCIE_TX_FULL_SWING << 18)) |
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sw a0, 0xc(t3) |
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dli t3, 0x90000efe0700601c |
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lw a1, 0x0(t3) |
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li a0, (0x1 << 26) |
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not a0, a0 |
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and a1, a1, a0 |
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sw a1, 0x0(t3) |
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dli t3, 0x90000efe00006000 |
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li a0, 0x60300000 |
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sw a0, 0x10(t3) |
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dli t1, 0x90000e0060300000 |
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li t3, (0x1<<18) |
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not t3, t3 |
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lw a0, 0x54(t1) |
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and a0, a0, t3 |
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sw a0, 0x54(t1) |
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lw a0, 0x58(t1) |
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and a0, a0, t3 |
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sw a0, 0x58(t1) |
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dli t1, 0x90000e0060300000 |
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li a0, 0xff204c |
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sw a0, 0x0(t1) |
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@ -1264,10 +1337,28 @@ cal_one_pcie_x8: |
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or a0, ((PCIE_TRY_GEN2 << 17) | (PCIE_TX_FULL_SWING << 18)) |
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sw a0, 0xc(t3) |
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dli t3, 0x90000efe0700681c |
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lw a1, 0x0(t3) |
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li a0, (0x1 << 26) |
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not a0, a0 |
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and a1, a1, a0 |
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sw a1, 0x0(t3) |
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dli t3, 0x90000efe00006800 |
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li a0, 0x60000000 |
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sw a0, 0x10(t3) |
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dli t1, 0x90000e0060000000 |
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li t3, (0x1<<18) |
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not t3, t3 |
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lw a0, 0x54(t1) |
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and a0, a0, t3 |
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sw a0, 0x54(t1) |
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lw a0, 0x58(t1) |
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and a0, a0, t3 |
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sw a0, 0x58(t1) |
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dli t1, 0x90000e0060000000 |
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li a0, 0xff204c |
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sw a0, 0x0(t1) |
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@ -1307,10 +1398,28 @@ cal_one_pcie_x8: |
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or a0, ((PCIE_TRY_GEN2 << 17) | (PCIE_TX_FULL_SWING << 18)) |
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sw a0, 0xc(t3) |
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dli t3, 0x90000efe0700701c |
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lw a1, 0x0(t3) |
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li a0, (0x1 << 26) |
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not a0, a0 |
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and a1, a1, a0 |
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sw a1, 0x0(t3) |
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dli t3, 0x90000efe00007000 |
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li a0, 0x60100000 |
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sw a0, 0x10(t3) |
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dli t1, 0x90000e0060100000 |
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li t3, (0x1<<18) |
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not t3, t3 |
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lw a0, 0x54(t1) |
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and a0, a0, t3 |
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sw a0, 0x54(t1) |
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lw a0, 0x58(t1) |
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and a0, a0, t3 |
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sw a0, 0x58(t1) |
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dli t1, 0x90000e0060100000 |
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li a0, 0xff204c |
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sw a0, 0x0(t1) |
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@ -1408,10 +1517,28 @@ cal_one_pcie_x8: |
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or a0, ((PCIE_TRY_GEN2 << 17) | (PCIE_TX_FULL_SWING << 18)) |
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sw a0, 0xc(t3) |
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dli t3, 0x90000efe0700981c |
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lw a1, 0x0(t3) |
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li a0, (0x1 << 26) |
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not a0, a0 |
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and a1, a1, a0 |
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sw a1, 0x0(t3) |
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dli t3, 0x90000efe00009800 |
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li a0, 0x60000000 |
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sw a0, 0x10(t3) |
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dli t1, 0x90000e0060000000 |
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li t3, (0x1<<18) |
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not t3, t3 |
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lw a0, 0x54(t1) |
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and a0, a0, t3 |
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sw a0, 0x54(t1) |
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lw a0, 0x58(t1) |
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and a0, a0, t3 |
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sw a0, 0x58(t1) |
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dli t1, 0x90000e0060000000 |
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li a0, 0xff204c |
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sw a0, 0x0(t1) |
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@ -1451,10 +1578,28 @@ cal_one_pcie_x8: |
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or a0, ((PCIE_TRY_GEN2 << 17) | (PCIE_TX_FULL_SWING << 18)) |
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sw a0, 0xc(t3) |
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dli t3, 0x90000efe0700a01c |
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lw a1, 0x0(t3) |
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li a0, (0x1 << 26) |
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not a0, a0 |
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and a1, a1, a0 |
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sw a1, 0x0(t3) |
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dli t3, 0x90000efe0000a000 |
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li a0, 0x60100000 |
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sw a0, 0x10(t3) |
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dli t1, 0x90000e0060100000 |
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li t3, (0x1<<18) |
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not t3, t3 |
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lw a0, 0x54(t1) |
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and a0, a0, t3 |
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sw a0, 0x54(t1) |
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lw a0, 0x58(t1) |
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and a0, a0, t3 |
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sw a0, 0x58(t1) |
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dli t1, 0x90000e0060100000 |
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li a0, 0xff204c |
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sw a0, 0x0(t1) |
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@ -1552,10 +1697,29 @@ cal_one_pcie_x8: |
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or a0, ((PCIE_TRY_GEN2 << 17) | (PCIE_TX_FULL_SWING << 18)) |
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sw a0, 0xc(t3) |
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dli t3, 0x90000efe0700781c |
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lw a1, 0x0(t3) |
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li a0, (0x1 << 26) |
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not a0, a0 |
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and a1, a1, a0 |
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sw a1, 0x0(t3) |
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dli t3, 0x90000efe00007800 |
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li a0, 0x60000000 |
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sw a0, 0x10(t3) |
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dli t1, 0x90000e0060000000 |
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li t3, (0x1<<18) |
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not t3, t3 |
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lw a0, 0x54(t1) |
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and a0, a0, t3 |
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sw a0, 0x54(t1) |
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lw a0, 0x58(t1) |
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and a0, a0, t3 |
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sw a0, 0x58(t1) |
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dli t1, 0x90000e0060000000 |
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li a0, 0xff204c |
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sw a0, 0x0(t1) |
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@ -1595,10 +1759,28 @@ cal_one_pcie_x8: |
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or a0, ((PCIE_TRY_GEN2 << 17) | (PCIE_TX_FULL_SWING << 18)) |
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sw a0, 0xc(t3) |
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dli t3, 0x90000efe0700801c |
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lw a1, 0x0(t3) |
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li a0, (0x1 << 26) |
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not a0, a0 |
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and a1, a1, a0 |
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sw a1, 0x0(t3) |
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dli t3, 0x90000efe00008000 |
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li a0, 0x60100000 |
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sw a0, 0x10(t3) |
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dli t1, 0x90000e0060100000 |
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li t3, (0x1<<18) |
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not t3, t3 |
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lw a0, 0x54(t1) |
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and a0, a0, t3 |
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sw a0, 0x54(t1) |
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lw a0, 0x58(t1) |
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and a0, a0, t3 |
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sw a0, 0x58(t1) |
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dli t1, 0x90000e0060100000 |
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li a0, 0xff204c |
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sw a0, 0x0(t1) |
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@ -1696,10 +1878,28 @@ cal_one_pcie_x8: |
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or a0, ((PCIE_TRY_GEN2 << 17) | (PCIE_TX_FULL_SWING << 18)) |
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sw a0, 0xc(t3) |
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dli t3, 0x90000efe0700881c |
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lw a1, 0x0(t3) |
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li a0, (0x1 << 26) |
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not a0, a0 |
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and a1, a1, a0 |
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sw a1, 0x0(t3) |
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dli t3, 0x90000efe00008800 |
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li a0, 0x60000000 |
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sw a0, 0x10(t3) |
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dli t1, 0x90000e0060000000 |
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li t3, (0x1<<18) |
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not t3, t3 |
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lw a0, 0x54(t1) |
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and a0, a0, t3 |
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sw a0, 0x54(t1) |
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lw a0, 0x58(t1) |
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and a0, a0, t3 |
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sw a0, 0x58(t1) |
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dli t1, 0x90000e0060000000 |
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li a0, 0xff204c |
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sw a0, 0x0(t1) |
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@ -1739,10 +1939,28 @@ cal_one_pcie_x8: |
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or a0, ((PCIE_TRY_GEN2 << 17) | (PCIE_TX_FULL_SWING << 18)) |
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sw a0, 0xc(t3) |
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dli t3, 0x90000efe0700901c |
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lw a1, 0x0(t3) |
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li a0, (0x1 << 26) |
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not a0, a0 |
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and a1, a1, a0 |
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sw a1, 0x0(t3) |
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dli t3, 0x90000efe00009000 |
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li a0, 0x60100000 |
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sw a0, 0x10(t3) |
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dli t1, 0x90000e0060100000 |
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li t3, (0x1<<18) |
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not t3, t3 |
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lw a0, 0x54(t1) |
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and a0, a0, t3 |
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sw a0, 0x54(t1) |
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lw a0, 0x58(t1) |
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and a0, a0, t3 |
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sw a0, 0x58(t1) |
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dli t1, 0x90000e0060100000 |
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li a0, 0xff204c |
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sw a0, 0x0(t1) |
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