Browse Source

add support for kingston 2G UDIMM at 400MHz

Change-Id: I96b97ed379698fb3ca3b51e1daca156b232a74c6
master
Huang Shuai 9 years ago
committed by zhangbaoqi
parent
commit
60696fe9ae
  1. 4
      Targets/Bonito3a8780e/Bonito/start.S
  2. 7
      pmon/arch/mips/mm/loongson3C_ddr3_leveling.S

4
Targets/Bonito3a8780e/Bonito/start.S

@ -368,12 +368,14 @@ gs_2f_v3_ddr2_cfg:
#ifdef SOFT_CLKSEL
//#define DDR_LOOPC 80 //667Mhz
#define DDR_LOOPC 72 //600
//#define DDR_LOOPC 72 //600
//#define DDR_LOOPC 60 //500MHz
#define DDR_LOOPC 48 //400MHz
#define DDR_REFC 1
#define DDR_DIV 4
// L1_* define both CPU and Node freq simutanleously
//#define L1_LOOPC 80//1000
//#define L1_LOOPC 72//900
#define L1_LOOPC 64//800
//#define L1_LOOPC 48//600

7
pmon/arch/mips/mm/loongson3C_ddr3_leveling.S

@ -38,13 +38,18 @@ ddr3_leveling:
bgt t1, t4, 3f
nop
//<= 500M, for udimm, add rd_oe_start/stop by 0x2 and sub tPHY_RDDATA by 0x1
// for rdimm, only sub tPHY_RDDATA by 0x1
GET_DIMM_TYPE
bnez a1, 4f //RDIMM
nop
//temp code for Kinston 2G UDIMM, at 400MHz, only sub tPHY_RDDATA by 0x1
dli t4, 12
beq t1, t4, 4f
nop
/* identify wheather there is ecc slice */
li t0, 0x8
dli t1, 0x250

Loading…
Cancel
Save