Change the lthalf parameter

Change-Id: Ib93b7401db8bd2c1638c20b3d6ec0a92537c7358

Targets/Bonito3a94w/Bonito/loongson_mc2_param.S

@@ -376,11 +376,11 @@ MC0_DDR3_RDIMM_CTRL_0x1d0: .dword 0x0a020d0502000018
 //0000_0000 pm_tODTL _00000000 pm_tXSRD 0000_0000 pm_tPHY_RDLAT 000_00000 pm_tPHY_WRLAT 000000_00_00000000_00000000 pm_tRAS_max 00_000000 pm_tRAS_min
 MC0_DDR3_RDIMM_CTRL_0x1d8: .dword 0x14050c0408070405
 //_00000000 pm_tXPDLL _00000000 pm_tXP 000_00000 pm_tWR 0000_0000 pm_tRTP 0000_0000 pm_tRL 0000_0000 pm_tWL 0000_0000 pm_tCCD 0000_0000 pm_tWTR
-//MC0_DDR3_RDIMM_CTRL_0x1e0: .dword 0x0503000000000000
-MC0_DDR3_RDIMM_CTRL_0x1e0: .dword 0x0a0a0a0a0a0a0a0a
+MC0_DDR3_RDIMM_CTRL_0x1e0: .dword 0x0503000000000000
+//MC0_DDR3_RDIMM_CTRL_0x1e0: .dword 0x0a0a0a0a0a0a0a0a
 //00_000000 pm_tW2R_diffcs_dly 00_000000 pm_tW2W_diffcs_adj_dly 00_000000 pm_tR2P_sameba_adj_dly 00_000000 pm_tW2P_sameba_adj_dly 00_000000 pm_tR2R_sameba_adj_dly 00_000000 pm_tR2W_sameba_adj_dly 00_000000 pm_tW2R_sameba_adj_dly 00_000000 pm_tW2W_sameba_adj_dly
-//MC0_DDR3_RDIMM_CTRL_0x1e8: .dword 0x030a000000010000
-MC0_DDR3_RDIMM_CTRL_0x1e8: .dword 0x0c0c0a0a0a0a0a0a
+MC0_DDR3_RDIMM_CTRL_0x1e8: .dword 0x030a000000010000
+//MC0_DDR3_RDIMM_CTRL_0x1e8: .dword 0x0c0c0a0a0a0a0a0a
 //00_000000 pm_tR2R_diffcs_adj_dly 00_000000 pm_tR2W_diffcs_dly 00_000000 pm_tR2P_samecs_dly 00_000000 pm_tW2P_samecs_dly 00_000000 pm_tR2R_samecs_adj_dly 00_000000 pm_tR2W_samecs_adj_dly 00_000000 pm_tW2R_samecs_adj_dly 00_000000 pm_tW2W_samecs_adj_dly
 MC0_DDR3_RDIMM_CTRL_0x1f0: .dword 0x000801e4ff000101
 //0000_0000 pm_power_up _00000000 pm_age_step _00000000 pm_tCPDED _00000000 pm_cs_map _00000000 pm_bs_config 00000_000 pm_channel_32 pm_channel_16 pm_nc 0000_0000 pm_pr_r2w 0000000_0 pm_placement_en

Targets/Bonito3a94w/Bonito/start.S

@@ -2154,7 +2154,7 @@ idle1000:
 #######################################
 #include "ddr_dir/ls3A8_ddr_config.S"
 #ifdef DDR3_DIMM
-#include "loongson3C_ddr3_leveling.S"
+#include "ddr_dir/loongson3C_ddr3_leveling.S"
 #endif
 #ifdef ARB_LEVEL
 #include "ddr_dir/ARB_level_new.S"

pmon/arch/mips/mm/loongson3C_ddr3_leveling.S

@@ -8,7 +8,7 @@
 #include "ddr_leveling_define.h"
 #define	PREMBLE_CHECK_DEBUG
 //#define	PRINT_PREMBLE_CHECK
-#define PRINT_DDR_LEVELING
+//#define PRINT_DDR_LEVELING
 #define	FILTER_CHECK
 //#define	FIND_PREMBLE_LENGTH
 //#define LVL_DEBUG
@@ -4778,7 +4778,7 @@ glvl_check_premble_end:
 1:
 
 //set rddqs_lt_half
-	lb		a0, 0x0(t1)
+	lb		a0, 0x10(t1)
 	dli		t4, 0x7f
 	and		a0, a0, t4
 #ifdef DDR_DLL_BYPASS
@@ -4787,14 +4787,20 @@ glvl_check_premble_end:
     daddu   t5, t5, 0x2
     divu    a0, a0, t5 //get dll_gate, no bypass mode
 #endif
- 	lb		a1, 0x1(t1)
+ 	lb		a1, 0x11(t1)
 	daddu	a0, a0, a1
 	and		a0, a0, t4
-	bgeu	a0, 0x40, rddqs_lthalf_set0
+#if 0
+	move	a1, a0
+	bal		hexserial
+	nop
+	move	a0, a1
+#endif
+	bgeu	a0, 0x3a, rddqs_lthalf_set1
 	nop
-	bltu	a0,	0x0, rddqs_lthalf_set0
+	bltu	a0,	0x1a, rddqs_lthalf_set1
 	nop
-	b		rddqs_lthalf_set1
+	b		rddqs_lthalf_set0
 	nop
 rddqs_lthalf_set0:
 	dsubu	t4, t1, 0x8
@@ -4991,8 +4997,8 @@ premble_check_length:
 	nop
 
 #endif
-	b		gate_leveling_exit
-	nop
+	b		gate_leveling_exit               //-------------------------the after code is not effect-until gate leveling exit-------------------------------------------
+	nop										//--------------------------------------!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!-------------------------------------------------------
 
 #endif
 
@@ -5130,8 +5136,8 @@ wait_init_done0:
     nop
     daddu   t0, t0, 0x1
 1:
-    dli     a2, 0x00
-    dli     a3, 0x40
+    dli     a2, 0x1a
+    dli     a3, 0x3a
     dli     t1, 0x018
     or      t1, t1, t8
 rddqs_lt_half:
@@ -5155,11 +5161,17 @@ rddqs_lt_half:
     dsrl    a1, a1, 8  //get dll_wrdata
     daddu   a0, a0, a1
     and     a0, a0, t6
-    bgeu    a0, a3, rddqs_lt_half_set0//because the rd gate edge is 0x2
+#if 0
+	move	a1, a0
+	bal		hexserial
+	nop
+	move	a0, a1
+#endif
+    bgeu    a0, a3, rddqs_lt_half_set1//because the rd gate edge is 0x2
     nop
-    bltu    a0, a2, rddqs_lt_half_set0
+    bltu    a0, a2, rddqs_lt_half_set1
     nop
-    b       rddqs_lt_half_set1
+    b       rddqs_lt_half_set0
     nop
 rddqs_lt_half_set0:
     dsubu   t2, t1, 0x18