ls2k s3 resume check ddr only if s3.

Change-Id: Ia74ce8a70f0b153ec02b35a8d93e33d8e2e8000f
Signed-off-by: Chong Qiao <qiaochong@loongson.cn>

Targets/LS2K/ls2k/ddr_dir/lsmc_config_param.S

@@ -43,7 +43,12 @@ ddr2_config:
 	sd v0, 0x140(t8)	
 1:
 #endif
-
+#ifdef DDR_RESET_REVERT
+#define DDR_PARAM_150_RESET 0x0002000000000000
+#else
+#define DDR_PARAM_150_RESET 0
+#endif
+#ifdef LS2K_STR
     /*If S3 mode: configure memory controller, make sure the memory reset is high*/
     ld      t1, 0x150(t8)
     dli	    a0, (0xff<<48)
@@ -56,18 +61,19 @@ ddr2_config:
     bne	    a1, v0, 1f
     nop
     
-    dli	    a0, (0x01<<48)
+    dli	    a0, (0x01<<48) ^ DDR_PARAM_150_RESET 
     b	    2f
     nop
 
 1:
-    dli	    a0, (0x02<<48)
+    dli	    a0, (0x02<<48) ^ DDR_PARAM_150_RESET 
 2:
     or	    t1, t1, a0
     sd      t1, 0x150(t8)
     /*clear mem_ctrl_flag*/
     dli     a0, 0x900000001fe07050
     sw      zero, 0x0(a0) 
+#endif
 #if 0 
 //autoset param registers
 set_tMOD:		

Targets/LS2K/ls2k/loongson_mc2_param.S

@@ -6,8 +6,16 @@ ddr2_reg_data_mc1:
 ddr2_RDIMM_reg_data:
 ddr2_RDIMM_reg_data_mc1:
 
+#ifdef LS2K_STR
+#define DDR_PARAM_150_RESET 0x0002000000000000
+#else
+#define DDR_PARAM_150_RESET 0
+#endif
+
 #ifdef DDR_RESET_REVERT
-#define DDR_PARAM_150 0x00000000f0020000   //reset pad
+#define DDR_PARAM_150 0x00000000f0020000 ^ DDR_PARAM_150_RESET  //bit48 reset pad
+#else
+#define DDR_PARAM_150 0x00020000f0020000 ^ DDR_PARAM_150_RESET   //bit48 reset pad
 #endif
 
 #ifndef DDR_PARAM_018