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change ddr parameter for 3a82h from 3a8780e to bring up ddr at 600MHz, now still 

has some errors(mostly at 35bit) at 600MHz, only testd MC0

fix board info for 3a2000 and replace cpu freq with bogoMIPS

Change-Id: I2d937ebb643eff85a52f75c62639f643050fe52f
master
Huang Shuai 10 years ago
committed by Huang Pei
parent
5cfd7f3e2c
commit
76ba908937
3 changed files with 71 additions and 39 deletions
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  1. 74
      Targets/Bonito3a82h/Bonito/loongson_mc2_param.S
  2. 4
      Targets/Bonito3a82h/Bonito/start.S
  3. 32
      Targets/Bonito3a82h/Bonito/tgt_machdep.c

74
Targets/Bonito3a82h/Bonito/loongson_mc2_param.S
View File

@ -21,78 +21,78 @@ MC0_DDR3_CTRL_0x010: .dword 0x0000000000000000
//XXXX pm_dll_value_8(RD) XXXX pm_dll_value_7 (RD) XXXX pm_dll_value_6(RD) XXXX pm_dll_value_5(RD)
//MC0_DDR3_CTRL_0x018: .dword 0x5252525216100000
//MC0_DDR3_CTRL_0x018: .dword 0x4040404016100000
//MC0_DDR3_CTRL_0x018: .dword 0x3030303016100000
MC0_DDR3_CTRL_0x018: .dword 0x2525252516100000
MC0_DDR3_CTRL_0x018: .dword 0x3030303016100000
//MC0_DDR3_CTRL_0x018: .dword 0x2525252516100000
//_00000000 pm_dll_ck_3 _00000000 pm_dll_ck_2 _00000000 pm_dll_ck_1 _00000000 pm_dll_ck_0 _00000000 pm_dll_increment _00000000 pm_dll_start_point _0000000_0 pm_dll_bypass _0000000_0 pm_init_start
MC0_DDR3_CTRL_0x020: .dword 0x0201000301000000
MC0_DDR3_CTRL_0x020: .dword 0x0201000201000000
//0000_0000 pm_dq_oe_end_0 0000_0000 pm_dq_oe_begin_0 000000_00 pm_dq_stop_edge_0 000000_00 pm_dq_start_edge_0 0000000_0 pm_rddata_delay_0 0000000_0 pm_rddqs_lt_half_0 0000000_0 pm_wrdqs_lt_half_0 0000000_0 pm_wrdq_lt_half_0
MC0_DDR3_CTRL_0x028: .dword 0x0303020202010101
MC0_DDR3_CTRL_0x028: .dword 0x0303000002010100
//0000_0000 pm_rd_oe_end_0 0000_0000 pm_rd_oe_begin_0 000000_00 pm_rd_stop_edge_0 000000_00 pm_rd_start_edge_0 0000_0000 pm_dqs_oe_end_0 0000_0000 pm_dqs_oe_begin_0 000000_00 pm_dqs_stop_edge_0 000000_00 pm_dqs_start_edge_0
MC0_DDR3_CTRL_0x030: .dword 0x0000000004030000
MC0_DDR3_CTRL_0x030: .dword 0x0000000003020202
//hXXXXXX (RD) 0000000_0 pm_wrdq_clkdelay_0 0000_0000 pm_odt_oe_end_0 0000_0000 pm_odt_oe_begin_0 000000_00 pm_odt_stop_edge_0 000000_00 pm_odt_start_edge_0
MC0_DDR3_CTRL_0x038: .dword 0x0000002020056500
//hXXXXXX (RD) _00000000 pm_dll_rddqs_n_0 _00000000 pm_dll_rddqs_p_0 _00000000 pm_dll_wrdqs_0 _00000000 pm_dll_wrdata_0 _00000000 pm_dll_gate_0
MC0_DDR3_CTRL_0x040: .dword 0x0201000301000000
MC0_DDR3_CTRL_0x040: .dword 0x0201000201000000
//0000_0000 pm_dq_oe_end_1 0000_0000 pm_dq_oe_begin_1 000000_00 pm_dq_stop_edge_1 000000_00 pm_dq_start_edge_1 0000000_0 pm_rddata_delay_1 0000000_0 pm_rddqs_lt_half_1 0000000_0 pm_wrdqs_lt_half_1 0000000_0 pm_wrdq_lt_half_1
MC0_DDR3_CTRL_0x048: .dword 0x0303020202010101
MC0_DDR3_CTRL_0x048: .dword 0x0303000002010100
//0000_0000 pm_rd_oe_end_1 0000_0000 pm_rd_oe_begin_1 000000_00 pm_rd_stop_edge_1 000000_00 pm_rd_start_edge_1 0000_0000 pm_dqs_oe_end_1 0000_0000 pm_dqs_oe_begin_1 000000_00 pm_dqs_stop_edge_1 000000_00 pm_dqs_start_edge_1
MC0_DDR3_CTRL_0x050: .dword 0x0000000004030000
MC0_DDR3_CTRL_0x050: .dword 0x0000000003020202
//hXXXXXX (RD) 0000000_0 pm_wrdq_clkdelay_1 0000_0000 pm_odt_oe_end_1 0000_0000 pm_odt_oe_begin_1 000000_00 pm_odt_stop_edge_1 000000_00 pm_odt_start_edge_1
MC0_DDR3_CTRL_0x058: .dword 0x0000002020056500
//hXXXXXX (RD) _00000000 pm_dll_rddqs_n_1 _00000000 pm_dll_rddqs_p_1 _00000000 pm_dll_wrdqs_1 _00000000 pm_dll_wrdata_1 _00000000 pm_dll_gate_1
MC0_DDR3_CTRL_0x060: .dword 0x0201000301000000
MC0_DDR3_CTRL_0x060: .dword 0x0201000201000000
//0000_0000 pm_dq_oe_end_2 0000_0000 pm_dq_oe_begin_2 000000_00 pm_dq_stop_edge_2 000000_00 pm_dq_start_edge_2 0000000_0 pm_rddata_delay_2 0000000_0 pm_rddqs_lt_half_2 0000000_0 pm_wrdqs_lt_half_2 0000000_0 pm_wrdq_lt_half_2
MC0_DDR3_CTRL_0x068: .dword 0x0303020202010101
MC0_DDR3_CTRL_0x068: .dword 0x0303000002010100
//0000_0000 pm_rd_oe_end_2 0000_0000 pm_rd_oe_begin_2 000000_00 pm_rd_stop_edge_2 000000_00 pm_rd_start_edge_2 0000_0000 pm_dqs_oe_end_2 0000_0000 pm_dqs_oe_begin_2 000000_00 pm_dqs_stop_edge_2 000000_00 pm_dqs_start_edge_2
MC0_DDR3_CTRL_0x070: .dword 0x0000000004030000
MC0_DDR3_CTRL_0x070: .dword 0x0000000003020202
//hXXXXXX (RD) 0000000_0 pm_wrdq_clkdelay_2 0000_0000 pm_odt_oe_end_2 0000_0000 pm_odt_oe_begin_2 000000_00 pm_odt_stop_edge_2 000000_00 pm_odt_start_edge_2
MC0_DDR3_CTRL_0x078: .dword 0x0000002020056500
//hXXXXXX (RD) _00000000 pm_dll_rddqs_n_2 _00000000 pm_dll_rddqs_p_2 _00000000 pm_dll_wrdqs_2 _00000000 pm_dll_wrdata_2 _00000000 pm_dll_gate_2
MC0_DDR3_CTRL_0x080: .dword 0x0201000301000000
MC0_DDR3_CTRL_0x080: .dword 0x0201000201000000
//0000_0000 pm_dq_oe_end_3 0000_0000 pm_dq_oe_begin_3 000000_00 pm_dq_stop_edge_3 000000_00 pm_dq_start_edge_3 0000000_0 pm_rddata_delay_3 0000000_0 pm_rddqs_lt_half_3 0000000_0 pm_wrdqs_lt_half_3 0000000_0 pm_wrdq_lt_half_3
MC0_DDR3_CTRL_0x088: .dword 0x0303020202010101
MC0_DDR3_CTRL_0x088: .dword 0x0303000002010100
//0000_0000 pm_rd_oe_end_3 0000_0000 pm_rd_oe_begin_3 000000_00 pm_rd_stop_edge_3 000000_00 pm_rd_start_edge_3 0000_0000 pm_dqs_oe_end_3 0000_0000 pm_dqs_oe_begin_3 000000_00 pm_dqs_stop_edge_3 000000_00 pm_dqs_start_edge_3
MC0_DDR3_CTRL_0x090: .dword 0x0000000004030000
MC0_DDR3_CTRL_0x090: .dword 0x0000000003020202
//hXXXXXX (RD) 0000000_0 pm_wrdq_clkdelay_3 0000_0000 pm_odt_oe_end_3 0000_0000 pm_odt_oe_begin_3 000000_00 pm_odt_stop_edge_3 000000_00 pm_odt_start_edge_3
MC0_DDR3_CTRL_0x098: .dword 0x0000002020056500
//hXXXXXX (RD) _00000000 pm_dll_rddqs_n_3 _00000000 pm_dll_rddqs_p_3 _00000000 pm_dll_wrdqs_3 _00000000 pm_dll_wrdata_3 _00000000 pm_dll_gate_3
MC0_DDR3_CTRL_0x0a0: .dword 0x0201000301000000
MC0_DDR3_CTRL_0x0a0: .dword 0x0201000201000000
//0000_0000 pm_dq_oe_end_4 0000_0000 pm_dq_oe_begin_4 000000_00 pm_dq_stop_edge_4 000000_00 pm_dq_start_edge_4 0000000_0 pm_rddata_delay_4 0000000_0 pm_rddqs_lt_half_4 0000000_0 pm_wrdqs_lt_half_4 0000000_0 pm_wrdq_lt_half_4
MC0_DDR3_CTRL_0x0a8: .dword 0x0303020202010101
MC0_DDR3_CTRL_0x0a8: .dword 0x0303000002010100
//0000_0000 pm_rd_oe_end_4 0000_0000 pm_rd_oe_begin_4 000000_00 pm_rd_stop_edge_4 000000_00 pm_rd_start_edge_4 0000_0000 pm_dqs_oe_end_4 0000_0000 pm_dqs_oe_begin_4 000000_00 pm_dqs_stop_edge_4 000000_00 pm_dqs_start_edge_4
MC0_DDR3_CTRL_0x0b0: .dword 0x0000000004030000
MC0_DDR3_CTRL_0x0b0: .dword 0x0000000003020202
//hXXXXXX (RD) 0000000_0 pm_wrdq_clkdelay_4 0000_0000 pm_odt_oe_end_4 0000_0000 pm_odt_oe_begin_4 000000_00 pm_odt_stop_edge_4 000000_00 pm_odt_start_edge_4
MC0_DDR3_CTRL_0x0b8: .dword 0x0000002020056500
//hXXXXXX (RD) _00000000 pm_dll_rddqs_n_4 _00000000 pm_dll_rddqs_p_4 _00000000 pm_dll_wrdqs_4 _00000000 pm_dll_wrdata_4 _00000000 pm_dll_gate_4
MC0_DDR3_CTRL_0x0c0: .dword 0x0201000301000000
MC0_DDR3_CTRL_0x0c0: .dword 0x0201000201000000
//0000_0000 pm_dq_oe_end_5 0000_0000 pm_dq_oe_begin_5 000000_00 pm_dq_stop_edge_5 000000_00 pm_dq_start_edge_5 0000000_0 pm_rddata_delay_5 0000000_0 pm_rddqs_lt_half_5 0000000_0 pm_wrdqs_lt_half_5 0000000_0 pm_wrdq_lt_half_5
MC0_DDR3_CTRL_0x0c8: .dword 0x0303020202010101
MC0_DDR3_CTRL_0x0c8: .dword 0x0303000002010100
//0000_0000 pm_rd_oe_end_5 0000_0000 pm_rd_oe_begin_5 000000_00 pm_rd_stop_edge_5 000000_00 pm_rd_start_edge_5 0000_0000 pm_dqs_oe_end_5 0000_0000 pm_dqs_oe_begin_5 000000_00 pm_dqs_stop_edge_5 000000_00 pm_dqs_start_edge_5
MC0_DDR3_CTRL_0x0d0: .dword 0x0000000004030000
MC0_DDR3_CTRL_0x0d0: .dword 0x0000000003020202
//hXXXXXX (RD) 0000000_0 pm_wrdq_clkdelay_5 0000_0000 pm_odt_oe_end_5 0000_0000 pm_odt_oe_begin_5 000000_00 pm_odt_stop_edge_5 000000_00 pm_odt_start_edge_5
MC0_DDR3_CTRL_0x0d8: .dword 0x0000002020056500
//hXXXXXX (RD) _00000000 pm_dll_rddqs_n_5 _00000000 pm_dll_rddqs_p_5 _00000000 pm_dll_wrdqs_5 _00000000 pm_dll_wrdata_5 _00000000 pm_dll_gate_5
MC0_DDR3_CTRL_0x0e0: .dword 0x0201000301000000
MC0_DDR3_CTRL_0x0e0: .dword 0x0201000201000000
//0000_0000 pm_dq_oe_end_6 0000_0000 pm_dq_oe_begin_6 000000_00 pm_dq_stop_edge_6 000000_00 pm_dq_start_edge_6 0000000_0 pm_rddata_delay_6 0000000_0 pm_rddqs_lt_half_6 0000000_0 pm_wrdqs_lt_half_6 0000000_0 pm_wrdq_lt_half_6
MC0_DDR3_CTRL_0x0e8: .dword 0x0303020202010101
MC0_DDR3_CTRL_0x0e8: .dword 0x0303000002010100
//0000_0000 pm_rd_oe_end_6 0000_0000 pm_rd_oe_begin_6 000000_00 pm_rd_stop_edge_6 000000_00 pm_rd_start_edge_6 0000_0000 pm_dqs_oe_end_6 0000_0000 pm_dqs_oe_begin_6 000000_00 pm_dqs_stop_edge_6 000000_00 pm_dqs_start_edge_6
MC0_DDR3_CTRL_0x0f0: .dword 0x0000000004030000
MC0_DDR3_CTRL_0x0f0: .dword 0x0000000003020202
//hXXXXXX (RD) 0000000_0 pm_wrdq_clkdelay_6 0000_0000 pm_odt_oe_end_6 0000_0000 pm_odt_oe_begin_6 000000_00 pm_odt_stop_edge_6 000000_00 pm_odt_start_edge_6
MC0_DDR3_CTRL_0x0f8: .dword 0x0000002020056500
//hXXXXXX (RD) _00000000 pm_dll_rddqs_n_6 _00000000 pm_dll_rddqs_p_6 _00000000 pm_dll_wrdqs_6 _00000000 pm_dll_wrdata_6 _00000000 pm_dll_gate_6
MC0_DDR3_CTRL_0x100: .dword 0x0201000301000000
MC0_DDR3_CTRL_0x100: .dword 0x0201000201000000
//0000_0000 pm_dq_oe_end_7 0000_0000 pm_dq_oe_begin_7 000000_00 pm_dq_stop_edge_7 000000_00 pm_dq_start_edge_7 0000000_0 pm_rddata_delay_7 0000000_0 pm_rddqs_lt_half_7 0000000_0 pm_wrdqs_lt_half_7 0000000_0 pm_wrdq_lt_half_7
MC0_DDR3_CTRL_0x108: .dword 0x0303020202010101
MC0_DDR3_CTRL_0x108: .dword 0x0303000002010100
//0000_0000 pm_rd_oe_end_7 0000_0000 pm_rd_oe_begin_7 000000_00 pm_rd_stop_edge_7 000000_00 pm_rd_start_edge_7 0000_0000 pm_dqs_oe_end_7 0000_0000 pm_dqs_oe_begin_7 000000_00 pm_dqs_stop_edge_7 000000_00 pm_dqs_start_edge_7
MC0_DDR3_CTRL_0x110: .dword 0x0000000004030000
MC0_DDR3_CTRL_0x110: .dword 0x0000000003020202
//hXXXXXX (RD) 0000000_0 pm_wrdq_clkdelay_7 0000_0000 pm_odt_oe_end_7 0000_0000 pm_odt_oe_begin_7 000000_00 pm_odt_stop_edge_7 000000_00 pm_odt_start_edge_7
MC0_DDR3_CTRL_0x118: .dword 0x0000002020056500
//hXXXXXX (RD) _00000000 pm_dll_rddqs_n_7 _00000000 pm_dll_rddqs_p_7 _00000000 pm_dll_wrdqs_7 _00000000 pm_dll_wrdata_7 _00000000 pm_dll_gate_7
MC0_DDR3_CTRL_0x120: .dword 0x0201000301000000
MC0_DDR3_CTRL_0x120: .dword 0x0201000201000000
//0000_0000 pm_dq_oe_end_8 0000_0000 pm_dq_oe_begin_8 000000_00 pm_dq_stop_edge_8 000000_00 pm_dq_start_edge_8 0000000_0 pm_rddata_delay_8 0000000_0 pm_rddqs_lt_half_8 0000000_0 pm_wrdqs_lt_half_8 0000000_0 pm_wrdq_lt_half_8
MC0_DDR3_CTRL_0x128: .dword 0x0303020202010101
MC0_DDR3_CTRL_0x128: .dword 0x0303000002010100
//0000_0000 pm_rd_oe_end_8 0000_0000 pm_rd_oe_begin_8 000000_00 pm_rd_stop_edge_8 000000_00 pm_rd_start_edge_8 0000_0000 pm_dqs_oe_end_8 0000_0000 pm_dqs_oe_begin_8 000000_00 pm_dqs_stop_edge_8 000000_00 pm_dqs_start_edge_8
MC0_DDR3_CTRL_0x130: .dword 0x0000000004030000
MC0_DDR3_CTRL_0x130: .dword 0x0000000003020202
//hXXXXXX (RD) 0000000_0 pm_wrdq_clkdelay_8 0000_0000 pm_odt_oe_end_8 0000_0000 pm_odt_oe_begin_8 000000_00 pm_odt_stop_edge_8 000000_00 pm_odt_start_edge_8
MC0_DDR3_CTRL_0x138: .dword 0x00000020207f6000
//hXXXXXX (RD) _00000000 pm_dll_rddqs_n_8 _00000000 pm_dll_rddqs_p_8 _00000000 pm_dll_wrdqs_8 _00000000 pm_dll_wrdata_8 _00000000 pm_dll_gate_8
@ -124,21 +124,21 @@ MC0_DDR3_CTRL_0x190: .dword 0x0000000000000000
//_00000000_00000000 pm_cmd_a 00000_000 pm_cmd_ba 00000_000 pm_cmd_cmd 0000_0000 pm_cmd_cs 0000000_0 pm_status_cmd(RD) 0000000_0 pm_cmd_req(WR) 0000000_0 pm_command
MC0_DDR3_CTRL_0x198: .dword 0x0000000000000000
//00000000 00000000 0000_0000 pm_status_sref(RD) 0000_0000 pm_srefresh_req 0000000_0 pm_pre_all_done(RD) 0000000_0 pm_pre_all_req(WR) 0000000_0 pm_mrs_done(RD) 0000000_0 pm_mrs_req(WR)
MC0_DDR3_CTRL_0x1a0: .dword 0x0000000800060940
MC0_DDR3_CTRL_0x1a0: .dword 0x0000001000060d30
//_00000000_00000000 pm_mr_3_cs_0 _00000000_00000000 pm_mr_2_cs_0 _00000000_00000000 pm_mr_1_cs_0 _00000000_00000000 pm_mr_0_cs_0
MC0_DDR3_CTRL_0x1a8: .dword 0x0000000800060940
MC0_DDR3_CTRL_0x1a8: .dword 0x0000001000060d30
//_00000000_00000000 pm_mr_3_cs_1 _00000000_00000000 pm_mr_2_cs_1 _00000000_00000000 pm_mr_1_cs_1 _00000000_00000000 pm_mr_0_cs_1
MC0_DDR3_CTRL_0x1b0: .dword 0x0000000800060940
MC0_DDR3_CTRL_0x1b0: .dword 0x0000001000060d30
//_00000000_00000000 pm_mr_3_cs_2 _00000000_00000000 pm_mr_2_cs_2 _00000000_00000000 pm_mr_1_cs_2 _00000000_00000000 pm_mr_0_cs_2
MC0_DDR3_CTRL_0x1b8: .dword 0x0000000800060940
MC0_DDR3_CTRL_0x1b8: .dword 0x0000001000060d30
//_00000000_00000000 pm_mr_3_cs_3 _00000000_00000000 pm_mr_2_cs_3 _00000000_00000000 pm_mr_1_cs_3 _00000000_00000000 pm_mr_0_cs_3
MC0_DDR3_CTRL_0x1c0: .dword 0x1b425b0802041905
MC0_DDR3_CTRL_0x1c0: .dword 0x3030c80c03042005
//_00000000 pm_tRESET _00000000 pm_tCKE _00000000 pm_tXPR _00000000 pm_tMOD _00000000 pm_tZQCL _00000000 pm_tZQ_CMD _00000000 pm_tWLDQSEN 000_00000 pm_tRDDATA
MC0_DDR3_CTRL_0x1c8: .dword 0x10040808103a4080
MC0_DDR3_CTRL_0x1c8: .dword 0x11070707154a4080
//00_000000 pm_tFAW 0000_0000 pm_tRRD 0000_0000 pm_tRCD _00000000 pm_tRP _00000000 pm_tREF _00000000 pm_tRFC _00000000 pm_tZQCS _00000000 pm_tZQperiod
MC0_DDR3_CTRL_0x1d0: .dword 0x0802090302000014
MC0_DDR3_CTRL_0x1d0: .dword 0x0a02090402000019
//0000_0000 pm_tODTL _00000000 pm_tXSRD 0000_0000 pm_tPHY_RDLAT 000_00000 pm_tPHY_WRLAT 000000_00_00000000_00000000 pm_tRAS_max 00_000000 pm_tRAS_min
MC0_DDR3_CTRL_0x1d8: .dword 0x0d04080408060404
MC0_DDR3_CTRL_0x1d8: .dword 0x14050c0607070406
//_00000000 pm_tXPDLL _00000000 pm_tXP 000_00000 pm_tWR 0000_0000 pm_tRTP 0000_0000 pm_tRL 0000_0000 pm_tWL 0000_0000 pm_tCCD 0000_0000 pm_tWTR
MC0_DDR3_CTRL_0x1e0: .dword 0x0503000000000000
//00_000000 pm_tW2R_diffcs_dly 00_000000 pm_tW2W_diffcs_adj_dly 00_000000 pm_tR2P_sameba_adj_dly 00_000000 pm_tW2P_sameba_adj_dly 00_000000 pm_tR2R_sameba_adj_dly 00_000000 pm_tR2W_sameba_adj_dly 00_000000 pm_tW2R_sameba_adj_dly 00_000000 pm_tW2W_sameba_adj_dly

4
Targets/Bonito3a82h/Bonito/start.S
View File

@ -354,10 +354,10 @@ gs_2f_v3_ddr2_cfg:
//#define DDR_LOOPC 80 //330MHz
//#define DDR_LOOPC 48 //400MHz
//#define DDR_LOOPC 28 //466MHz
#define DDR_LOOPC 60 //500MHz
//#define DDR_LOOPC 60 //500MHz
//#define DDR_LOOPC 32 //533MHz
//#define DDR_LOOPC 34 //566MHz
//#define DDR_LOOPC 72 //600MHz
#define DDR_LOOPC 72 //600MHz
//#define DDR_LOOPC 38 //633MHz
#define DDR_REFC 1
//#define DDR_DIV 8

32
Targets/Bonito3a82h/Bonito/tgt_machdep.c
View File

@ -2857,3 +2857,35 @@ void print_mem_freq(void)
printf("sw selected! mem@ %dMhz\n", (mem_sw_freq_mul() * mem_ref_clock)/mem_sw_freq_div());
}
extern struct interface_info g_board;
struct board_devices *board_devices_info()
{
struct board_devices *bd = &g_board;
strcpy(bd->name,"Loongson-3A2000-2H-1w-V0.7-demo");
bd->num_resources = 10;
return bd;
}
void print_cpu_info()
{
int cycles1, cycles2;
int bogo;
int loops = 1 << 18;
int freq = tgt_pipefreq() / 1000000;
printf("Copyright 2000-2002, Opsycon AB, Sweden.\n");
printf("Copyright 2005, ICT CAS.\n");
printf("CPU %s ", md_cpuname());
cycles1 = (int)read_c0_count();
__loop_delay(loops);
cycles2 = (int)read_c0_count();
bogo = freq * loops / (cycles2 - cycles1);
printf("BogoMIPS: %d\n", bogo);
}

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