Fix PCIE_G0/G1/H PHY cfg address mistake and Fix HT stuck problem again.

1. Current code makes a mistake on PCIE_G0/G1/H PHY cfg address, which will
cause trouble if these three PORTs are not simultaneously enabled or disabled.
2. Modify the setup ht link process to wait HT link status infinately.
The start.S only print out the WARNING info(if any) but not stall the cpu.

Change-Id: Ic71b6e3db4c67063612e54a2ebdac362bec94438

Targets/Bonito3a3000_7a/Bonito/start.S

@@ -601,18 +601,18 @@ bsp_start:
     move    a1, t2
     bal     reset_ht_link
     nop
-    li      a0, 0x0303
+    li      a0, 0xf3f3
     and     a0, a0, v0
     beqz    a0, 8f
     nop
     move    t8, v0
-    TTYDBG("!!!LS3A-7A link fail. fail status: ")
+    TTYDBG("!!!LS3A-7A link error occur. Error status: ")
     move    a0, t8
     bal     hexserial
     nop
-1:
-    b       1b
-    nop
+//1:
+//    b       1b
+//    nop
 8:
     TTYDBG("LS3A-7A linkup.")
 //setup LS3A - 7A HT link done.

pmon/arch/mips/ls7a/ls3a7a_setup_ht_link.S

@@ -432,11 +432,9 @@ reset_ht_link:
     bnez    t5, 2f
     nop
     TTYDBG("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b=")
-    TTYDBG("Wait HT bus down fail!\r\n")
-    //failed more than given time, set fail mark and break
+    li      t5, 0x1f
+    //failed more than given time, set fail mark
     or      t8, t8, (0x1 << HT1_LINKDOWN_FAIL_OFFSET + N1_OFFSET)
-    b       88f
-    nop
 2:
     lw      a0, 0x44(t2)
     li      a1, 0x20
@@ -470,11 +468,9 @@ reset_ht_link:
     bnez    t5, 2f
     nop
     TTYDBG("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b=")
-    TTYDBG("Wait HT bus down fail!\r\n")
-    //failed more than given time, set fail mark and break
+    li      t5, 0x1f
+    //failed more than given time, set fail mark
     or      t8, t8, (0x1 << HT1_LINKDOWN_FAIL_OFFSET)
-    b       88f
-    nop
 2:
     lw      a0, 0x44(t0)
     li      a1, 0x20
@@ -520,10 +516,8 @@ reset_ht_link:
     bnez    t5, 2f
     nop
     TTYDBG("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b=")
-    TTYDBG("Wait HT bus up fail!\r\n")
+    li      t5, 0x1f
     or      t8, t8, (0x1 << HT1_LINKUP_FAIL_OFFSET + N1_OFFSET)
-    b       88f
-    nop
 2:
     lw      a0, 0x44(t2)
     li      a1, 0x20
@@ -547,10 +541,8 @@ reset_ht_link:
     bnez    t5, 2f
     nop
     TTYDBG("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b=")
-    TTYDBG("Wait HT bus up fail!\r\n")
+    li      t5, 0x1f
     or      t8, t8, (0x1 << HT1_LINKUP_FAIL_OFFSET)
-    b       88f
-    nop
 2:
     lw      a0, 0x44(t0)
     li      a1, 0x20
@@ -612,8 +604,6 @@ reset_ht_link:
     nop
     or      t8, t8, (0x1 << HT1_CPU_CRC_FAIL_OFFSET)
     li      t5, MAX_HT_CRC_ERR_COUNT
-    //b       88f
-    //nop
 2:
     lw      a0, 0x44(t0)
     li      a1, 0x300
@@ -642,8 +632,6 @@ reset_ht_link:
     nop
     or      t8, t8, (0x1 << HT1_SB_CRC_FAIL_OFFSET)
     li      t5, MAX_HT_CRC_ERR_COUNT
-    //b       88f
-    //nop
 2:
     lw      a0, 0x44(t1)
     li      a1, 0x300
@@ -675,8 +663,6 @@ reset_ht_link:
     nop
     or      t8, t8, (0x1 << HT1_CPU_CRC_FAIL_OFFSET + N1_OFFSET)
     li      t5, MAX_HT_CRC_ERR_COUNT
-    //b       88f
-    //nop
 2:
     lw      a0, 0x44(t2)
     li      a1, 0x300
@@ -705,8 +691,6 @@ reset_ht_link:
     nop
     or      t8, t8, (0x1 << HT1_SB_CRC_FAIL_OFFSET + N1_OFFSET)
     li      t5, MAX_HT_CRC_ERR_COUNT
-    //b       88f
-    //nop
 2:
     lw      a0, 0x44(t3)
     li      a1, 0x300

pmon/arch/mips/ls7a/ls7a_init.S

@@ -404,7 +404,7 @@
 #endif
 
 #if (!(LS7A_PCIE_G0_P0_DISABLE && LS7A_PCIE_G0_P1_DISABLE))
-    daddu   a0, t0, 0x5d0
+    daddu   a0, t0, 0x5f0
     li      a1, 0x403f1002
     bal     ls7a_phy_cfg_write
     nop
@@ -418,7 +418,7 @@
     bal     ls7a_phy_cfg_write
     nop
 
-    daddu   a0, t0, 0x5d8
+    daddu   a0, t0, 0x5f8
     li      a1, 0x403f1002
     bal     ls7a_phy_cfg_write
     nop
@@ -439,7 +439,7 @@
 #endif
 
 #if (!(LS7A_PCIE_G1_P0_DISABLE && LS7A_PCIE_G1_P1_DISABLE))
-    daddu   a0, t0, 0x5f0
+    daddu   a0, t0, 0x610
     li      a1, 0x403f1002
     bal     ls7a_phy_cfg_write
     nop
@@ -453,7 +453,7 @@
     bal     ls7a_phy_cfg_write
     nop
 
-    daddu   a0, t0, 0x5f8
+    daddu   a0, t0, 0x618
     li      a1, 0x403f1002
     bal     ls7a_phy_cfg_write
     nop
@@ -474,7 +474,7 @@
 #endif
 
 #if (!(LS7A_PCIE_H_P0_DISABLE && LS7A_PCIE_H_P1_DISABLE))
-    daddu   a0, t0, 0x610
+    daddu   a0, t0, 0x5d0
     li      a1, 0x403f1002
     bal     ls7a_phy_cfg_write
     nop
@@ -488,7 +488,7 @@
     bal     ls7a_phy_cfg_write
     nop
 
-    daddu   a0, t0, 0x618
+    daddu   a0, t0, 0x5d8
     li      a1, 0x403f1002
     bal     ls7a_phy_cfg_write
     nop