2K:set attr&td to 0 for PCIE MEM and CFG access and set no-datalength-mismatch check

Change-Id: Iaf90f780a11ec2663e8f12bee30a05c5c6e8e7b3

Targets/LS2K/ls2k/start.S

@@ -479,6 +479,13 @@ cp0_main:
 	or	t1, 0x20000
 	sw	t1, 0x0(t0)
 
+	dli	t0, 0x900000fe0700681c
+    lw  t2, 0x0(t0)
+    li  t1, (0x1 << 26)
+    or  t2, t1
+    sw  t2, 0x0(t0)
+
+
 	dli	t0, 0x900000fe00006800
 	li	t1, 0x10000000
 	sw	t1, 0x10(t0)
@@ -487,6 +494,16 @@ cp0_main:
 	li      t1, 0x10000000
 	or	t0, t0, t1
 
+    li  t1, (0x7<<18)|(0x7<<2)
+    not t1, t1
+    lw  t2, 0x54(t0)
+    and t2, t2, t1
+    sw  t2, 0x54(t0)
+
+    lw  t2, 0x58(t0)
+    and t2, t2, t1
+    sw  t2, 0x58(t0)
+
 	dli	t1, 0xff204f
         sw      t1, 0x0(t0)
   
@@ -498,6 +515,12 @@ cp0_main:
 	or	t1, 0x20000
 	sw	t1, 0x0(t0)
 
+	dli	t0, 0x900000fe0700701c
+    lw  t2, 0x0(t0)
+    li  t1, (0x1 << 26)
+    or  t2, t1
+    sw  t2, 0x0(t0)
+
 	dli	t0, 0x900000fe00007000
 	li	t1, 0x10100000
 	sw	t1, 0x10(t0)
@@ -506,6 +529,16 @@ cp0_main:
 	li      t1, 0x10100000
 	or	t0, t0, t1
 
+    li  t1, (0x7<<18)|(0x7<<2)
+    not t1, t1
+    lw  t2, 0x54(t0)
+    and t2, t2, t1
+    sw  t2, 0x54(t0)
+
+    lw  t2, 0x58(t0)
+    and t2, t2, t1
+    sw  t2, 0x58(t0)
+
 	dli	t1, 0xff204c
         sw      t1, 0x0(t0)
   
@@ -517,6 +550,12 @@ cp0_main:
 	or	t1, 0x20000
 	sw	t1, 0x0(t0)
 
+	dli	t0, 0x900000fe0700481c
+    lw  t2, 0x0(t0)
+    li  t1, (0x1 << 26)
+    or  t2, t1
+    sw  t2, 0x0(t0)
+
 	dli	t0, 0x900000fe00004800
 	li	t1, 0x11000000
 	sw	t1, 0x10(t0)
@@ -525,6 +564,16 @@ cp0_main:
 	li      t1, 0x11000000
 	or	t0, t0, t1
 
+    li  t1, (0x7<<18)|(0x7<<2)
+    not t1, t1
+    lw  t2, 0x54(t0)
+    and t2, t2, t1
+    sw  t2, 0x54(t0)
+
+    lw  t2, 0x58(t0)
+    and t2, t2, t1
+    sw  t2, 0x58(t0)
+
 	dli	t1, 0xff204c
         sw      t1, 0x0(t0)
   
@@ -536,6 +585,12 @@ cp0_main:
 	or	t1, 0x20000
 	sw	t1, 0x0(t0)
 
+	dli	t0, 0x900000fe0700501c
+    lw  t2, 0x0(t0)
+    li  t1, (0x1 << 26)
+    or  t2, t1
+    sw  t2, 0x0(t0)
+
 	dli	t0, 0x900000fe00005000
 	li	t1, 0x11100000
 	sw	t1, 0x10(t0)
@@ -544,6 +599,16 @@ cp0_main:
 	li      t1, 0x11100000
 	or	t0, t0, t1
 
+    li  t1, (0x7<<18)|(0x7<<2)
+    not t1, t1
+    lw  t2, 0x54(t0)
+    and t2, t2, t1
+    sw  t2, 0x54(t0)
+
+    lw  t2, 0x58(t0)
+    and t2, t2, t1
+    sw  t2, 0x58(t0)
+
 	dli	t1, 0xff204c
         sw      t1, 0x0(t0)