turn off cache eanable operation in CPU_ConfigCache.

git-svn-id: file:///svn/pmon-all/pmon-all@20 214b0138-1524-0410-9122-e5cb4b5bc56c

pmon/arch/mips/cache.S

@@ -447,7 +447,7 @@ ConfResult:
 	srl	t5, t2				# calculate set size.
 	sw	t5, CpuPrimaryDataSetSize
 
-#if 1
+#if 0
 	and	v0, 0xfffffff8
         or	v0, 0x00000003			# set coherency mode WB KSEG0
 

sys/arch/mips/include/newtest/mydebug.S

@@ -4,7 +4,7 @@ bootkeytest:
 	beqz v0,bootnow
 	nop
 mycmd_loop:
-	PRINTSTR("A:writeone-testone\r\nB:writesome+-testsome--\r\nC:writesome-testsome-rom\r\nD:writeall-testall\r\nE:writesome-testsome-ram\r\nF:writeall-testall-ram\r\nG:copytest\r\nz:read @addr\r\ns:write\r\nv:write then read @addr\r\ng:rwtest\r\nn:write 16M\r\nd:debug\r\nb:boot\r\n");
+	PRINTSTR("A:writeone-testone\r\nB:writesome+-testsome--\r\nC:writesome-testsome-rom\r\nD:writeall-testall\r\nE:writesome-testsome-ram\r\nF:writeall-testall-ram\r\nG:copytest\r\nH:writesomereverse-testsome-rom\r\nI:writesomereverse-testsome-ram\r\nz:read @addr\r\ns:write\r\nv:write then read @addr\r\ng:rwtest\r\nn:write 16M\r\nj:write 0 to a0000000\r\nd:debug\r\nb:boot\r\n");
 	bal tgt_getchar
 	nop
 	li v1,'A'
@@ -58,6 +58,9 @@ mycmd_loop:
 	li v1,'w'
 	beq v0,v1,dummywritetest
 	nop
+	li v1,'j'
+	beq v0,v1,dummywritetest1
+	nop
 	b bootnow
 	nop
 dummyreadtest:
@@ -74,6 +77,27 @@ dummywritetest:
 	addiu v0,8
 	b 1b
 	nop
+dummywritetest1:
+	li v0,0xa0000000
+1:
+	sd zero,(v0)
+	sd zero,(v0)
+	sd zero,(v0)
+	sd zero,(v0)
+	sd zero,(v0)
+	sd zero,(v0)
+	sd zero,(v0)
+	sd zero,(v0)
+	sd zero,(v0)
+	sd zero,(v0)
+	sd zero,(v0)
+	sd zero,(v0)
+	sd zero,(v0)
+	sd zero,(v0)
+	sd zero,(v0)
+	sd zero,(v0)
+	b 1b
+	nop
 memtest:
 #include "writeone-testone8.S"	
 memtest1: