From 847c1e80b58a9040f2088af4276c9cbc817802ce Mon Sep 17 00:00:00 2001 From: Wang Huandong Date: Fri, 14 Dec 2012 16:27:58 +0800 Subject: [PATCH] change the DDR3-UDIMM params for stability fix CPU hung when CP/IO-ZONE/OS SETUP/multi-DIMM test Targets: 3c780e --- Targets/Bonito3c780e/Bonito/loongson3C_ddr_param.S | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/Targets/Bonito3c780e/Bonito/loongson3C_ddr_param.S b/Targets/Bonito3c780e/Bonito/loongson3C_ddr_param.S index e68d7ed8..b5e0fc1a 100644 --- a/Targets/Bonito3c780e/Bonito/loongson3C_ddr_param.S +++ b/Targets/Bonito3c780e/Bonito/loongson3C_ddr_param.S @@ -224,7 +224,9 @@ MC0_DDR3_CTRL_0x008: .dword 0x0000000000000000 //XXXX pm_dll_value_4(RD) XXXX pm_dll_value_3 (RD) XXXX pm_dll_value_2(RD) XXXX pm_dll_value_1(RD) MC0_DDR3_CTRL_0x010: .dword 0x0000000000000000 //XXXX pm_dll_value_8(RD) XXXX pm_dll_value_7 (RD) XXXX pm_dll_value_6(RD) XXXX pm_dll_value_5(RD) -MC0_DDR3_CTRL_0x018: .dword 0x5252525216600000 +//MC0_DDR3_CTRL_0x018: .dword 0x5252525216600000 +//MC0_DDR3_CTRL_0x018: .dword 0x4040404016600000 +MC0_DDR3_CTRL_0x018: .dword 0x3030303016600000 //_00000000 pm_dll_ck_3 _00000000 pm_dll_ck_2 _00000000 pm_dll_ck_1 _00000000 pm_dll_ck_0 _00000000 pm_dll_increment _00000000 pm_dll_start_point _0000000_0 pm_dll_bypass _0000000_0 pm_init_start MC0_DDR3_CTRL_0x020: .dword 0x0202000001000000 //0000_0000 pm_dq_oe_end_0 0000_0000 pm_dq_oe_begin_0 000000_00 pm_dq_stop_edge_0 000000_00 pm_dq_start_edge_0 0000000_0 pm_rddata_delay_0 0000000_0 pm_rddqs_lt_half_0 0000000_0 pm_wrdqs_lt_half_0 0000000_0 pm_wrdq_lt_half_0 @@ -338,9 +340,9 @@ MC0_DDR3_CTRL_0x1c0: .dword 0x3030c80c03032008 //_00000000 pm_tRESET _00000000 pm_tCKE _00000000 pm_tXPR _00000000 pm_tMOD _00000000 pm_tZQCL _00000000 pm_tZQ_CMD _00000000 pm_tWLDQSEN 000_00000 pm_tRDDATA MC0_DDR3_CTRL_0x1c8: .dword 0x1f06090903a04004 //00_000000 pm_tFAW 0000_0000 pm_tRRD 0000_0000 pm_tRCD _00000000 pm_tRP _00000000 pm_tREF _00000000 pm_tRFC _00000000 pm_tZQCS _00000000 pm_tZQperiod -MC0_DDR3_CTRL_0x1d0: .dword 0x0a0208040200001c +MC0_DDR3_CTRL_0x1d0: .dword 0x0a0209040200001c //0000_0000 pm_tODTL _00000000 pm_tXSRD 0000_0000 pm_tPHY_RDLAT 000_00000 pm_tPHY_WRLAT 000000_00_00000000_00000000 pm_tRAS_max 00_000000 pm_tRAS_min -MC0_DDR3_CTRL_0x1d8: .dword 0x14050c060a080406 +MC0_DDR3_CTRL_0x1d8: .dword 0x14050c060a080506 //_00000000 pm_tXPDLL _00000000 pm_tXP 000_00000 pm_tWR 0000_0000 pm_tRTP 0000_0000 pm_tRL 0000_0000 pm_tWL 0000_0000 pm_tCCD 0000_0000 pm_tWTR MC0_DDR3_CTRL_0x1e0: .dword 0x0503000000000000 //00_000000 pm_tW2R_diffcs_dly 00_000000 pm_tW2W_diffcs_adj_dly 00_000000 pm_tR2P_sameba_adj_dly 00_000000 pm_tW2P_sameba_adj_dly 00_000000 pm_tR2R_sameba_adj_dly 00_000000 pm_tR2W_sameba_adj_dly 00_000000 pm_tW2R_sameba_adj_dly 00_000000 pm_tW2W_sameba_adj_dly