2k trfc and tref update

Change-Id: I5abaa0b0551b77ac696942665b3edae43f3a9c62

Targets/LS2K/ls2k/ddr_dir/ddr_config_define.h

@@ -67,7 +67,7 @@ DIMM infor:
 |[15:15]| SDRAM_WIDTH        | 1'b1    | x16               |
 |       |                    | 1'b0    | x8                |
 ------------------------------------------------------------
-|[63:47]| MC1--like s1[31:16] for MC0
+|[63:48]| MC1--like s1[31:16] for MC0
 temparary used in PROBE_DIMM
 |[38:32]| DIMM_MEMSIZE       | 7'b0000 | 0M                |
 |       |                    | 7'b0001 | 512M              |
@@ -292,6 +292,7 @@ temparary used in PROBE_DIMM
 #define ADDR_MIRROR_OFFSET  22
 #define COL_SIZE_OFFSET     20
 #define MC_CS_MAP_OFFSET    16
+#define MC1_CS_MAP_OFFSET   48
 #define SDRAM_WIDTH_OFFSET  15
 #define MC_CS_MAP_MASK      (0xf)
 #define MC1_MEMSIZE_OFFSET  40
@@ -350,6 +351,11 @@ dli     a1, MC_CS_MAP_MASK;\
 dsll    a1, a1, MC_CS_MAP_OFFSET;\
 and     a1, s1, a1;\
 dsrl    a1, a1, MC_CS_MAP_OFFSET;
+#define GET_MC1_CS_MAP      \
+dli     a1, MC_CS_MAP_MASK;\
+dsll    a1, a1, MC1_CS_MAP_OFFSET;\
+and     a1, s1, a1;\
+dsrl    a1, a1, MC1_CS_MAP_OFFSET;
 #define GET_DIMM_MEMSIZE      \
 dli     a1, DIMM_MEMSIZE_MASK;\
 dsll    a1, a1, DIMM_MEMSIZE_OFFSET;\

Targets/LS2K/ls2k/ddr_dir/lsmc_config_param.S

@@ -289,6 +289,86 @@ set_tRTP:
 	sb		t4, 0x18(t1)
 */
 #endif
+set_tREFI:
+	dli		t1, DDR_FREQ
+	divu	t1, t1, 10
+	dli		a2, 78
+	dmulou	a2, a2, t1
+#ifndef TEMP_EXTREME
+	dsrl	a2, a2, 8
+#else
+	dsrl	a2, a2, 9
+#endif
+//	daddu	a2, a2, 1
+	dli		t1, 0x1c8
+	or		t1, t1, t8
+	sb		a2, 0x3(t1)
+
+set_tRFC:
+    GET_MC0_MEMSIZE
+    beqz    t3, 1f
+    nop
+    GET_MC1_MEMSIZE
+1:
+    move	t1, a1
+	GET_MC_CS_MAP
+    beqz    t3, 1f
+    nop
+	GET_MC1_CS_MAP
+1:
+	dli 	t5, 0x4
+	dli		a2, 0x0
+cal_memsize:
+	dsubu	t5, t5, 1
+	beqz	t5, 1f
+	nop
+	and		t4, a1, 0x1
+	dsrl	a1, a1, 0x1	
+	beqz	t4, cal_memsize
+	nop
+	daddu	a2, a2, 1
+	b		cal_memsize
+	nop
+
+1:
+	divu	a2, t1, a2
+	dli     t5, 0x2
+	divu	a2, a2, t5
+
+	dli		t1, 0x1
+	blt		a2, t1, 21f
+	dli		t5, 0x9
+
+	dli		t1, 0x2
+	blt		a2, t1, 21f
+	dli		t5, 0xb
+
+	dli		t1, 0x4
+	blt		a2, t1, 21f
+	dli		t5, 0x10
+
+	dli		t1, 0x8
+	blt		a2, t1, 21f
+	dli		t5, 0x1a
+
+	dli		t1, 0x10
+	blt		a2, t1, 21f
+	dli		t5, 0x23
+
+	PRINTSTR("\r\n memsize wrong \r\n")
+	b 		2f
+	nop
+21:
+
+	dli		t1, DDR_FREQ
+	dmulou	t5, t5, t1
+	divu	t5, t5, 100
+	
+	dli		t1, 0x1c8
+	or		t1, t1, t8
+	sb		t5, 0x2(t1)
+ 
+2:
 
     //for UDIMM 4cs,open 2T mode
     GET_DIMM_TYPE

Targets/LS2K/ls2k/loongson3_clksetting.S

@@ -13,6 +13,7 @@ ATTENTION:
 #define SOFT_CLKSEL
 
 
+#define DDR_FREQ   500   //this param must change with DDR freq together,ether soft or hard freq modified!!!
 #ifdef SOFT_CLKSEL
 #if 1
 /* MEM @ 500Mhz */

Targets/LS2K/ls2k/loongson_mc2_param.S

@@ -95,7 +95,7 @@ MC0_DDR3_CTRL_0x130: .dword 0x0000000003020202
 //hXXXXXX (RD) 0000000_0 pm_wrdq_clkdelay_8 0000_0000 pm_odt_oe_end_8 0000_0000 pm_odt_oe_begin_8 000000_00 pm_odt_stop_edge_8 000000_00 pm_odt_start_edge_8
 MC0_DDR3_CTRL_0x138: .dword 0x00000020207f6000
 //hXXXXXX (RD) _00000000 pm_dll_rddqs_n_8 _00000000 pm_dll_rddqs_p_8 _00000000 pm_dll_wrdqs_8 _00000000 pm_dll_wrdata_8 _00000000 pm_dll_gate_8
-MC0_DDR3_CTRL_0x140: .dword 0x0403000001ff01ff
+MC0_DDR3_CTRL_0x140: .dword 0x0003000001ff01ff
 //00000_000 pm_pad_ocd_clk 00000_000 pm_pad_ocd_ctl 0000000_0 pm_pad_ocd_dqs 0000000_0 pm_pad_ocd_dq 0000000_0_00000000 pm_pad_enzi 0000000_0 pm_pad_en_ctl _00000000 pm_pad_en_clk
 MC0_DDR3_CTRL_0x148: .dword 0x0000000000010100
 //_0000 pm_pad_adj_ncode_dq _0000 pm_pad_adj_pcode_dq 00000 _0 pm_pad_outodt_dq _0 pm_pad_slewrate_dq _0 pm_pad_code_dq _0000 pm_pad_adj_ncode_dq _0000 pm_pad_adj_pcode_dq 00000 _0 pm_pad_outodt_dq _0 pm_pad_slewrate_dq _0 00000000 0000000_0 pm_pad_vref_internal 0000000_0 pm_pad_odt_se 0000000_0 pm_pad_modezi1v8
@@ -328,7 +328,7 @@ MC0_DDR3_RDIMM_CTRL_0x130: .dword 0x0000000003020202
 //hXXXXXX (RD) 0000000_0 pm_wrdq_clkdelay_8 0000_0000 pm_odt_oe_end_8 0000_0000 pm_odt_oe_begin_8 000000_00 pm_odt_stop_edge_8 000000_00 pm_odt_start_edge_8
 MC0_DDR3_RDIMM_CTRL_0x138: .dword 0x00000020207f6000
 //hXXXXXX (RD) _00000000 pm_dll_rddqs_n_8 _00000000 pm_dll_rddqs_p_8 _00000000 pm_dll_wrdqs_8 _00000000 pm_dll_wrdata_8 _00000000 pm_dll_gate_8
-MC0_DDR3_RDIMM_CTRL_0x140: .dword 0x0403000001ff01ff
+MC0_DDR3_RDIMM_CTRL_0x140: .dword 0x0003000001ff01ff
 //00000_000 pm_pad_ocd_clk 00000_000 pm_pad_ocd_ctl 0000000_0 pm_pad_ocd_dqs 0000000_0 pm_pad_ocd_dq 0000000_0_00000000 pm_pad_enzi 0000000_0 pm_pad_en_ctl _00000000 pm_pad_en_clk
 MC0_DDR3_RDIMM_CTRL_0x148: .dword 0x0000000000010100
 //_0000 pm_pad_adj_ncode_dq _0000 pm_pad_adj_pcode_dq 00000 _0 pm_pad_outodt_dq _0 pm_pad_slewrate_dq _0 pm_pad_code_dq _0000 pm_pad_adj_ncode_dq _0000 pm_pad_adj_pcode_dq 00000 _0 pm_pad_outodt_dq _0 pm_pad_slewrate_dq _0 00000000 0000000_0 pm_pad_vref_internal 0000000_0 pm_pad_odt_se 0000000_0 pm_pad_modezi1v8