modify 3aserver codes to support gcc4.4

Change-Id: Ie75ebc59d21a36b5948e68eb739f8b2e78bbe033
Target: 3aserver

Targets/Bonito3aserver/Bonito/loongson3_fixup.S

@@ -27,7 +27,7 @@
     nop
     nop
     nop
-
+	.set mips3
 #if 0
 #set XBAR to route all the DMA request to Scache0
 /* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
@@ -61,13 +61,13 @@
 
 #ifdef MULTI_CHIP
 /* Fix HT connection bug between two LS3A chipses */ 
-  li  t0, 0x90000cfdfb00003c;
+  dli  t0, 0x90000cfdfb00003c;
   lw  a0, 0x00(t0);
   li  a1, 0x30000; 
   or  a0, a1;
   sw  a0, 0x00(t0);
 
-  li  t0, 0x90001cfdfb00003c;
+  dli  t0, 0x90001cfdfb00003c;
   lw  a0, 0x00(t0);
   li  a1, 0x30000; 
   or  a0, a1;

Targets/Bonito3aserver/Bonito/start.S

@@ -259,6 +259,7 @@ locate:
 	or	t1, t2, t1
 
 	bal	scache_init_64_fast
+	nop
 	dli	t2, NODE0_CORE0_BUF0
 
 	or	t1, t2, t1

Targets/Bonito3aserver/Bonito/tgt_machdep.c

@@ -1284,57 +1284,7 @@ tgt_devinit()
 }
 
 
-#ifdef DEVBD2F_CS5536
-	void
-tgt_reboot()
-{
-	unsigned long hi, lo;
-
-	/* reset the cs5536 whole chip */
-	_rdmsr(0xe0000014, &hi, &lo);
-	lo |= 0x00000001;
-	_wrmsr(0xe0000014, hi, lo);
-
-	while(1);
-}
-
-	void
-tgt_poweroff()
-{
-	unsigned long val;
-	unsigned long tag;
-	unsigned long base;
-
-	tag = _pci_make_tag(0, 14, 0);
-	base = _pci_conf_read(tag, 0x14);
-	//base |= 0xbfd00000;
-	base |= BONITO_PCIIO_BASE_VA;
-	base &= ~3;
-
-	/* make cs5536 gpio13 output enable */
-	val = *(volatile unsigned long *)(base + 0x04);
-	val = ( val & ~(1 << (16 + 13)) ) | (1 << 13) ;
-	*(volatile unsigned long *)(base + 0x04) = val;
-
-	/* make cs5536 gpio13 output low level voltage. */
-	val = *(volatile unsigned long *)(base + 0x00);
-	val = (val | (1 << (16 + 13))) & ~(1 << 13);
-	*(volatile unsigned long *)(base + 0x00) = val;
-
-	while(1);
-}
-#else
-static void delay(int j)
-{
-	volatile int i, k;
-
-	for(k = 0; k < j; k++)
-		for(i = 0; i < 1000; i++);
-
-}
-
-	void
-tgt_poweroff()
+void tgt_poweroff()
 {
 	char * watch_dog_base = 0xb8000cd6;
 	char * watch_dog_config  = 0xba00a041;
@@ -1383,7 +1333,6 @@ void tgt_reboot(void)
 {
 	watchdog_enable();
 }
-#endif
 
 
 /*

Targets/Bonito3aserver/pci/amd_780e.c

@@ -20,6 +20,15 @@
 #define OUTW(b,addr) (*(volatile unsigned short *) (addr) = (b))
 #define OUTL(b,addr) (*(volatile unsigned int *) (addr) = (b))
 
+/* Get SB ASIC Revision.*/
+static u8 get_sb700_revision()
+{
+	device_t dev;
+	//dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
+	dev = _pci_make_tag(0, 20, 0);
+	return pci_read_config8(dev, 0x08);
+}
+
 void rs780_por_pcicfg_init(device_t nb_tag)
 {
 	printk_info("enter rs780_por_pcicfg_init\n");
@@ -557,16 +566,6 @@ void rs780_before_pci_fixup(void){
 
 }
 
-/* Get SB ASIC Revision.*/
-static u8 get_sb700_revision()
-{
-	device_t dev;
-	//dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
-	dev = _pci_make_tag(0, 20, 0);
-	return pci_read_config8(dev, 0x08);
-}
-
-
 /*
 * Compliant with CIM_48's sbPciCfg.
 * Add any south bridge setting.
@@ -620,7 +619,7 @@ static void sb700_pci_cfg()
 	byte = pci_read_config8(dev, 0x78);
 	byte &= 0xfd;
 	pci_write_config8(dev, 0x78, byte);
-#ifdef 1
+#if 0
 	printk_info("enable hpet clock source\n");
 	/* HPET clocksource, BDF: 0-14-0 */
 	dev = _pci_make_tag(0, 14, 0);

Targets/Bonito3aserver/pci/sb700_sata.c

@@ -1,19 +1,9 @@
 #include "sb700.h"
 #include "rs780_cmn.h"
 
-#if 0
-#define writeb(val, addr) (*(volatile u8*)(addr) = (val))
-#define writew(val, addr) (*(volatile u16*)(addr) = (val))
-#define writel(val, addr) (*(volatile u32*)(addr) = (val))
-#define readb(addr) (*(volatile u8*)(addr))
-#define readw(addr) (*(volatile u16*)(addr))
-#define readl(addr) (*(volatile u32*)(addr))
-#endif
-
 extern struct southbridge_ati_sb700_config conf_info;
 
-
-#ifndef 1
+#if 0
 static sata_drive_detect(int portnum, u32 iobar)
 {
 	u8 byte, byte2;
@@ -260,7 +250,7 @@ static void sata_init(device_t dev)
 	}
 #endif
 
-#ifdef 1
+#if 0
 	/* Below is CIM InitSataLateFar */
 	/* Enable interrupts from the HBA  */
 	printk_info("Enable interrupts from the HBA\n");