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@ -83,10 +83,22 @@ u64 __raw_writeq_sp(u64 addr, u64 val) |
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extern char _start; |
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extern char ddr2_leveled_mark; |
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#ifndef LS3B |
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extern char ddr2_reg_data_mc0_leveled, ddr2_reg_data_mc1_leveled; |
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#ifdef MULTI_CHIP |
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extern char n1_ddr2_reg_data_mc0_leveled, n1_ddr2_reg_data_mc1_leveled; |
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#endif |
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#else |
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extern char ddr2_reg_data_leveled; |
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#ifdef MULTI_CHIP |
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extern char n1_ddr2_reg_data_leveled; |
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#endif |
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#ifdef DUAL_3B |
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extern char n2_ddr2_reg_data_leveled; |
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extern char n3_ddr2_reg_data_leveled; |
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#endif |
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#endif |
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//#define DEBUG
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#ifdef DEBUG |
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@ -94,7 +106,7 @@ extern int do_cmd(char *); |
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extern void dump_l2xbar(int node); |
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#endif |
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#ifdef loongson3A3 |
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#ifdef LSMCD3_2 |
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#define DDR_PARAM_NUM 180 |
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#else |
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#define DDR_PARAM_NUM 152 |
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@ -190,6 +202,7 @@ int read_ddr_param(u64 node_id_shift44, int mc_selector, unsigned long long * b |
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//do_cmd("showwindows");
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//dump_l2xbar(1);
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#ifndef LS3B |
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// step 1. Change The Primest window for MC0 or MC1 register space
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enable_ddrcfgwindow(node_id_shift44, mc_selector, buf); |
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@ -198,7 +211,7 @@ int read_ddr_param(u64 node_id_shift44, int mc_selector, unsigned long long * b |
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// step 2. Enabel access to MC0 or MC1 register space
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enable_ddrconfig(node_id_shift44); |
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#endif |
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// step 3. Read out ddr config register to buffer
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printf("\nNow Read out DDR parameter from DDR MC%d controler after DDR training\n", mc_selector); |
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for ( i = DDR_PARAM_NUM - 1; i >= 0; i--) // NOTICE HERE: it means system has DDR_PARAM_NUM double words
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@ -206,22 +219,26 @@ int read_ddr_param(u64 node_id_shift44, int mc_selector, unsigned long long * b |
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val[i] = ld((MC_CONFIG_ADDR | node_id_shift44) + (0x10 * i)); |
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#ifdef DEBUG |
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printf("< CFGREG >:val[%d] = %016llx \n", i, val[i]); |
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printf("< CFGREG >:val[%03d] = %016llx \n", i, val[i]); |
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#endif |
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} |
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//clear param_start
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val[3] &= 0xfffffeffffffffff; |
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#ifndef LS3B |
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// step 4. Disabel access to MC0 or MC1 register space
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disable_ddrconfig(node_id_shift44); |
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// step 5. Restore The Primest window for accessing system memory
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disable_ddrcfgwidow(node_id_shift44, mc_selector, buf); |
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#endif |
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printf("Read out DDR MC%d config Done.\n", mc_selector); |
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return 0; |
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} |
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#ifndef LS3B |
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void save_ddrparam(u64 node_id_shift44, int mc0_param_store_addr, int mc1_param_store_addr) |
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{ |
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@ -234,7 +251,7 @@ void save_ddrparam(u64 node_id_shift44, int mc0_param_store_addr, int mc1_param_ |
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#endif |
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#ifdef DEBUG |
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printf("node_id_shift44=0x%016llx\n", node_id_shift44); |
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printf("\nnode_id_shift44=0x%016llx\n", node_id_shift44); |
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#endif |
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/********************************************************/ |
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/************************/ // End of flash
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@ -313,7 +330,6 @@ void save_ddrparam(u64 node_id_shift44, int mc0_param_store_addr, int mc1_param_ |
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} |
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// test : master
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int save_board_ddrparam() |
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{ |
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unsigned long long flag; |
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@ -331,6 +347,83 @@ int save_board_ddrparam() |
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} |
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return(1); |
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} |
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#else |
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void save_ddrparam(u64 node_id_shift44, int mc0_param_store_addr) |
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{ |
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unsigned long long ddr_param_buf[DDR_PARAM_NUM + 1]; |
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#ifdef DEBUG |
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int i; |
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unsigned long long tmp; |
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#endif |
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#ifdef DEBUG |
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printf("\nnode_id_shift44=0x%016llx\n", node_id_shift44); |
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#endif |
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/********************************************************/ |
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/************************/ // End of flash
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/* DDRPTOVF */ // End - 8 (byte) (1M-8)
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/* -------------------- */ //
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/* */ //
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/* ....... */ |
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/* ....... */ |
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/* ....... */ // $ddr3_data
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/* ....... */ |
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/* */ |
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/************************/ // Base of flash: offset 0x00
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/********************************************************/ |
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// step 1. Read out DDR controler register values and save them in buffers
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// step 1.1 Read out DDR controler register from MC0 and save them in buffer0
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read_ddr_param(node_id_shift44, MC0, ddr_param_buf); |
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//ddr_param_buf[DDR_PARAM_NUM] = 0x0;
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// step 1.2 Program buffers of MC0 register into FLASH
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tgt_flashprogram((int *)(0xbfc00000+(mc0_param_store_addr -(int)&_start)), DDR_PARAM_NUM*8, ddr_param_buf,TRUE); |
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#ifdef DEBUG |
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for(i = 0; i< DDR_PARAM_NUM; i++) |
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{ |
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tmp = ld(0x900000001fc00000 + mc0_param_store_addr - (int)&_start + i * 8); |
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if(ddr_param_buf[i] != tmp) |
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{ |
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printf("\nMiscompare:i=%d, val=%016llx", i, tmp); |
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} |
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else |
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printf("\nSame:i=%d, val=%016llx", i, tmp); |
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} |
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#endif |
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} |
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int save_board_ddrparam() |
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{ |
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unsigned long long flag; |
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unsigned long long node_id; |
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if(ld(0x900000001fc00000 + (int) &ddr2_leveled_mark - (int)&_start) == 0) |
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{ |
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node_id = 0; |
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save_ddrparam(node_id << 44, (int)&ddr2_reg_data_leveled); |
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#ifdef MULTI_CHIP |
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node_id = 1; |
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save_ddrparam(node_id << 44, (int)&n1_ddr2_reg_data_leveled); |
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#endif |
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#ifdef DUAL_3B |
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node_id = 2; |
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save_ddrparam(node_id << 44, (int)&n2_ddr2_reg_data_leveled); |
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node_id = 3; |
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save_ddrparam(node_id << 44, (int)&n3_ddr2_reg_data_leveled); |
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#endif |
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flag = 0x1; |
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tgt_flashprogram((int *)(0xbfc00000 + ((int)&ddr2_leveled_mark - (int)&_start)), 8, &flag, TRUE); |
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} |
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return(1); |
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} |
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#endif |
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int cmd_save_ddrparam(ac, av) |
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int ac; |
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Chen Xinke
13 years ago
wanghongmei