reverse rddqs_lt_half set method to fix ddr stuck problem.

Changed the ddr i2c address for the node get ture infomation.

Change-Id: Ibe3912682d6b1b5cc03787434a40e4e5c7da6893

Targets/Bonito3a84w/Bonito/start.S

@@ -759,7 +759,7 @@ MEM_INIT_DONE:
     	TTYDBG("NODE 2 MEMORY CONFIG BEGIN\r\n")
 
 #ifdef  AUTO_DDR_CONFIG
-    	dli     s1, 0xf5f40002  //set use MC1 or MC0 or MC1/0 and give All device id
+	dli     s1, 0xf7f60002  //set use MC1 or MC0 or MC1/0 and give All device id
 #else
 	//dli     s1, 0xc2e30400c2e30405
     	//dli     s1, 0xc1a10400c1a10406  // use MC0, 2G SCS UDIMM
@@ -858,7 +858,7 @@ MEM_INIT_DONE:
     	TTYDBG("NODE 3 MEMORY CONFIG BEGIN\r\n")
 
 #ifdef  AUTO_DDR_CONFIG
-    	dli     s1, 0xf7f60003  //set use MC1 or MC0 or MC1/0 and give All device id
+	dli     s1, 0xf5f40003  //set use MC1 or MC0 or MC1/0 and give All device id
 #else
 	//dli     s1, 0xc2e30400c2e30405
     	//dli     s1, 0xc1a10400c1a10407  // use MC0, 2G SCS UDIMM

pmon/arch/mips/mm/loongson3C_ddr3_leveling.S

@@ -2527,11 +2527,11 @@ rddqs_lt_half:
     dsrl    a1, a1, 8  //get dll_wrdata
     daddu   a0, a0, a1
     and     a0, a0, t6
-    bgeu    a0, a3, rddqs_lt_half_set1//because the rd gate edge is 0x2
+    bgeu    a0, a3, rddqs_lt_half_set0//because the rd gate edge is 0x2
     nop
-    bltu    a0, a2, rddqs_lt_half_set1
+    bltu    a0, a2, rddqs_lt_half_set0
     nop
-    b       rddqs_lt_half_set0
+    b       rddqs_lt_half_set1
     nop
 rddqs_lt_half_set0:
     dsubu   t2, t1, 0x18