diff --git a/Targets/Bonito3a780e/Bonito/loongson3a_ddr3_param.S b/Targets/Bonito3a780e/Bonito/loongson3a_ddr3_param.S index 3431dc22..97a80d55 100644 --- a/Targets/Bonito3a780e/Bonito/loongson3a_ddr3_param.S +++ b/Targets/Bonito3a780e/Bonito/loongson3a_ddr3_param.S @@ -1,37 +1,38 @@ /*DDR3 PARAMETER */ +//#define REGDIMM_5 ddr3_reg_data: -MC0_DDR3_CTL_000 : .dword 0x0000000000010101 +MC0_DDR3_CTL_000 : .dword 0x0000000000000101 //000000000000000_0 concurrentap(RW) 0000000_1 bank_split_en(RW) 0000000_0 auto_refresh_mode(RW) 0000000_0 arefresh(WR) 0000000_0 ap(RW) 0000000_1 addr_cmp_en(RW) 0000000_1 active_aging(RW) MC0_DDR3_CTL_010 : .dword 0x0001000100010000 //0000000_0 fwc(WR) 0000000_0 fast_write(RW) 0000000_1 enable_quick_srefresh(RW) 0000000_1 eight_bank_mode(RW) 0000000_0 ecc_disable_w_uc_err(RW) 0000000_1 dqs_n_en(RW) 0000000_0 dll_bypass_mode(RW) 0000000_0 dlllockreg(RD) MC0_DDR3_CTL_020 : .dword 0x0100010101000000 //0000000_1 priority_en(RW) 0000000_0 power_down(RW) 0000000_1 placement_en(RW) 0000000_1 odt_add_turn_clk_en(RW) 0000000_0 no_cmd_init(RW) 0000000_0 intrptwritea(RW) 0000000_0 intrptreada(RW) 0000000_0 intrptapburst(RW) -MC0_DDR3_CTL_030 : .dword 0x0101000001000000 +MC0_DDR3_CTL_030 : .dword 0x0000000000000000 //0000000_1 swap_port_rw_same_en(RW) 0000000_1 swap_en(RW) 0000000_0 start(RW) 0000000_0 srefresh(RW+) 0000000_1 rw_same_en(RW) 0000000_0 reg_dimm_enable(RW) 0000000_0 reduc(RW) 0000000_0 pwrup_srefresh_exit(RW) -MC0_DDR3_CTL_040 : .dword 0x0100010200010101 +MC0_DDR3_CTL_040 : .dword 0x0100010200000101 //000000_01 rtt_0(RW) 000000_11 ctrl_raw(RW) 000000_01 axi0_w_priority(RW) 000000_01 axi0_r_priority(RW) 0000000_0 write_modereg(WR) 0000000_1 writeinterp(RW) 0000000_1 tref_enable(RW) 0000000_1 tras_lockout(RW) MC0_DDR3_CTL_050 : .dword 0x0000000404050100 //00000_000 q_fullness(RW) 00000_000 port_data_error_type(RD) 000_00000 out_of_range_type(RD) 00000_000 max_cs_reg(RD) 00000_100 column_size(RW) 0000_0101 caslat(RW) 00000_010 addr_pins(RW) 00000000 -MC0_DDR3_CTL_060 : .dword 0x0a05040603040003 +MC0_DDR3_CTL_060 : .dword 0x0a050e0e0e0e0003 //0000_1010 aprebit(RW) 0000_0101 wrlat(RW) 0000_0100 twtr(RW) 000_00110 twr_int(RW) 00000_011 trtp(RW) 00000_100 trrd(RW) 0000000000000_011 tcke(RW) -MC0_DDR3_CTL_070 : .dword 0x0f0e000000010808 #modified by jian 20100212 from:0x0f0e020000010a08b# +MC0_DDR3_CTL_070 : .dword 0x0f0e000000010a0a #modified by jian 20100212 from:0x0f0e020000010a08b# //0000_0000 max_row_reg(RD) 0000_0000 max_col_reg(RD) 0000_0000 initaref(RW) 00000000000000000000_1111 cs_map(RW) 000_01010 caslat_lin_gate(RW) 000_01010 caslat_lin(RW) //MC0_DDR3_CTL_080 : .dword 0x0102040801020408 #modified by jian 20100212 to: #0x0004020100000000 MC0_DDR3_CTL_080 : .dword 0x0804020100000000 //0000_0001 odt_wr_map_cs3(RW) 0000_0010 odt_wr_map_cs2(RW) 0000_0100 odt_wr_map_cs1(RW) 0000_1000 odt_wr_map_cs0(RW) 0000_0001 odt_rd_map_cs3(RW) 0000_0010 odt_rd_map_cs2(RW) 0000_0100 odt_rd_map_cs1(RW) 0000_1000 odt_rd_map_cs0(RW) -MC0_DDR3_CTL_090 : .dword 0x0000050b00000000 +MC0_DDR3_CTL_090 : .dword 0x0000061f00000000 //000_00000 ocd_adjust_pup_cs_0(RW) 000_00000 ocd_adjust_pdn_cs_0(RW) 0000_0101 trp(RW) 000_01011 tdal(RW) 000000000000_0000 port_cmd_error_type(RD) 0000000000000000 -MC0_DDR3_CTL_0a0 : .dword 0x0000003f3f140612 +MC0_DDR3_CTL_0a0 : .dword 0x0000003f3f1f061a //MC0_DDR3_CTL_0a0 : .dword 0x0000003f3f14021b //00000000000000000000000000_111111 command_age_count(RW) 00_111111 age_count(RW) 000_10100 trc(RW) 000_00110 tmrd(RW) 000_10010 tfaw(RW) MC0_DDR3_CTL_0b0 : .dword 0x0000000000000000 -MC0_DDR3_CTL_0c0 : .dword 0x00002c050f000000 +MC0_DDR3_CTL_0c0 : .dword 0x00004f0f1f000000 //000000000000000000101100 trfc(RW) 00000101 trcd_int(RW) 00001111 tras_min(RW) 00000000 out_of_range_length(RD) 00000000 ecc_u_synd(RD) 00000000 ecc_c_synd(RD) MC0_DDR3_CTL_0d0 : .dword 0x0000000000000000 MC0_DDR3_CTL_0e0 : .dword 0x0000000000000000 MC0_DDR3_CTL_0f0 : .dword 0x0000000000000000 MC0_DDR3_CTL_100 : .dword 0x0000000000000000 -MC0_DDR3_CTL_110 : .dword 0x000000000000012d +MC0_DDR3_CTL_110 : .dword 0x000000000000052d //0_000000000000000 emrs2_data_1(RW) 0_000000000000000 emrs2_data_0(RW) 000000000000000000_00110000101101 tref(RW) MC0_DDR3_CTL_120 : .dword 0xffff000000000000 //0000000000011100 axi0_en_size_lt_width_instr(RW) 00000000000000000_000000000000000 emrs2_data_3(RW) 0_000000000000000 emrs2_data_2(RW) @@ -58,34 +59,34 @@ MC0_DDR3_CTL_1d0 : .dword 0x0203070400000101 //0000_0010 tdfi_phy_wrlat_base(RW) 0000_0000 tdfi_phy_wrlat(RD) 000_00111 tdfi_phy_rdlat(RW) 0000_0000 tdfi_ctrlupd_min(RD) 000000000000_0000 dram_clk_disable(RW) 0000000_1 odt_alt_en(RW) 0000000_1 drive_dq_dqs(RW) MC0_DDR3_CTL_1e0 : .dword 0x0c2d0c2d0c2d0205 //00_00000000000000 tdfi_phyupd_type0(RD) 00_00000000000000 tdfi_phyupd_resp(RD) 00_00000000000000 tdfi_ctrlupd_max(RD) 000_00000 tdfi_rddata_en_base(RW) 000_00000 tdfi_rddata_en(RD) -MC0_DDR3_CTL_1f0 : .dword 0x0012108000000000 -MC0_DDR3_CTL_200 : .dword 0x0012108000121080 -MC0_DDR3_CTL_210 : .dword 0x0012108000121080 +MC0_DDR3_CTL_1f0 : .dword 0x0016008000000000 +MC0_DDR3_CTL_200 : .dword 0x0012008000141080 +MC0_DDR3_CTL_210 : .dword 0x0012008000121080 //00000000001000000000111510000000 dll_ctrl_reg_0_4(RW) 00000000001000000000111010000000 dll_ctrl_reg_0_3(RW) -MC0_DDR3_CTL_220 : .dword 0x00101080000f1080 +MC0_DDR3_CTL_220 : .dword 0x0014108000141080 //00000000001000000000111510000000 dll_ctrl_reg_0_6(RW) 00000000001000000000111010000000 dll_ctrl_reg_0_5(RW) -MC0_DDR3_CTL_230 : .dword 0x000f108000101080 -MC0_DDR3_CTL_240 : .dword 0x0000150000001500 +MC0_DDR3_CTL_230 : .dword 0x000f108000121080 +MC0_DDR3_CTL_240 : .dword 0x0000150000001000 //00000000000000000000111000000000 dll_ctrl_reg_1_1(RW) 00000000000000000000111000000000 dll_ctrl_reg_1_0(RW) MC0_DDR3_CTL_250 : .dword 0x0000150000001200 -MC0_DDR3_CTL_260 : .dword 0x0000120000001200 -MC0_DDR3_CTL_270 : .dword 0x0000120000001200 +MC0_DDR3_CTL_260 : .dword 0x0000150000001800 +MC0_DDR3_CTL_270 : .dword 0x0000140000001200 MC0_DDR3_CTL_280 : .dword 0x0000000000001200 MC0_DDR3_CTL_290 : .dword 0x0000000000000000 MC0_DDR3_CTL_2a0 : .dword 0x0000000000000000 MC0_DDR3_CTL_2b0 : .dword 0x0000000000000000 MC0_DDR3_CTL_2c0 : .dword 0x0000000000000000 -MC0_DDR3_CTL_2d0 : .dword 0xf3002837003c09b5 +MC0_DDR3_CTL_2d0 : .dword 0x03001827003c09b5 //11110100000000000011101100100111 phy_ctrl_reg_0_0(RD) 000000_00000000000000000110011101 pad_ctrl_reg_0(RW) MC0_DDR3_CTL_2e0 : .dword 0xf3002837f3002837 MC0_DDR3_CTL_2f0 : .dword 0xf3002837f3002837 MC0_DDR3_CTL_300 : .dword 0xf3002837f3002837 -MC0_DDR3_CTL_310 : .dword 0xf3002837f3002837 +MC0_DDR3_CTL_310 : .dword 0xf3002837f3002847 MC0_DDR3_CTL_320 : .dword 0x26c0000126c00001 MC0_DDR3_CTL_330 : .dword 0x26c0000126c00001 MC0_DDR3_CTL_340 : .dword 0x26c0000126c00001 MC0_DDR3_CTL_350 : .dword 0x26c0000126c00001 -MC0_DDR3_CTL_360 : .dword 0x0800c10526c00001 +MC0_DDR3_CTL_360 : .dword 0x0800e10526c00001 //00000000000000001100000000000101 phy_ctrl_reg_2(RW) 00000111110000000000001100000001 phy_ctrl_reg_1_8(RD) MC0_DDR3_CTL_370 : .dword 0x0000000000000000 MC0_DDR3_CTL_380 : .dword 0x0000000000000000 @@ -152,13 +153,13 @@ MC0_DDR3_CTL_740 : .dword 0x0100000000000000 //MC0_DDR3_CTL_750 : .dword 0x0100000101020101 MC0_DDR3_CTL_750 : .dword 0x0100000101020101 //000000_01 wrlvl_cs(RW) 000000_00 sw_leveling_mode(RW) 000000_00 rdlvl_cs(RW) 000000_01 axi2_w_priority(RW) 000000_01 axi2_r_priority(RW) 000000_10 axi2_port_ordering(RW) 000000_01 axi1_w_priority(RW) 000000_01 axi1_r_priority(RW) -MC0_DDR3_CTL_760 : .dword 0x0303030000030001 +MC0_DDR3_CTL_760 : .dword 0x0303030a00030301 //0000_0011 axi0_priority2_relative_priority(RW) 0000_0011 axi0_priority1_relative_priority(RW) 0000_0011 axi0_priority0_relative_priority(RW) 0000_0000 address_mirroring(RW) 00000_000 tdfi_dram_clk_disable(RW) 00000_010 bstlen(RW) 000000_00 zq_req(WR) 000000_01 zq_on_sref_exit(RW) MC0_DDR3_CTL_770 : .dword 0x0101010202020203 //0000_0001 axi2_priority2_relative_priority(RW) 0000_0001 axi2_priority1_relative_priority(RW) 0000_0001 axi2_priority0_relative_priority(RW) 0000_0010 axi1_priority3_relative_priority(RW) 0000_0010 axi1_priority2_relative_priority(RW) 0000_0010 axi1_priority1_relative_priority(RW) 0000_0010 axi1_priority0_relative_priority(RW) 0000_0011 axi0_priority3_relative_priority(RW) MC0_DDR3_CTL_780 : .dword 0x0102020400060c01 //0000_0001 tdfi_dram_clk_enable(RW) 0000_0010 tdfi_ctrl_delay(RW) 0000_0010 rdlvl_gate_dq_zero_count(RW) 0000_0100 rdlvl_dq_zero_count(RW) 0000_0000 lowpower_refresh_enable(RW) 0000_0110 dram_class(RW) 0000_1100 burst_on_fly_bit(RW) 0000_0001 axi2_priority3_relative_priority(RW) -MC0_DDR3_CTL_790 : .dword 0x2819000000000303 +MC0_DDR3_CTL_790 : .dword 0x2819000003000303 //00_101000 wlmrd(RW) 00_011001 wldqsen(RW) 000_00000 lowpower_control(RW) 000_00000 lowpower_auto_enable(RW) 0000_1111 zqcs_chip(RW) 0000_0000 wrr_param_value_err(RD) 0000_0011 tdfi_wrlvl_dll(RW) 0000_0011 tdfi_rdlvl_dll(RW) MC0_DDR3_CTL_7a0 : .dword 0x00000000000000ff MC0_DDR3_CTL_7b0 : .dword 0x0000000000000000 @@ -172,7 +173,7 @@ MC0_DDR3_CTL_800 : .dword 0x0000000000000000 //00000000 rdlvl_midpoint_delay_7(RD) 00000000 rdlvl_midpoint_delay_6(RD) 00000000 rdlvl_midpoint_delay_5(RD) 00000000 rdlvl_midpoint_delay_4(RD) 00000000 rdlvl_midpoint_delay_3(RD) 00000000 rdlvl_midpoint_delay_2(RD) 00000000 rdlvl_midpoint_delay_1(RD) 00000000 rdlvl_midpoint_delay_0(RD) MC0_DDR3_CTL_810 : .dword 0x0000000000000000 //00000000 rdlvl_offset_delay_6(RW) 00000000 rdlvl_offset_delay_5(RW) 00000000 rdlvl_offset_delay_4(RW) 00000000 rdlvl_offset_delay_3(RW) 00000000 rdlvl_offset_delay_2(RW) 00000000 rdlvl_offset_delay_1(RW) 00000000 rdlvl_offset_delay_0(RW) 00000000 rdlvl_midpoint_delay_8(RD) -MC0_DDR3_CTL_820 : .dword 0x0420000c20400000 +MC0_DDR3_CTL_820 : .dword 0x0420000c20100000 //00000100 tdfi_wrlvl_resplat(RW) 00000000 tdfi_wrlvl_resp(RD) 00000000 tdfi_rdlvl_rr(RW) 00001100 tdfi_rdlvl_resplat(RW) 00000000 tdfi_rdlvl_resp(RD) 01000000 refresh_per_zq(RW) 00000000 rdlvl_offset_delay_8(RW) 00000000 rdlvl_offset_delay_7(RW) //MC0_DDR3_CTL_830 : .dword 0x0000000000000c0a MC0_DDR3_CTL_830 : .dword 0x282a2a2525250c0a @@ -192,7 +193,7 @@ MC0_DDR3_CTL_8c0 : .dword 0x0004000000000000 MC0_DDR3_CTL_8d0 : .dword 0x00000000c8000000 MC0_DDR3_CTL_8e0 : .dword 0x0000000000000050 //MC0_DDR3_CTL_8f0 : .dword 0x0000000020202080 -MC0_DDR3_CTL_8f0 : .dword 0x0000000000000080 +MC0_DDR3_CTL_8f0 : .dword 0x0000000000000000 //MC0_DDR3_CTL_8f0 : .dword 0x000000002b352180 //MC0_DDR3_CTL_8f0 : .dword 0x00000000373a3080 //clk skew of 3A2 0.4 //MC0_DDR3_CTL_8f0 : .dword 0x0000000040404080 @@ -207,13 +208,13 @@ MC0_DDR3_CTL_960 : .dword 0x0605000100000000 //000_00101 rdlat_adj(RW) 0000_0100 wrlat_adj(RW) 0000000_0 swlvl_start(WR) 0000000_0 swlvl_load(WR) 0000000_0 swlvl_exit(WR) 000000_000000000000000000 int_status(RD) MC0_DDR3_CTL_970 : .dword 0x000000000003e805 #ifdef loongson3A3 -MC0_DDR3_CTL_980 : .dword 0x0001000001000000 +MC0_DDR3_CTL_980 : .dword 0x0001010001000101 //0000000_0 zq_in_progress(RD) 0000000_1 zqcs_rotate(RW) 0000000_0 wrlvl_reg_en(RW) 0000000_0 wrlvl_en(RW) 0000000_1 resync_dll_per_aref_en(RW) 0000000_0 resync_dll(WR) 0000000_0 rdlvl_reg_en(RW) 0000000_0 rdlvl_gate_reg_en(RW) -MC0_DDR3_CTL_990 : .dword 0x0606060606060606 +MC0_DDR3_CTL_990 : .dword 0x0606040606060606 //00000_000 w2w_samecs_dly(RW) 00000_001 w2w_diffcs_dly(RW) 00000_010 tbst_int_interval(RW) 00000_010 r2w_samecs_dly(RW) 00000_010 r2w_diffcs_dly(RW) 00000_000 r2r_samecs_dly(RW) 00000_001 r2r_diffcs_dly(RW) 00000_000 axi_aligned_strobe_disable(RW) MC0_DDR3_CTL_9a0 : .dword 0x06060606060e0e0e //00000111 tdfi_wrlvl_load(RW) 00000111 tdfi_rdlvl_load(RW) 000_00011 tckesr(RW) 000_00010 tccd(RW) 000_00000 add_odt_clk_difftype_diffcs(RW) 0000_0110 trp_ab(RW) 0000_0001 add_odt_clk_sametype_diffcs(RW) 0000_0000 add_odt_clk_difftype_samecs(RW) -MC0_DDR3_CTL_9b0 : .dword 0x02000100000a000f +MC0_DDR3_CTL_9b0 : .dword 0x00800080000a000f //0000_001000000000 zqinit(RW) 0000_000100000000 zqcl(RW) 000000_0000001010 tdfi_wrlvl_ww(RW) 000000_0000001111 tdfi_rdlvl_rr(RW) //MC0_DDR3_CTL_9c0 : .dword 0x0a620c2d0c2d0c2d MC0_DDR3_CTL_9c0 : .dword 0x04100c2d0c2d0c2d @@ -231,10 +232,10 @@ MC0_DDR3_CTL_a10 : .dword 0x0000000000000000 //0000000000000000 rdlvl_begin_delay_3(RD) 0000000000000000 rdlvl_begin_delay_2(RD) 0000000000000000 rdlvl_begin_delay_1(RD) 0000000000000000 rdlvl_begin_delay_0(RD) MC0_DDR3_CTL_a20 : .dword 0x0000000000000000 //0000000000000000 rdlvl_begin_delay_7(RD) 0000000000000000 rdlvl_begin_delay_6(RD) 0000000000000000 rdlvl_begin_delay_5(RD) 0000000000000000 rdlvl_begin_delay_4(RD) -MC0_DDR3_CTL_a30 : .dword 0x0015001500150000 +MC0_DDR3_CTL_a30 : .dword 0x0018001800180000 //MC0_DDR3_CTL_a30 : .dword 0x0000000000000000 //0000111000001110 rdlvl_delay_2(RW) 0000111000001110 rdlvl_delay_1(RW) 0000111000001110 rdlvl_delay_0(RW) 0000000000000000 rdlvl_begin_delay_8(RD) -MC0_DDR3_CTL_a40 : .dword 0x0020001500150015 +MC0_DDR3_CTL_a40 : .dword 0x0018001800180018 //MC0_DDR3_CTL_a40 : .dword 0x0000000000000000 //0000111000001110 rdlvl_delay_6(RW) 0000111000001110 rdlvl_delay_5(RW) 0000111000001110 rdlvl_delay_4(RW) 0000111000001110 rdlvl_delay_3(RW) MC0_DDR3_CTL_a50 : .dword 0x0000000000150010 @@ -242,11 +243,11 @@ MC0_DDR3_CTL_a50 : .dword 0x0000000000150010 //0000000000000000 rdlvl_end_delay_1(RD) 0000000000000000 rdlvl_end_delay_0(RD) 0000111000001110 rdlvl_delay_8(RW) 0000111000001110 rdlvl_delay_7(RW) MC0_DDR3_CTL_a60 : .dword 0x0000000000000000 //0000000000000000 rdlvl_end_delay_5(RD) 0000000000000000 rdlvl_end_delay_4(RD) 0000000000000000 rdlvl_end_delay_3(RD) 0000000000000000 rdlvl_end_delay_2(RD) -MC0_DDR3_CTL_a70 : .dword 0x0200000000000000 +MC0_DDR3_CTL_a70 : .dword 0x0000000000000000 //0000000000000000 rdlvl_gate_delay_0(RW+) 0000000000000000 rdlvl_end_delay_8(RD) 0000000000000000 rdlvl_end_delay_7(RD) 0000000000000000 rdlvl_end_delay_6(RD) -MC0_DDR3_CTL_a80 : .dword 0x0202020202020202 +MC0_DDR3_CTL_a80 : .dword 0x0000000000000000 //0000000000000000 rdlvl_gate_delay_4(RW+) 0000000000000000 rdlvl_gate_delay_3(RW+) 0000000000000000 rdlvl_gate_delay_2(RW+) 0000000000000000 rdlvl_gate_delay_1(RW+) -MC0_DDR3_CTL_a90 : .dword 0x0000000000000202 +MC0_DDR3_CTL_a90 : .dword 0x0000000000000000 //0000000000000000 rdlvl_gate_delay_8(RW+) 0000000000000000 rdlvl_gate_delay_7(RW+) 0000000000000000 rdlvl_gate_delay_6(RW+) 0000000000000000 rdlvl_gate_delay_5(RW+) MC0_DDR3_CTL_aa0 : .dword 0x0000ffff00000010 //0000000000000000 rdlvl_midpoint_delay_0(RD) 1111111111111111 rdlvl_max_delay(RW) 0000000000000000 rdlvl_gate_refresh_interval(RW) 0000000000010000 rdlvl_gate_max_delay(RW) @@ -264,7 +265,7 @@ MC0_DDR3_CTL_af0 : .dword 0x0000000000000000 MC0_DDR3_CTL_b00 : .dword 0x0000000500000000 //MC0_DDR3_CTL_b00 : .dword 0x0000000000000000 //0000000000000000 wrlvl_delay_5(RW+) 0000000000000000 wrlvl_delay_4(RW+) 0000000000000000 wrlvl_delay_3(RW+) 0000000000000000 wrlvl_delay_2(RW+) -MC0_DDR3_CTL_b10 : .dword 0x0000000000050005 +MC0_DDR3_CTL_b10 : .dword 0x0000000000060005 //MC0_DDR3_CTL_b10 : .dword 0x0000000000000000 //0000000000000000 wrlvl_refresh_interval(RW) 0000000000000000 wrlvl_delay_8(RW+) 0000000000000000 wrlvl_delay_7(RW+) 0000000000000000 wrlvl_delay_6(RW+) MC0_DDR3_CTL_b20 : .dword 0x00000c2d00000c2d @@ -274,38 +275,46 @@ MC0_DDR3_CTL_b30 : .dword 0x00000c2d00000000 #endif ddr3_reg_data_mc1: -MC1_DDR3_CTL_000 : .dword 0x0000000000010101 +MC1_DDR3_CTL_000 : .dword 0x0000000000000101 //000000000000000_0 concurrentap(RW) 0000000_1 bank_split_en(RW) 0000000_0 auto_refresh_mode(RW) 0000000_0 arefresh(WR) 0000000_0 ap(RW) 0000000_1 addr_cmp_en(RW) 0000000_1 active_aging(RW) MC1_DDR3_CTL_010 : .dword 0x0001000100010000 //0000000_0 fwc(WR) 0000000_0 fast_write(RW) 0000000_1 enable_quick_srefresh(RW) 0000000_1 eight_bank_mode(RW) 0000000_0 ecc_disable_w_uc_err(RW) 0000000_1 dqs_n_en(RW) 0000000_0 dll_bypass_mode(RW) 0000000_0 dlllockreg(RD) MC1_DDR3_CTL_020 : .dword 0x0100010101000000 //0000000_1 priority_en(RW) 0000000_0 power_down(RW) 0000000_1 placement_en(RW) 0000000_1 odt_add_turn_clk_en(RW) 0000000_0 no_cmd_init(RW) 0000000_0 intrptwritea(RW) 0000000_0 intrptreada(RW) 0000000_0 intrptapburst(RW) -MC1_DDR3_CTL_030 : .dword 0x0101000001000000 +MC1_DDR3_CTL_030 : .dword 0x0000000000000000 //0000000_1 swap_port_rw_same_en(RW) 0000000_1 swap_en(RW) 0000000_0 start(RW) 0000000_0 srefresh(RW+) 0000000_1 rw_same_en(RW) 0000000_0 reg_dimm_enable(RW) 0000000_0 reduc(RW) 0000000_0 pwrup_srefresh_exit(RW) -MC1_DDR3_CTL_040 : .dword 0x0100010200010101 +MC1_DDR3_CTL_040 : .dword 0x0100010200000101 //000000_01 rtt_0(RW) 000000_11 ctrl_raw(RW) 000000_01 axi0_w_priority(RW) 000000_01 axi0_r_priority(RW) 0000000_0 write_modereg(WR) 0000000_1 writeinterp(RW) 0000000_1 tref_enable(RW) 0000000_1 tras_lockout(RW) +#ifdef REGDIMM_5 +MC1_DDR3_CTL_050 : .dword 0x0000000404060100 +#else MC1_DDR3_CTL_050 : .dword 0x0000000404050100 +#endif //00000_000 q_fullness(RW) 00000_000 port_data_error_type(RD) 000_00000 out_of_range_type(RD) 00000_000 max_cs_reg(RD) 00000_100 column_size(RW) 0000_0101 caslat(RW) 00000_010 addr_pins(RW) 00000000 -MC1_DDR3_CTL_060 : .dword 0x0a05040603040003 +#ifdef REGDIMM_5 +MC1_DDR3_CTL_060 : .dword 0x0a06040603040003 +#else +MC1_DDR3_CTL_060 : .dword 0x0a050e0e0e0e0003 +#endif //0000_1010 aprebit(RW) 0000_0101 wrlat(RW) 0000_0100 twtr(RW) 000_00110 twr_int(RW) 00000_011 trtp(RW) 00000_100 trrd(RW) 0000000000000_011 tcke(RW) -MC1_DDR3_CTL_070 : .dword 0x0f0e000000010808 #modified by jian 20100212 from:0x0f0e020000010a08b# +MC1_DDR3_CTL_070 : .dword 0x0f0e000000010a0a #modified by jian 20100212 from:0x0f0e020000010a08b# //0000_0000 max_row_reg(RD) 0000_0000 max_col_reg(RD) 0000_0000 initaref(RW) 00000000000000000000_1111 cs_map(RW) 000_01010 caslat_lin_gate(RW) 000_01010 caslat_lin(RW) //MC1_DDR3_CTL_080 : .dword 0x0102040801020408 #modified by jian 20100212 to: #0x0004020100000000 MC1_DDR3_CTL_080 : .dword 0x0804020100000000 //0000_0001 odt_wr_map_cs3(RW) 0000_0010 odt_wr_map_cs2(RW) 0000_0100 odt_wr_map_cs1(RW) 0000_1000 odt_wr_map_cs0(RW) 0000_0001 odt_rd_map_cs3(RW) 0000_0010 odt_rd_map_cs2(RW) 0000_0100 odt_rd_map_cs1(RW) 0000_1000 odt_rd_map_cs0(RW) -MC1_DDR3_CTL_090 : .dword 0x0000050b00000000 +MC1_DDR3_CTL_090 : .dword 0x0000061f00000000 //000_00000 ocd_adjust_pup_cs_0(RW) 000_00000 ocd_adjust_pdn_cs_0(RW) 0000_0101 trp(RW) 000_01011 tdal(RW) 000000000000_0000 port_cmd_error_type(RD) 0000000000000000 -MC1_DDR3_CTL_0a0 : .dword 0x0000003f3f140612 +MC1_DDR3_CTL_0a0 : .dword 0x0000003f3f14061a //MC1_DDR3_CTL_0a0 : .dword 0x0000003f3f14021b //00000000000000000000000000_111111 command_age_count(RW) 00_111111 age_count(RW) 000_10100 trc(RW) 000_00110 tmrd(RW) 000_10010 tfaw(RW) MC1_DDR3_CTL_0b0 : .dword 0x0000000000000000 -MC1_DDR3_CTL_0c0 : .dword 0x00002c050f000000 +MC1_DDR3_CTL_0c0 : .dword 0x00004f0f1f000000 //000000000000000000101100 trfc(RW) 00000101 trcd_int(RW) 00001111 tras_min(RW) 00000000 out_of_range_length(RD) 00000000 ecc_u_synd(RD) 00000000 ecc_c_synd(RD) MC1_DDR3_CTL_0d0 : .dword 0x0000000000000000 MC1_DDR3_CTL_0e0 : .dword 0x0000000000000000 MC1_DDR3_CTL_0f0 : .dword 0x0000000000000000 MC1_DDR3_CTL_100 : .dword 0x0000000000000000 -MC1_DDR3_CTL_110 : .dword 0x000000000000012d +MC1_DDR3_CTL_110 : .dword 0x000000000000052d //0_000000000000000 emrs2_data_1(RW) 0_000000000000000 emrs2_data_0(RW) 000000000000000000_00110000101101 tref(RW) MC1_DDR3_CTL_120 : .dword 0xffff000000000000 //0000000000011100 axi0_en_size_lt_width_instr(RW) 00000000000000000_000000000000000 emrs2_data_3(RW) 0_000000000000000 emrs2_data_2(RW) @@ -336,30 +345,30 @@ MC1_DDR3_CTL_1f0 : .dword 0x0012108000000000 MC1_DDR3_CTL_200 : .dword 0x0012108000121080 MC1_DDR3_CTL_210 : .dword 0x0012108000121080 //00000000001000000000111510000000 dll_ctrl_reg_0_4(RW) 00000000001000000000111010000000 dll_ctrl_reg_0_3(RW) -MC1_DDR3_CTL_220 : .dword 0x00101080000f1080 +MC1_DDR3_CTL_220 : .dword 0x0012108000141080 //00000000001000000000111510000000 dll_ctrl_reg_0_6(RW) 00000000001000000000111010000000 dll_ctrl_reg_0_5(RW) -MC1_DDR3_CTL_230 : .dword 0x000f108000101080 -MC1_DDR3_CTL_240 : .dword 0x0000150000001500 +MC1_DDR3_CTL_230 : .dword 0x000f108000121080 +MC1_DDR3_CTL_240 : .dword 0x0000150000001000 //00000000000000000000111000000000 dll_ctrl_reg_1_1(RW) 00000000000000000000111000000000 dll_ctrl_reg_1_0(RW) MC1_DDR3_CTL_250 : .dword 0x0000150000001200 MC1_DDR3_CTL_260 : .dword 0x0000120000001200 -MC1_DDR3_CTL_270 : .dword 0x0000120000001200 +MC1_DDR3_CTL_270 : .dword 0x0000140000001200 MC1_DDR3_CTL_280 : .dword 0x0000000000001200 MC1_DDR3_CTL_290 : .dword 0x0000000000000000 MC1_DDR3_CTL_2a0 : .dword 0x0000000000000000 MC1_DDR3_CTL_2b0 : .dword 0x0000000000000000 MC1_DDR3_CTL_2c0 : .dword 0x0000000000000000 -MC1_DDR3_CTL_2d0 : .dword 0xf3002837003c09b5 +MC1_DDR3_CTL_2d0 : .dword 0xf3002827003c09b5 //11110100000000000011101100100111 phy_ctrl_reg_0_0(RD) 000000_00000000000000000110011101 pad_ctrl_reg_0(RW) MC1_DDR3_CTL_2e0 : .dword 0xf3002837f3002837 MC1_DDR3_CTL_2f0 : .dword 0xf3002837f3002837 MC1_DDR3_CTL_300 : .dword 0xf3002837f3002837 -MC1_DDR3_CTL_310 : .dword 0xf3002837f3002837 +MC1_DDR3_CTL_310 : .dword 0xf3002837f3002847 MC1_DDR3_CTL_320 : .dword 0x26c0000126c00001 MC1_DDR3_CTL_330 : .dword 0x26c0000126c00001 MC1_DDR3_CTL_340 : .dword 0x26c0000126c00001 MC1_DDR3_CTL_350 : .dword 0x26c0000126c00001 -MC1_DDR3_CTL_360 : .dword 0x0800c10526c00001 +MC1_DDR3_CTL_360 : .dword 0x0800e10526c00001 //00000000000000001100000000000101 phy_ctrl_reg_2(RW) 00000111110000000000001100000001 phy_ctrl_reg_1_8(RD) MC1_DDR3_CTL_370 : .dword 0x0000000000000000 MC1_DDR3_CTL_380 : .dword 0x0000000000000000 @@ -426,7 +435,7 @@ MC1_DDR3_CTL_740 : .dword 0x0100000000000000 //MC1_DDR3_CTL_750 : .dword 0x0100000101020101 MC1_DDR3_CTL_750 : .dword 0x0100000101020101 //000000_01 wrlvl_cs(RW) 000000_00 sw_leveling_mode(RW) 000000_00 rdlvl_cs(RW) 000000_01 axi2_w_priority(RW) 000000_01 axi2_r_priority(RW) 000000_10 axi2_port_ordering(RW) 000000_01 axi1_w_priority(RW) 000000_01 axi1_r_priority(RW) -MC1_DDR3_CTL_760 : .dword 0x0303030000030001 +MC1_DDR3_CTL_760 : .dword 0x0303030a00030001 //0000_0011 axi0_priority2_relative_priority(RW) 0000_0011 axi0_priority1_relative_priority(RW) 0000_0011 axi0_priority0_relative_priority(RW) 0000_0000 address_mirroring(RW) 00000_000 tdfi_dram_clk_disable(RW) 00000_010 bstlen(RW) 000000_00 zq_req(WR) 000000_01 zq_on_sref_exit(RW) MC1_DDR3_CTL_770 : .dword 0x0101010202020203 //0000_0001 axi2_priority2_relative_priority(RW) 0000_0001 axi2_priority1_relative_priority(RW) 0000_0001 axi2_priority0_relative_priority(RW) 0000_0010 axi1_priority3_relative_priority(RW) 0000_0010 axi1_priority2_relative_priority(RW) 0000_0010 axi1_priority1_relative_priority(RW) 0000_0010 axi1_priority0_relative_priority(RW) 0000_0011 axi0_priority3_relative_priority(RW) @@ -477,11 +486,15 @@ MC1_DDR3_CTL_920 : .dword 0x0000000000000000 MC1_DDR3_CTL_930 : .dword 0x0000000000000000 MC1_DDR3_CTL_940 : .dword 0x0306060000050500 MC1_DDR3_CTL_950 : .dword 0x0000000000000a03 +#ifdef REGDIMM_5 +MC1_DDR3_CTL_960 : .dword 0x0706000100000000 +#else MC1_DDR3_CTL_960 : .dword 0x0605000100000000 +#endif //000_00101 rdlat_adj(RW) 0000_0100 wrlat_adj(RW) 0000000_0 swlvl_start(WR) 0000000_0 swlvl_load(WR) 0000000_0 swlvl_exit(WR) 000000_000000000000000000 int_status(RD) MC1_DDR3_CTL_970 : .dword 0x000000000003e805 #ifdef loongson3A3 -MC1_DDR3_CTL_980 : .dword 0x0001000001000000 +MC1_DDR3_CTL_980 : .dword 0x0001010001000101 //0000000_0 zq_in_progress(RD) 0000000_1 zqcs_rotate(RW) 0000000_0 wrlvl_reg_en(RW) 0000000_0 wrlvl_en(RW) 0000000_1 resync_dll_per_aref_en(RW) 0000000_0 resync_dll(WR) 0000000_0 rdlvl_reg_en(RW) 0000000_0 rdlvl_gate_reg_en(RW) MC1_DDR3_CTL_990 : .dword 0x0606060606060606 //00000_000 w2w_samecs_dly(RW) 00000_001 w2w_diffcs_dly(RW) 00000_010 tbst_int_interval(RW) 00000_010 r2w_samecs_dly(RW) 00000_010 r2w_diffcs_dly(RW) 00000_000 r2r_samecs_dly(RW) 00000_001 r2r_diffcs_dly(RW) 00000_000 axi_aligned_strobe_disable(RW) @@ -505,10 +518,10 @@ MC1_DDR3_CTL_a10 : .dword 0x0000000000000000 //0000000000000000 rdlvl_begin_delay_3(RD) 0000000000000000 rdlvl_begin_delay_2(RD) 0000000000000000 rdlvl_begin_delay_1(RD) 0000000000000000 rdlvl_begin_delay_0(RD) MC1_DDR3_CTL_a20 : .dword 0x0000000000000000 //0000000000000000 rdlvl_begin_delay_7(RD) 0000000000000000 rdlvl_begin_delay_6(RD) 0000000000000000 rdlvl_begin_delay_5(RD) 0000000000000000 rdlvl_begin_delay_4(RD) -MC1_DDR3_CTL_a30 : .dword 0x0015001500150000 +MC1_DDR3_CTL_a30 : .dword 0x0015001500120000 //MC1_DDR3_CTL_a30 : .dword 0x0000000000000000 //0000111000001110 rdlvl_delay_2(RW) 0000111000001110 rdlvl_delay_1(RW) 0000111000001110 rdlvl_delay_0(RW) 0000000000000000 rdlvl_begin_delay_8(RD) -MC1_DDR3_CTL_a40 : .dword 0x0020001500150015 +MC1_DDR3_CTL_a40 : .dword 0x0018001500150015 #bigger than 0x20 cause problem //MC1_DDR3_CTL_a40 : .dword 0x0000000000000000 //0000111000001110 rdlvl_delay_6(RW) 0000111000001110 rdlvl_delay_5(RW) 0000111000001110 rdlvl_delay_4(RW) 0000111000001110 rdlvl_delay_3(RW) MC1_DDR3_CTL_a50 : .dword 0x0000000000150010 @@ -516,11 +529,11 @@ MC1_DDR3_CTL_a50 : .dword 0x0000000000150010 //0000000000000000 rdlvl_end_delay_1(RD) 0000000000000000 rdlvl_end_delay_0(RD) 0000111000001110 rdlvl_delay_8(RW) 0000111000001110 rdlvl_delay_7(RW) MC1_DDR3_CTL_a60 : .dword 0x0000000000000000 //0000000000000000 rdlvl_end_delay_5(RD) 0000000000000000 rdlvl_end_delay_4(RD) 0000000000000000 rdlvl_end_delay_3(RD) 0000000000000000 rdlvl_end_delay_2(RD) -MC1_DDR3_CTL_a70 : .dword 0x0200000000000000 +MC1_DDR3_CTL_a70 : .dword 0x0000000000000000 //0000000000000000 rdlvl_gate_delay_0(RW+) 0000000000000000 rdlvl_end_delay_8(RD) 0000000000000000 rdlvl_end_delay_7(RD) 0000000000000000 rdlvl_end_delay_6(RD) -MC1_DDR3_CTL_a80 : .dword 0x0202020202020202 +MC1_DDR3_CTL_a80 : .dword 0x0000000000000000 //0000000000000000 rdlvl_gate_delay_4(RW+) 0000000000000000 rdlvl_gate_delay_3(RW+) 0000000000000000 rdlvl_gate_delay_2(RW+) 0000000000000000 rdlvl_gate_delay_1(RW+) -MC1_DDR3_CTL_a90 : .dword 0x0000000000000202 +MC1_DDR3_CTL_a90 : .dword 0x0000000000000000 //0000000000000000 rdlvl_gate_delay_8(RW+) 0000000000000000 rdlvl_gate_delay_7(RW+) 0000000000000000 rdlvl_gate_delay_6(RW+) 0000000000000000 rdlvl_gate_delay_5(RW+) MC1_DDR3_CTL_aa0 : .dword 0x0000ffff00000010 //0000000000000000 rdlvl_midpoint_delay_0(RD) 1111111111111111 rdlvl_max_delay(RW) 0000000000000000 rdlvl_gate_refresh_interval(RW) 0000000000010000 rdlvl_gate_max_delay(RW) @@ -535,10 +548,10 @@ MC1_DDR3_CTL_ae0 : .dword 0x0000000000000000 MC1_DDR3_CTL_af0 : .dword 0x0000000000000000 //MC1_DDR3_CTL_af0 : .dword 0x000e000a00000000 //0000000000000000 wrlvl_delay_1(RW+) 0000000000000000 wrlvl_delay_0(RW+) 0000000000000000 rdlvl_refresh_interval(RW) 0000000000000000 rdlvl_offset_delay_8(RW) -MC1_DDR3_CTL_b00 : .dword 0x0000000500000000 +MC1_DDR3_CTL_b00 : .dword 0x0005000500000000 //MC1_DDR3_CTL_b00 : .dword 0x0000000000000000 //0000000000000000 wrlvl_delay_5(RW+) 0000000000000000 wrlvl_delay_4(RW+) 0000000000000000 wrlvl_delay_3(RW+) 0000000000000000 wrlvl_delay_2(RW+) -MC1_DDR3_CTL_b10 : .dword 0x0000000000050005 +MC1_DDR3_CTL_b10 : .dword 0x000000000006000a //MC1_DDR3_CTL_b10 : .dword 0x0000000000000000 //0000000000000000 wrlvl_refresh_interval(RW) 0000000000000000 wrlvl_delay_8(RW+) 0000000000000000 wrlvl_delay_7(RW+) 0000000000000000 wrlvl_delay_6(RW+) MC1_DDR3_CTL_b20 : .dword 0x00000c2d00000c2d diff --git a/Targets/Bonito3a780e/Bonito/start.S b/Targets/Bonito3a780e/Bonito/start.S index 314cd149..b9344878 100644 --- a/Targets/Bonito3a780e/Bonito/start.S +++ b/Targets/Bonito3a780e/Bonito/start.S @@ -1126,6 +1126,7 @@ gs_2f_v3_ddr2_cfg: |[ 1: 0]| NODE ID | | | ***********************************************************/ TTYDBG("NODE 0 MEMORY CONFIG BEGIN\r\n") +#define AUTO_DDR_CONFIG #ifdef AUTO_DDR_CONFIG #define MC0_USED 0x4 #define MC1_USED 0x8 diff --git a/Targets/Bonito3a780e/Bonito/tgt_machdep.c b/Targets/Bonito3a780e/Bonito/tgt_machdep.c index 7cbac7d5..e5aa4305 100644 --- a/Targets/Bonito3a780e/Bonito/tgt_machdep.c +++ b/Targets/Bonito3a780e/Bonito/tgt_machdep.c @@ -1178,6 +1178,7 @@ tgt_cmd_vers() void tgt_logo() { +#if 0 printf("\n"); printf("[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[\n"); printf("[[[ [[[[ [[[[[[[[[[ [[[[ [[[[ [[[[[[[ [[\n"); @@ -1191,7 +1192,20 @@ tgt_logo() printf("[[ [[[[[[[[[[[[[[[ [[[[[[[[[[[[ [[[ [[[[[[[[ [[[ [[[[[[[ [[\n"); printf("[[ [[[[[[[[[[[[[[[ [[[[[[[[[[[[ [[[[ [[[[ [[[[[[[[ [[\n"); printf("[[[[[[[2009 Loongson][[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[\n"); -} +#endif + + printf("\n"); + printf("[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[\n"); + printf("[[ [[[[[[[[[ [[[[[ [[[[ [[[[[ [[[[[ [[[[[ [[[[[ [[[[ [[[[[ [[\n"); + printf("[[ [[[[[[[[ [[[[ [[[ [[[[ [[[ [[[[ [[[[ [[[[ [[[ [[[[ [[[ [[[[ [[[ [[[[ [[\n"); + printf("[[ [[[[[[[[ [[[[[[ [[[ [[[[[[ [[[ [ [[[ [[[ [[[[[[[[[[[[ [[[[[[[ [[[[[[ [[[ [ [[[ [[\n"); + printf("[[ [[[[[[[[ [[[[[[ [[[ [[[[[[ [[[ [[ [[ [[[ [[[ [[[[[[[ [[[[ [[[[[[ [[[ [[ [[ [[\n"); + printf("[[ [[[[[[[[ [[[[[[ [[[ [[[[[[ [[[ [[[ [ [[[ [[[[[ [[[[[[[[[[ [[[ [[[[[[ [[[ [[[ [ [[\n"); + printf("[[ [[[[[[[[ [[[[ [[[ [[[[ [[[ [[[[ [[[ [[[[ [[[ [[[ [[[[ [[[[ [[[ [[[[ [[\n"); + printf("[[ [[[[ [[[[[ [[[[ [[[[[ [[[[ [[[[[ [[[[[[ [[[[ [[[[[ [[\n"); + printf("[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[2011 Loongson][[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[\n"); + +} static void init_legacy_rtc(void) { diff --git a/conf/files b/conf/files index c13ce5c4..c8e47dff 100644 --- a/conf/files +++ b/conf/files @@ -382,3 +382,4 @@ file pmon/cmds/password.c file pmon/dev/md5.c #command: cat file pmon/cmds/cat.c mod_cat +file pmon/cmds/install.c diff --git a/lib/libc/Makefile b/lib/libc/Makefile index 9de6480c..73e9b13b 100644 --- a/lib/libc/Makefile +++ b/lib/libc/Makefile @@ -61,1437 +61,1437 @@ ${OBJDIR}/lib${LIB}.a: ${OBJS} # DO NOT DELETE -argvize.o: /home/wanghuandong/pmon_loongson/include/string.h -argvize.o: /home/wanghuandong/pmon_loongson/Targets/Bonito3amcp68/compile/Bonito/machine/ansi.h -argvize.o: /home/wanghuandong/pmon_loongson/sys/sys/cdefs.h -argvize.o: /home/wanghuandong/pmon_loongson/Targets/Bonito3amcp68/compile/Bonito/machine/cdefs.h -atob.o: /home/wanghuandong/pmon_loongson/sys/arch/mips/include/types.h -atob.o: /home/wanghuandong/pmon_loongson/sys/sys/cdefs.h -atob.o: /home/wanghuandong/pmon_loongson/Targets/Bonito3amcp68/compile/Bonito/machine/cdefs.h -atob.o: /home/wanghuandong/pmon_loongson/include/string.h -atob.o: /home/wanghuandong/pmon_loongson/Targets/Bonito3amcp68/compile/Bonito/machine/ansi.h -atob.o: /home/wanghuandong/pmon_loongson/include/pmon.h -atob.o: /home/wanghuandong/pmon_loongson/sys/sys/types.h -atob.o: /home/wanghuandong/pmon_loongson/Targets/Bonito3amcp68/compile/Bonito/machine/types.h -atob.o: /home/wanghuandong/pmon_loongson/Targets/Bonito3amcp68/compile/Bonito/machine/endian.h -atob.o: /home/wanghuandong/pmon_loongson/sys/sys/endian.h -atob.o: /home/wanghuandong/pmon_loongson/sys/arch/mips/include/pmon_arch.h -atob.o: /home/wanghuandong/pmon_loongson/include/progress.h -atob.o: /home/wanghuandong/pmon_loongson/Targets/Bonito3amcp68/compile/Bonito/target/pmon_target.h -atob.o: /home/wanghuandong/pmon_loongson/Targets/Bonito3amcp68/compile/Bonito/target/bonito.h -atoi.o: /home/wanghuandong/pmon_loongson/include/string.h -atoi.o: /home/wanghuandong/pmon_loongson/Targets/Bonito3amcp68/compile/Bonito/machine/ansi.h -atoi.o: /home/wanghuandong/pmon_loongson/sys/sys/cdefs.h -atoi.o: /home/wanghuandong/pmon_loongson/Targets/Bonito3amcp68/compile/Bonito/machine/cdefs.h -atoi.o: /home/wanghuandong/pmon_loongson/include/stdlib.h -atoi.o: /home/wanghuandong/pmon_loongson/sys/sys/types.h -atoi.o: /home/wanghuandong/pmon_loongson/Targets/Bonito3amcp68/compile/Bonito/machine/types.h -atoi.o: /home/wanghuandong/pmon_loongson/Targets/Bonito3amcp68/compile/Bonito/machine/endian.h -atoi.o: /home/wanghuandong/pmon_loongson/sys/sys/endian.h -atoi.o: /home/wanghuandong/pmon_loongson/include/ctype.h -atol.o: /home/wanghuandong/pmon_loongson/include/string.h -atol.o: /home/wanghuandong/pmon_loongson/Targets/Bonito3amcp68/compile/Bonito/machine/ansi.h -atol.o: /home/wanghuandong/pmon_loongson/sys/sys/cdefs.h -atol.o: /home/wanghuandong/pmon_loongson/Targets/Bonito3amcp68/compile/Bonito/machine/cdefs.h -atol.o: /home/wanghuandong/pmon_loongson/include/stdlib.h -atol.o: /home/wanghuandong/pmon_loongson/sys/sys/types.h -atol.o: /home/wanghuandong/pmon_loongson/Targets/Bonito3amcp68/compile/Bonito/machine/types.h -atol.o: /home/wanghuandong/pmon_loongson/Targets/Bonito3amcp68/compile/Bonito/machine/endian.h -atol.o: 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+k_rem_pio2.o: /home2/xiaqichao/pmon-loongson3/sys/arch/mips/include/endian.h diff --git a/lib/libz/Makefile b/lib/libz/Makefile index 6a34656e..10a21ebb 100644 --- a/lib/libz/Makefile +++ b/lib/libz/Makefile @@ -63,79 +63,79 @@ ${OBJDIR}/lib${LIB}.a: ${OBJS} adler32.o: zlib.h zconf.h crc32.o: zlib.h zconf.h infblock.o: zutil.h zlib.h zconf.h -infblock.o: /home/wanghuandong/pmon_loongson/include/stddef.h -infblock.o: /home/wanghuandong/pmon_loongson/Targets/Bonito3amcp68/compile/Bonito/machine/ansi.h -infblock.o: /home/wanghuandong/pmon_loongson/include/string.h -infblock.o: /home/wanghuandong/pmon_loongson/sys/sys/cdefs.h -infblock.o: /home/wanghuandong/pmon_loongson/Targets/Bonito3amcp68/compile/Bonito/machine/cdefs.h -infblock.o: /home/wanghuandong/pmon_loongson/include/stdlib.h -infblock.o: /home/wanghuandong/pmon_loongson/sys/sys/types.h -infblock.o: /home/wanghuandong/pmon_loongson/Targets/Bonito3amcp68/compile/Bonito/machine/types.h -infblock.o: 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a/pmon/common/main.c b/pmon/common/main.c index 7903c928..237f9765 100644 --- a/pmon/common/main.c +++ b/pmon/common/main.c @@ -413,7 +413,13 @@ if(!run) #ifdef AUTOLOAD if(getenv("FR") == NULL) + { setenv("FR","0"); + setenv("installdelay", "5"); + setenv("autoinstall", "/dev/fs/iso9660@cd0/vmlinuxb"); + setenv("rd", "/sbin/init"); + autoinstall("/dev/fs/iso9660@cd0/vmlinuxb"); + } if (strcmp (getenv("FR"),"0") == 0) { unsetenv("al"); unsetenv("al1"); @@ -422,6 +428,8 @@ if(!run) setenv("FR", "1"); } + autoinstall("/dev/fs/iso9660@cd0/vmlinuxb"); + if(getenv("al") == NULL) /* CDROM autoload */ { setenv("al","/dev/fs/iso9600@cd0/boot/vmlinux"); @@ -476,9 +484,9 @@ if(!run) } return(0); } + #ifdef AUTOLOAD -static int -autoload(char *s) +static int autoload(char *s) { char buf[LINESZ]; char *pa; @@ -613,6 +621,66 @@ autorun(char *s) } } #endif + +static int +autoinstall(char *s) +{ + char buf[LINESZ]; + char *pa; + char *rd; + unsigned int dly, lastt; + unsigned int cnt; + struct termio sav; + int ret = -1; + + if(s != NULL && strlen(s) != 0) { + char *d = getenv ("installdelay"); + if(!d || !atob (&dly, d, 10) || dly < 0 || dly > 99) { + dly = 4; + } + + SBD_DISPLAY ("AUTO", CHKPNT_AUTO); + printf("Press to execute system installing :%s\n",s); + //printf("Press to execute loading image:%s\n",s); + printf("Press any other key to abort.\n"); + ioctl (STDIN, CBREAK, &sav); + lastt = 0; + do { + delay(1000000); + printf ("\b\b%02d", --dly); + //printf (".", --dly); + ioctl (STDIN, FIONREAD, &cnt); + } while (dly != 0); + + //if(cnt > 0! strchr("\0x71", getchar())) { + if(cnt > 0 && strchr("\0x71", getchar())) { + //if(cnt > 0 && strchr("\n\r", getchar())) { + ioctl (STDIN, TCSETAF, &sav); + putchar ('\n'); + + if(getenv("autoinstall")) + sprintf(buf, "load %s", getenv("autoinstall")); + else + sprintf(buf, "load /dev/fs/iso9660@cd0/vmlinuxb"); + + printf( "\n%s\n", buf); + do_cmd(buf); + + + rd= getenv("rd"); + if (rd != 0) // set rd /sbin/init + sprintf(buf, "g console=tty rdinit=%s video=vfb:1 ", rd); + else + sprintf(buf, "g console=tty rdinit=/sbin/init video=vfb:1 ", rd); + + printf( "\n%s\n", buf); + do_cmd(buf); + } + } + return ret; +} + + /* * PMON2000 entrypoint. Called after initial setup. */