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Target: 3aserver 

1. fixup no output on UART when system up

2. enable 495MHz ddr3_rdimm param (NOT test when the frequency is low)

3. enable ddr3 leveling in 3aserver
master
Wang Huandong 12 years ago
committed by wanghongmei
parent
b0850d6714
commit
9d15d2086c
3 changed files with 35 additions and 31 deletions
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  1. 47
      Targets/Bonito3aserver/Bonito/loongson3A3_ddr_param.S
  2. 17
      Targets/Bonito3aserver/Bonito/start.S
  3. 2
      Targets/Bonito3aserver/conf/Bonito.3aserver

47
Targets/Bonito3aserver/Bonito/loongson3A3_ddr_param.S
View File

@ -308,11 +308,11 @@ MC0_DDR3_RDIMM_CTL_020 : .dword 0x0100010000000000
//0000000_1 priority_en(RW) 0000000_0 power_down(RW) 0000000_1 placement_en(RW) 0000000_0 odt_add_turn_clk_en(RD) 0000000_0 no_cmd_init(RW) 0000000_0 intrptwritea(RW) 0000000_0 intrptreada(RW) 0000000_0 intrptapburst(RW)
MC0_DDR3_RDIMM_CTL_030 : .dword 0x0001000001010000
//0000000_1 swap_port_rw_same_en(RW) 0000000_1 swap_en(RW) 0000000_0 start(RW) 0000000_0 srefresh(RW+) 0000000_1 rw_same_en(RW) 0000000_0 reg_dimm_enable(RW) 0000000_0 reduc(RW) 0000000_0 pwrup_srefresh_exit(RW)
MC0_DDR3_RDIMM_CTL_040 : .dword 0x0002010200000101
MC0_DDR3_RDIMM_CTL_040 : .dword 0x0102010200000101
//000000_00 rtt_0(RD) 000000_11 ctrl_raw(RW) 000000_01 axi0_w_priority(RW) 000000_01 axi0_r_priority(RW) 0000000_0 write_modereg(WR) 0000000_1 writeinterp(RW) 0000000_1 tref_enable(RW) 0000000_1 tras_lockout(RW)
MC0_DDR3_RDIMM_CTL_050 : .dword 0x0700000004060100
MC0_DDR3_RDIMM_CTL_050 : .dword 0x0700000004070100
//00000_000 q_fullness(RW) 00000_000 port_data_error_type(RD) 000_00000 out_of_range_type(RD) 00000_000 max_cs_reg(RD) 00000_100 column_size(RW) 0000_0101 caslat(RW) 00000_010 addr_pins(RW) 00000000
MC0_DDR3_RDIMM_CTL_060 : .dword 0x0a05040804040003
MC0_DDR3_RDIMM_CTL_060 : .dword 0x0a06040804040003
//0000_1010 aprebit(RW) 0000_0101 wrlat(RW) 0000_0100 twtr(RW) 000_00110 twr_int(RW) 00000_011 trtp(RW) 00000_100 trrd(RW) 0000000000000_011 tcke(RW)
MC0_DDR3_RDIMM_CTL_070 : .dword 0x0000020000030c0c
//0000_1111 max_row_reg(RD) 0000_1110 max_col_reg(RD) 0000_0000 initaref(RW) 00000000000000000000_1111 cs_map(RW) 000_01010 caslat_lin_gate(RW) 000_01010 caslat_lin(RW)
@ -320,7 +320,7 @@ MC0_DDR3_RDIMM_CTL_080 : .dword 0x0804020100000000
//0000_0001 odt_wr_map_cs3(RW) 0000_0010 odt_wr_map_cs2(RW) 0000_0100 odt_wr_map_cs1(RW) 0000_1000 odt_wr_map_cs0(RW) 0000_0001 odt_rd_map_cs3(RW) 0000_0010 odt_rd_map_cs2(RW) 0000_0100 odt_rd_map_cs1(RW) 0000_1000 odt_rd_map_cs0(RW)
MC0_DDR3_RDIMM_CTL_090 : .dword 0x0000081100000000
//000_00000 ocd_adjust_pup_cs_0(RW) 000_00000 ocd_adjust_pdn_cs_0(RW) 0000_0101 trp(RW) 000_01011 tdal(RW) 000000000000_0000 port_cmd_error_type(RD) 0000000000000000
MC0_DDR3_RDIMM_CTL_0a0 : .dword 0x0000000f3f1b0410
MC0_DDR3_RDIMM_CTL_0a0 : .dword 0x0000003f3f1b0410
//00000000000000000000000000_111111 command_age_count(RW) 00_111111 age_count(RW) 000_10100 trc(RW) 000_00110 tmrd(RW) 000_10010 tfaw(RW)
MC0_DDR3_RDIMM_CTL_0b0 : .dword 0x0000000000000000
MC0_DDR3_RDIMM_CTL_0c0 : .dword 0x00003b0814000000
@ -331,15 +331,15 @@ MC0_DDR3_RDIMM_CTL_0f0 : .dword 0x0000000000000000
//Bit 21:16 dll_lock(RD)
MC0_DDR3_RDIMM_CTL_100 : .dword 0x0000000000000000
//MC0_DDR3_RDIMM_CTL_110 : .dword 0x00000000000005e0 #200M+
MC0_DDR3_RDIMM_CTL_110 : .dword 0x0000000000000900 #300M+
//MC0_DDR3_RDIMM_CTL_110 : .dword 0x0000000000000c00 #400M+
//MC0_DDR3_RDIMM_CTL_110 : .dword 0x0000000000000900 #300M+
MC0_DDR3_RDIMM_CTL_110 : .dword 0x0000000000000c00 #400M+
//MC0_DDR3_RDIMM_CTL_110 : .dword 0x0000000000000f20 #500M+
//0_000000000000000 emrs2_data_1(RW) 0_000000000000000 emrs2_data_0(RW) 000000000000000000_00110000101101 tref(RW)
MC0_DDR3_RDIMM_CTL_120 : .dword 0x5555000000000000
//0000000000011100 axi0_en_size_lt_width_instr(RW) hXXXX 0_000000000000000 emrs2_data_3(RW) 0_000000000000000 emrs2_data_2(RW)
//MC0_DDR3_RDIMM_CTL_130 : .dword 0x36800003020001a7 #200M+
MC0_DDR3_RDIMM_CTL_130 : .dword 0x52100003020000a7 #300M+
//MC0_DDR3_RDIMM_CTL_130 : .dword 0x6d800003020000a7 #400M+
//MC0_DDR3_RDIMM_CTL_130 : .dword 0x52100003020000a7 #300M+
MC0_DDR3_RDIMM_CTL_130 : .dword 0x6d800003020000a7 #400M+
//MC0_DDR3_RDIMM_CTL_130 : .dword 0x890000040200014e #500M+
//0110110101010110 tras_max(RW) 0000000000000011 tpdex(RW) 0000001000000000 tdll(RW) 0000000000000000 tcpd(RW)
MC0_DDR3_RDIMM_CTL_140 : .dword 0x0000000002000041
@ -386,15 +386,21 @@ MC0_DDR3_RDIMM_CTL_2b0 : .dword 0x0000000000000000
MC0_DDR3_RDIMM_CTL_2c0 : .dword 0x0000000000000000
//hXXXXXXX 00_00 dll_obs_reg_0_8(RW) hXXXXXXX 00_00 dll_obs_reg_0_7(RW)
//11110100000000000011101100100111 phy_ctrl_reg_0_0(RD) 000000_00000000000000000110011101 pad_ctrl_reg_0(RW)
MC0_DDR3_RDIMM_CTL_2d0 : .dword 0xf4003733021c09b5
//MC0_DDR3_RDIMM_CTL_2d0 : .dword 0xf3002837003c09b5
//MC0_DDR3_RDIMM_CTL_2e0 : .dword 0xf3002837f3002837
//MC0_DDR3_RDIMM_CTL_2f0 : .dword 0xf3002837f3002837
//MC0_DDR3_RDIMM_CTL_300 : .dword 0xf3002837f3002837
//MC0_DDR3_RDIMM_CTL_310 : .dword 0xf3002837f3002837
MC0_DDR3_RDIMM_CTL_2d0 : .dword 0xf4003833012c09b5
MC0_DDR3_RDIMM_CTL_2e0 : .dword 0xf4003733f4003733
MC0_DDR3_RDIMM_CTL_2f0 : .dword 0xf4003733f4003733
MC0_DDR3_RDIMM_CTL_300 : .dword 0xf4003733f4003733
MC0_DDR3_RDIMM_CTL_310 : .dword 0xf4003733f4003733
MC0_DDR3_RDIMM_CTL_310 : .dword 0xf4003733f4003833
MC0_DDR3_RDIMM_CTL_320 : .dword 0x26c0000126c00001
MC0_DDR3_RDIMM_CTL_330 : .dword 0x26c0000126c00001
MC0_DDR3_RDIMM_CTL_340 : .dword 0x26c0000126c00001
MC0_DDR3_RDIMM_CTL_350 : .dword 0x26c0000126c00001
//MC0_DDR3_RDIMM_CTL_360 : .dword 0x0000c10026c00001
MC0_DDR3_RDIMM_CTL_360 : .dword 0x0800e10026c00001
//00000000000000001100000000000101 phy_ctrl_reg_2(RW) 00000111110000000000001100000001 phy_ctrl_reg_1_8(RW)
//--------------
@ -517,7 +523,8 @@ MC0_DDR3_RDIMM_CTL_8d0 : .dword 0x0000041104000000
//h00_XXXXXXXX cke_inactive(RW) 000000_000000000000000000 wrlvl_status(RD)
MC0_DDR3_RDIMM_CTL_8e0 : .dword 0x0000000030000000
//h00000000_XXXXXXXX trst_pwron(RW)
MC0_DDR3_RDIMM_CTL_8f0 : .dword 0x0000000048484880
//MC0_DDR3_RDIMM_CTL_8f0 : .dword 0x0000000008080880
MC0_DDR3_RDIMM_CTL_8f0 : .dword 0x0000000028282880
//hXXXXXXX 000_0 XXXXXXXX dll_ctrl_reg_2(RW)
MC0_DDR3_RDIMM_CTL_900 : .dword 0x0000000000000000
//h000000 00_00 X XXXXXXXX rdlvl_error_status(RW)
@ -527,29 +534,31 @@ MC0_DDR3_RDIMM_CTL_920 : .dword 0x0000000000000000
//h00000000000000_XX rdlvl_gate_resp_mask[71:64](RW)
MC0_DDR3_RDIMM_CTL_930 : .dword 0x0000000000000000
//hXXXXXXXX XXXXXXXX rdlvl_resp_mask[63:0](RW)
MC0_DDR3_RDIMM_CTL_940 : .dword 0x0306060000060600
MC0_DDR3_RDIMM_CTL_940 : .dword 0x0302020000060600
//MC0_DDR3_RDIMM_CTL_940 : .dword 0x0306060000060600
//0000_0000 tdfi_rdlvl_en(RW) 00000_000 w2r_samecs_delay(RW) 00000_000 w2r_diffcs_delay(RW) 00000_000 lvl_status(RD) 0000000_0 rdlvl_edge(RW) 0000_0000 cksrx(RW) 0000_0000 cksre(RW) _00000000 rdlvl_resp_mask[71:64](RW)
MC0_DDR3_RDIMM_CTL_950 : .dword 0x0000000000000d00
//hXXXXX 00_00 XXXX mask_int[17:0](RW) hXXXX txpdll(RW) 0000_0000 tdfi_wrlvl_en(RW)
MC0_DDR3_RDIMM_CTL_960 : .dword 0x0705000000000000 //for DDR3 cxk
MC0_DDR3_RDIMM_CTL_960 : .dword 0x0806000000000000 //for DDR3 cxk
//000_00101 rdlat_adj(RW) 0000_0100 wrlat_adj(RW) 0000000_0 swlvl_start(WR) 0000000_0 swlvl_load(WR) 0000000_0 swlvl_exit(WR) 000000_000000000000000000 int_status(RD)
MC0_DDR3_RDIMM_CTL_970 : .dword 0x000000000003e805
//h00000 000_0 XXXX int_ack[16:0](WR) hXXXX dll_rst_delay(RW) hXX dll_rst_adj_dly(RW)
MC0_DDR3_RDIMM_CTL_980 : .dword 0x0001010001000101
//0000000_0 zq_in_progress(RD) 0000000_1 zqcs_rotate(RW) 0000000_0 wrlvl_reg_en(RW) 0000000_0 wrlvl_en(RW) 0000000_1 resync_dll_per_aref_en(RW) 0000000_0 resync_dll(WR) 0000000_0 rdlvl_reg_en(RW) 0000000_0 rdlvl_gate_reg_en(RW)
MC0_DDR3_RDIMM_CTL_990 : .dword 0x0606040606060600
MC0_DDR3_RDIMM_CTL_990 : .dword 0x0202020202020200
//MC0_DDR3_RDIMM_CTL_990 : .dword 0x0606040606060600
//00000_000 w2w_samecs_dly(RW) 00000_001 w2w_diffcs_dly(RW) 00000_010 tbst_int_interval(RW) 00000_010 r2w_samecs_dly(RW) 00000_010 r2w_diffcs_dly(RW) 00000_000 r2r_samecs_dly(RW) 00000_001 r2r_diffcs_dly(RW) 00000_000 axi_aligned_strobe_disable(RW)
MC0_DDR3_RDIMM_CTL_9a0 : .dword 0x0707040402090202
MC0_DDR3_RDIMM_CTL_9a0 : .dword 0x0707040400090002
//00000111 tdfi_wrlvl_load(RW) 00000111 tdfi_rdlvl_load(RW) 000_00011 tckesr(RW) 000_00010 tccd(RW) 000_00000 add_odt_clk_difftype_diffcs(RW) 0000_0110 trp_ab(RW) 0000_0001 add_odt_clk_sametype_diffcs(RW) 0000_0000 add_odt_clk_difftype_samecs(RW)
MC0_DDR3_RDIMM_CTL_9b0 : .dword 0x02000100000a000f
//0000_001000000000 zqinit(RW) 0000_000100000000 zqcl(RW) 000000_0000001010 tdfi_wrlvl_ww(RW) 000000_0000001111 tdfi_rdlvl_rr(RW)
MC0_DDR3_RDIMM_CTL_9c0 : .dword 0x08200c2d0c2d0c2d
MC0_DDR3_RDIMM_CTL_9c0 : .dword 0x08300c2d0c2d0c2d
//0_000101001010010 mr0_data_0(RW) 00_00110000101101 tdfi_phyupd_type3(RW) 00_00110000101101 tdfi_phyupd_type2(RW) 00_00110000101101 tdfi_phyupd_type1(RW)
MC0_DDR3_RDIMM_CTL_9d0 : .dword 0x0044082008200820
MC0_DDR3_RDIMM_CTL_9d0 : .dword 0x0044083008300830
//0_000000000000100 mr1_data_0(RW) 0_000101001010010 mr0_data_3(RW) 0_000101001010010 mr0_data_2(RW) 0_000101001010010 mr0_data_1(RW)
MC0_DDR3_RDIMM_CTL_9e0 : .dword 0x0000004400440044
MC0_DDR3_RDIMM_CTL_9e0 : .dword 0x0008004400440044
//0_000000000000000 mr2_data_0(RW) 0_000000000000100 mr1_data_3(RW) 0_000000000000100 mr1_data_2(RW) 0_000000000000100 mr1_data_1(RW)
MC0_DDR3_RDIMM_CTL_9f0 : .dword 0x0000000000000000
MC0_DDR3_RDIMM_CTL_9f0 : .dword 0x0000000800080008
//0_000000000000000 mr3_data_0(RW) 0_000000000000000 mr2_data_3(RW) 0_000000000000000 mr2_data_2(RW) 0_000000000000000 mr2_data_1(RW)
MC0_DDR3_RDIMM_CTL_a00 : .dword 0x007f000000000000
//0000000011111111 dfi_wrlvl_max_delay(RW) 0_000000000000000 mr3_data_3(RW) 0_000000000000000 mr3_data_2(RW) 0_000000000000000 mr3_data_1(RW)

17
Targets/Bonito3aserver/Bonito/start.S
View File

@ -605,17 +605,6 @@ common:
nop
#endif
#define SHUTDOWN_CORE
#ifdef SHUTDOWN_CORE
li a0, 0xbfe00184
li t1, 0x0001ffff
sw t1, 0x0(a0)
li a0, 0x900010001fe00184
li t1, 0x0000ffff
sw t1, 0x0(a0)
#endif
#if 0 /* Niuxie Tube */
li a0,0xbff00080
@ -3082,6 +3071,12 @@ NODE0_INIT_MEM:
NODE1_INIT_MEM:
//wait the NODE scache enabled
WatchDog_Enable;
dli t0, NODE1_CORE0_BUF0
li a1, NODE_SCACHE_ENABLED
lw a0, SP_OFF(t0)
WatchDog_Close;
dli t0, NODE1_CORE0_BUF0
1:
li a1, NODE_SCACHE_ENABLED

2
Targets/Bonito3aserver/conf/Bonito.3aserver
View File

@ -21,7 +21,7 @@ option TARGETNAME="\"Bonito\""
# Platform options
#
option loongson3A3
#option ARB_LEVEL #use software MC leveling
option ARB_LEVEL #use software MC leveling
option DDR3_DIMM #board use DDR3 memory, use: USE_SB_I2C, else use USE_GPIO_I2C and MULTI_I2C_BUS
option AUTO_DDR_CONFIG #use DIMM SPD auto detect DIMM

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