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Set save_ddrparam as default option. 

Add support for LOONGSON_2H in save_ddrparam.c
master
Chen Xinke 12 years ago
committed by wanghongmei
parent
4ee43b428b
commit
a6b9614641
3 changed files with 525 additions and 523 deletions
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  1. 2
      conf/files
  2. 212
      pmon/cmds/save_ddrparam.c
  3. 2
      pmon/common/main.c

2
conf/files
View File

@ -412,6 +412,6 @@ file pmon/dev/md5.c
#command: cat
file pmon/cmds/cat.c mod_cat
file pmon/cmds/install.c
#file pmon/cmds/save_ddrparam.c
file pmon/cmds/save_ddrparam.c
file pmon/cmds/showwindows.c
file pmon/cmds/interface.c amd_780e

212
pmon/cmds/save_ddrparam.c
View File

@ -46,33 +46,32 @@ int cmd_save_ddrparam __P((int, char *[]));
u64 __raw_readq_sp(u64 q)
{
u64 ret;
u64 ret;
asm volatile(
".set mips3;\r\n"
"move $8,%1;\r\n"
"ld %0,0($8);\r\n"
:"=r"(ret)
:"r" (q)
:"$8");
asm volatile(
".set mips3;\r\n"
"move $8,%1;\r\n"
"ld %0,0($8);\r\n"
:"=r"(ret)
:"r" (q)
:"$8");
return ret;
}
u64 __raw_writeq_sp(u64 addr, u64 val)
{
u64 ret;
asm volatile(
".set mips3;\r\n"
"move $8,%1;\r\n"
"move $9,%2;\r\n"
"sd $9,0($8);\r\n"
"ld %0,0($8);\r\n"
:"=r"(ret)
:"r" (addr), "r" (val)
:"$8", "$9");
u64 ret;
asm volatile(
".set mips3;\r\n"
"move $8,%1;\r\n"
"move $9,%2;\r\n"
"sd $9,0($8);\r\n"
"ld %0,0($8);\r\n"
:"=r"(ret)
:"r" (addr), "r" (val)
:"$8", "$9");
return ret;
}
@ -84,12 +83,16 @@ u64 __raw_writeq_sp(u64 addr, u64 val)
extern char _start;
extern char ddr2_leveled_mark;
#ifndef LS3B
#ifdef LOONGSON_2H
extern char ddr2_reg_data_leveled;
#endif
#ifdef loongson3A3
extern char ddr2_reg_data_mc0_leveled, ddr2_reg_data_mc1_leveled;
#ifdef MULTI_CHIP
extern char n1_ddr2_reg_data_mc0_leveled, n1_ddr2_reg_data_mc1_leveled;
#endif
#else
#endif
#ifdef LS3B
extern char ddr2_reg_data_leveled;
#ifdef MULTI_CHIP
extern char n1_ddr2_reg_data_leveled;
@ -112,56 +115,87 @@ extern void dump_l2xbar(int node);
#else
#define DDR_PARAM_NUM 152
#endif
#define MC_CONFIG_ADDR 0x900000000ff00000ull
#ifdef LOONGSON_2H
#define CPU_CONFIG_ADDR 0x900000001fd00200ull
#else
#define CPU_CONFIG_ADDR 0x900000001fe00180ull
#define CPU_L2XBAR_CONFIG_ADDR 0x900000003ff00000ull
#define MC_CONFIG_ADDR 0x900000000ff00000ull
#endif
static void disable_ddrconfig(u64 node_id_shift44)
void enable_ddrconfig(u64 node_id_shift44)
{
unsigned long long val;
/* Disable DDR access configure register */
#ifndef LS3B
#ifdef loongson3A3
val = ld(CPU_CONFIG_ADDR | node_id_shift44);
val |= 0x100;
val &=0xfffffffffffffeffull;
sd(CPU_CONFIG_ADDR | node_id_shift44, val);
#ifdef DEBUG
printf("Disable sys config reg:0x1fe00180 = %016llx\n", ld(CPU_CONFIG_ADDR | node_id_shift44));
printf("Enable sys config reg = %016llx", ld(CPU_CONFIG_ADDR | node_id_shift44));
#endif
#else
return;
#endif
#ifdef LS3B
val = ld(CPU_CONFIG_ADDR | node_id_shift44 & 0xffffefffffffffffull);
val |= 0x210;
val &=0xfffffffffffffdefull;
sd(CPU_CONFIG_ADDR | node_id_shift44 & 0xffffefffffffffffull, val);
#ifdef DEBUG
printf("Disable sys config reg:0x1fe00180 = %016llx\n", ld(CPU_CONFIG_ADDR | node_id_shift44 & 0xffffefffffffffffull));
printf("Enable sys config reg = %016llx", ld(CPU_CONFIG_ADDR | node_id_shift44 & 0xffffefffffffffffull));
#endif
return;
#endif
#ifdef LOONGSON_2H
val = ld(CPU_CONFIG_ADDR | node_id_shift44);
val &=0xffffffffffffdfffull;
sd(CPU_CONFIG_ADDR | node_id_shift44, val);
#ifdef DEBUG
printf("Enable sys config reg = %016llx", ld(CPU_CONFIG_ADDR | node_id_shift44 & 0xffffefffffffffffull));
#endif
return;
#endif
}
static void enable_ddrconfig(u64 node_id_shift44)
void disable_ddrconfig(u64 node_id_shift44)
{
unsigned long long val;
#ifndef LS3B
/* Disable DDR access configure register */
#ifdef loongson3A3
val = ld(CPU_CONFIG_ADDR | node_id_shift44);
val &=0xfffffffffffffeffull;
val |= 0x100;
sd(CPU_CONFIG_ADDR | node_id_shift44, val);
#ifdef DEBUG
printf("Enable sys config reg:0x1fe00180 = %016llx", ld(CPU_CONFIG_ADDR | node_id_shift44));
printf("Disable sys config reg = %016llx\n", ld(CPU_CONFIG_ADDR | node_id_shift44));
#endif
#else
return;
#endif
#ifdef LS3B
val = ld(CPU_CONFIG_ADDR | node_id_shift44 & 0xffffefffffffffffull);
val &=0xfffffffffffffdefull;
val |= 0x210;
sd(CPU_CONFIG_ADDR | node_id_shift44 & 0xffffefffffffffffull, val);
#ifdef DEBUG
printf("Enable sys config reg:0x1fe00180 = %016llx", ld(CPU_CONFIG_ADDR | node_id_shift44 & 0xffffefffffffffffull));
printf("Disable sys config reg = %016llx\n", ld(CPU_CONFIG_ADDR | node_id_shift44 & 0xffffefffffffffffull));
#endif
return;
#endif
#ifdef LOONGSON_2H
val = ld(CPU_CONFIG_ADDR | node_id_shift44);
val |= 0x2000ull;
sd(CPU_CONFIG_ADDR | node_id_shift44, val);
#ifdef DEBUG
printf("Disable sys config reg = %016llx\n", ld(CPU_CONFIG_ADDR | node_id_shift44));
#endif
return;
#endif
}
#ifdef loongson3A3
void enable_ddrcfgwindow(u64 node_id_shift44, int mc_selector, unsigned long long * buf)
//use window 0 which is used to route 0x1fc00000 addr space, not used here.
{
@ -187,10 +221,8 @@ void enable_ddrcfgwindow(u64 node_id_shift44, int mc_selector, unsigned long lon
printf("Now dump L2X bar windows\n");
dump_l2xbar(1);
#endif
}
//restore origin configure
void disable_ddrcfgwidow(u64 node_id_shift44, int mc_selector, unsigned long long * buf)
{
@ -207,6 +239,7 @@ void disable_ddrcfgwidow(u64 node_id_shift44, int mc_selector, unsigned long lon
printf("new :: 0x00: %016llx 0x40: %016llx 0x80: %016llx\n", ld((CPU_L2XBAR_CONFIG_ADDR | node_id_shift44)), ld((CPU_L2XBAR_CONFIG_ADDR | node_id_shift44) + 0x40), ld((CPU_L2XBAR_CONFIG_ADDR | node_id_shift44) + 0x80));
#endif
}
#endif
#define MC0 0x0
#define MC1 0x1
@ -217,19 +250,14 @@ int read_ddr_param(u64 node_id_shift44, int mc_selector, unsigned long long * b
unsigned long long * val = base;
unsigned long long buf[3];
//do_cmd("showwindows");
//dump_l2xbar(1);
#ifndef LS3B
#ifdef loongson3A3
// step 1. Change The Primest window for MC0 or MC1 register space
enable_ddrcfgwindow(node_id_shift44, mc_selector, buf);
#endif
//do_cmd("showwindows");
//dump_l2xbar(1);
// step 2. Enabel access to MC0 or MC1 register space
enable_ddrconfig(node_id_shift44);
// step 3. Read out ddr config register to buffer
printf("\nNow Read out DDR parameter from DDR MC%d controler after DDR training\n", mc_selector);
for ( i = DDR_PARAM_NUM - 1; i >= 0; i--) // NOTICE HERE: it means system has DDR_PARAM_NUM double words
@ -246,7 +274,7 @@ int read_ddr_param(u64 node_id_shift44, int mc_selector, unsigned long long * b
// step 4. Disabel access to MC0 or MC1 register space
disable_ddrconfig(node_id_shift44);
#ifndef LS3B
#ifdef loongson3A3
// step 5. Restore The Primest window for accessing system memory
disable_ddrcfgwidow(node_id_shift44, mc_selector, buf);
#endif
@ -255,46 +283,33 @@ int read_ddr_param(u64 node_id_shift44, int mc_selector, unsigned long long * b
return 0;
}
#ifndef LS3B
#ifdef loongson3A3
void save_ddrparam(u64 node_id_shift44, int mc0_param_store_addr, int mc1_param_store_addr)
{
unsigned long long ddr_param_buf[DDR_PARAM_NUM + 1];
unsigned long long tmp1, tmp2, tmp3, tmp4;
unsigned long long ddr_param_buf[DDR_PARAM_NUM + 1];
unsigned long long tmp1, tmp2, tmp3, tmp4;
#ifdef DEBUG
int i;
unsigned long long tmp;
int i;
unsigned long long tmp;
#endif
#ifdef DEBUG
printf("\nnode_id_shift44=0x%016llx\n", node_id_shift44);
#endif
/********************************************************/
/************************/ // End of flash
/* DDRPTOVF */ // End - 8 (byte) (1M-8)
/* -------------------- */ //
/* */ //
/* ....... */
/* ....... */
/* ....... */ // $ddr3_data
/* ....... */
/* */
/************************/ // Base of flash: offset 0x00
/********************************************************/
// step 1. Read out DDR controler register values and save them in buffers
//according to low 256M route manner to decide NODE MC enable state. not ok now!
//according to high memory route manner to decide NODE MC enable state.
printf("\nnode_id_shift44=0x%016llx\n", node_id_shift44);
#endif
// step 1. Read out DDR controler register values and save them in buffers
//according to L2 window route manner to decide NODE MC enable state.
//according to high memory route manner to decide NODE MC enable state.
tmp1 = ld((CPU_L2XBAR_CONFIG_ADDR | node_id_shift44) + 0xa0);
tmp2 = ld((CPU_L2XBAR_CONFIG_ADDR | node_id_shift44) + 0xa8);
tmp3 = ld((CPU_L2XBAR_CONFIG_ADDR | node_id_shift44) + 0xb0);
tmp4 = ld((CPU_L2XBAR_CONFIG_ADDR | node_id_shift44) + 0xb8);
#ifdef DEBUG
printf("tmp1=0x%016llx\n", tmp1);
printf("tmp2=0x%016llx\n", tmp2);
printf("tmp1=0x%016llx\n", tmp1);
printf("tmp2=0x%016llx\n", tmp2);
#endif
//note, only check the last 4-bit is not ok!
tmp1 &= 0xff;
@ -311,7 +326,7 @@ void save_ddrparam(u64 node_id_shift44, int mc0_param_store_addr, int mc1_param_
tgt_flashprogram((int *)(0xbfc00000+(mc0_param_store_addr -(int)&_start)), DDR_PARAM_NUM*8, ddr_param_buf,TRUE);
#ifdef DEBUG
for(i = 0; i< DDR_PARAM_NUM; i++)
for(i = 0; i< DDR_PARAM_NUM; i++)
{
tmp = ld(0x900000001fc00000 + mc0_param_store_addr - (int)&_start + i * 8);
if(ddr_param_buf[i] != tmp)
@ -333,7 +348,7 @@ void save_ddrparam(u64 node_id_shift44, int mc0_param_store_addr, int mc1_param_
tgt_flashprogram((int *)(0xbfc00000+(mc1_param_store_addr -(int)&_start)), DDR_PARAM_NUM*8, ddr_param_buf,TRUE);
#ifdef DEBUG
for(i = 0; i< DDR_PARAM_NUM; i++)
for(i = 0; i< DDR_PARAM_NUM; i++)
{
tmp = ld(0x900000001fc00000 + mc1_param_store_addr - (int)&_start + i * 8);
if(ddr_param_buf[i] != tmp)
@ -345,7 +360,6 @@ void save_ddrparam(u64 node_id_shift44, int mc0_param_store_addr, int mc1_param_
}
#endif
}
}
int save_board_ddrparam(void)
@ -366,44 +380,31 @@ int save_board_ddrparam(void)
return(1);
}
#else
//for LS3B/LOONGSON_2H
void save_ddrparam(u64 node_id_shift44, int mc0_param_store_addr)
{
unsigned long long ddr_param_buf[DDR_PARAM_NUM + 1];
unsigned long long ddr_param_buf[DDR_PARAM_NUM + 1];
#ifdef DEBUG
int i;
unsigned long long tmp;
int i;
unsigned long long tmp;
#endif
#ifdef DEBUG
printf("\nnode_id_shift44=0x%016llx\n", node_id_shift44);
#endif
/********************************************************/
/************************/ // End of flash
/* DDRPTOVF */ // End - 8 (byte) (1M-8)
/* -------------------- */ //
/* */ //
/* ....... */
/* ....... */
/* ....... */ // $ddr3_data
/* ....... */
/* */
/************************/ // Base of flash: offset 0x00
/********************************************************/
// step 1. Read out DDR controler register values and save them in buffers
// step 1.1 Read out DDR controler register from MC0 and save them in buffer0
read_ddr_param(node_id_shift44, MC0, ddr_param_buf);
//ddr_param_buf[DDR_PARAM_NUM] = 0x0;
// step 1.2 Program buffers of MC0 register into FLASH
tgt_flashprogram((int *)(0xbfc00000+(mc0_param_store_addr -(int)&_start)), DDR_PARAM_NUM*8, ddr_param_buf,TRUE);
printf("\nnode_id_shift44=0x%016llx\n", node_id_shift44);
#endif
// step 1.1 Read out DDR controler register from MC0 and save them in buffer0
read_ddr_param(node_id_shift44, MC0, ddr_param_buf);
//ddr_param_buf[DDR_PARAM_NUM] = 0x0;
// step 1.2 Program buffers of MC0 register into FLASH
tgt_flashprogram((int *)(0xbfc00000+(mc0_param_store_addr -(int)&_start)), DDR_PARAM_NUM*8, ddr_param_buf,TRUE);
#ifdef DEBUG
for(i = 0; i< DDR_PARAM_NUM; i++)
for(i = 0; i< DDR_PARAM_NUM; i++)
{
tmp = ld(0x900000001fc00000 + mc0_param_store_addr - (int)&_start + i * 8);
if(ddr_param_buf[i] != tmp)
@ -414,7 +415,6 @@ void save_ddrparam(u64 node_id_shift44, int mc0_param_store_addr)
printf("\nSame:i=%d, val=%016llx", i, tmp);
}
#endif
}
int save_board_ddrparam(void)
@ -425,6 +425,7 @@ int save_board_ddrparam(void)
{
node_id = 0;
save_ddrparam(node_id << 44, (int)&ddr2_reg_data_leveled);
#ifdef LS3B
#ifdef MULTI_CHIP
node_id = 1;
save_ddrparam(node_id << 44, (int)&n1_ddr2_reg_data_leveled);
@ -434,6 +435,7 @@ int save_board_ddrparam(void)
save_ddrparam(node_id << 44, (int)&n2_ddr2_reg_data_leveled);
node_id = 3;
save_ddrparam(node_id << 44, (int)&n3_ddr2_reg_data_leveled);
#endif
#endif
flag = 0x1;
tgt_flashprogram((int *)(0xbfc00000 + ((int)&ddr2_leveled_mark - (int)&_start)), 8, &flag, TRUE);

2
pmon/common/main.c
View File

@ -425,7 +425,7 @@ if(!run)
{
run=1;
#ifdef ARB_LEVEL
//save_board_ddrparam();
save_board_ddrparam();
#endif
#ifdef AUTOLOAD

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