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Code fix. 

1. Disable LPC CTRL/MEM/MMIO-BAR and set them to fix address.
CTRL: 0x10002000~0x10002fff;
MEM:  0x12000000~0x13ffffff;
IO:   0x18000000~0x1801ffff;
As the kernel need also be modified to reserve the low 128KB IO space and skip LPC BAR, so we disable board LPC now.
The GPU emu code is also modified.
2. Fix GPU/DC class code.
3. Disable 3A HT dw_write to support mask write and change the PIX pll default setting.
4. Fix WatchDog control defination.
5. Disable HT freq soft configure to fix possible HT link fail. And add check of HT pll lock.

Change-Id: I1ac3eaacc1fcda52b8ae1a0dbbdc0306833da7dc
master
Chen Xinke 7 years ago
committed by zhangbaoqi
parent
ed62cd95d7
commit
ab9c1a4be0
10 changed files with 151 additions and 27 deletions
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  1. 14
      Targets/Bonito3a3000_7a/Bonito/loongson3_def.h
  2. 14
      Targets/Bonito3a3000_7a/Bonito/ls7a_config.h
  3. 14
      Targets/Bonito3a3000_7a/Bonito/start.S
  4. 7
      Targets/Bonito3a3000_7a/pci/ls7a_pci.c
  5. 2
      Targets/Bonito3a3000_7a/pci/pci_machdep.c
  6. 8
      pmon/arch/mips/ls7a/ls3a7a_ht_init.S
  7. 53
      pmon/arch/mips/ls7a/ls3a7a_setup_ht_link.S
  8. 3
      pmon/arch/mips/ls7a/ls7a_define.h
  9. 52
      pmon/arch/mips/ls7a/ls7a_init.S
  10. 11
      x86emu/int10/generic.c

14
Targets/Bonito3a3000_7a/Bonito/loongson3_def.h
View File

@ -80,7 +80,19 @@ GPIO_CLEAR_OUTPUT(0x1<<13); \
/* WatchDog Enable for chip MAX6369*/
#define WatchDog_Enable \
GPIO_CLEAR_OUTPUT(0x2038);
GPIO_CLEAR_OUTPUT(0x1<<13); \
GPIO_SET_OUTPUT(0x1<<14); \
GPIO_SET_OUTPUT(0x1<<5); \
GPIO_CLEAR_OUTPUT(0x1<<4); \
GPIO_SET_OUTPUT(0x1<<3); \
GPIO_CLEAR_OUTPUT(0x1<<14); \
li v1,0x100;\
78:; \
subu v1,1; \
bnez v1,78b; \
nop; \
GPIO_SET_OUTPUT(0x1<<13);
#define w83627write(x,y,z) \
li v0, 0xb800002e; \

14
Targets/Bonito3a3000_7a/Bonito/ls7a_config.h
View File

@ -4,6 +4,8 @@
//#define DEBUG_HT1_PARAM
#endif
#define CHECK_HT_PLL_MODE
#define CHECK_HT_PLL_LOCK
#define CHECK_7A_HT_PLL_LOCK
#ifdef MULTI_CHIP
#define LS7A_2WAY_CONNECT
@ -11,7 +13,7 @@
#define HT1_RECONNECT 1
//HT GEN1.0/3.0 cfg
#define HT1_GEN_CFG 3
#define HT1_GEN_CFG 1
//HT1 width cfg
#if defined(LS7A_2WAY_CONNECT) || (HT1_GEN_CFG == 1)
#define HT1_WIDTH_CFG HT_WIDTH_CTRL_8BIT //only support 8 bit
@ -21,13 +23,13 @@
//HT1 freq cfg
#if (HT1_GEN_CFG == 3)
#define HT1_HARD_FREQ_CFG HT_GEN3_FREQ_CTRL_1600M
#define LS7A_HT1_SOFT_FREQ_CFG (LS7A_HT_PLL_1600M | (0x1 << 1))
#define LS3A_HT1_SOFT_FREQ_CFG (LS3A_HT_PLL_1600M | (0x1 << 1))
#define LS7A_HT1_SOFT_FREQ_CFG (LS7A_HT_PLL_1600M | (0x0 << 1))
#define LS3A_HT1_SOFT_FREQ_CFG (LS3A_HT_PLL_1600M | (0x0 << 1))
#else
#define HT1_HARD_FREQ_CFG HT_GEN1_FREQ_CTRL_800M
//in HT GEN1 mode, define PLL freq to request freq x 2, for example, if you want to use HT1 800M, define HT_PLL_1600M
#define LS7A_HT1_SOFT_FREQ_CFG (LS7A_HT_PLL_1600M | (0x1 << 1))
#define LS3A_HT1_SOFT_FREQ_CFG (LS3A_HT_PLL_1600M | (0x1 << 1))
#define LS7A_HT1_SOFT_FREQ_CFG (LS7A_HT_PLL_1600M | (0x0 << 1))
#define LS3A_HT1_SOFT_FREQ_CFG (LS3A_HT_PLL_1600M | (0x0 << 1))
#endif
#define LS7A_GRAPHICS_DISABLE 0
@ -50,7 +52,7 @@
#define LS7A_SATA2_DISABLE 0
#define LS7A_USB0_DISABLE 0
#define LS7A_USB1_DISABLE 0
#define LS7A_LPC_DISABLE 0
#define LS7A_LPC_DISABLE 1
//#define USE_PCIE_PAD_REFCLK
//#define USE_SATA_PAD_REFCLK

14
Targets/Bonito3a3000_7a/Bonito/start.S
View File

@ -440,6 +440,9 @@ bsp_start:
dli t0, CONFBUS_HEADER_ADDR
li t1, CONFBUS_BASE_ADDR
sw t1, 0x10(t0)
lw t2, 0x4(t0)
ori t2, t2, 0x2
sw t2, 0x4(t0)
TTYDBG("set LS7A MISC and confbus base address done.\r\n")
//set PWM output 1
@ -459,9 +462,6 @@ bsp_start:
sw a0, 0x308(t0)
sw a1, 0x30c(t0)
bal beep_off
nop
//setup LS3A - 7A HT link start...
//check 3A clksel setting
li t0, 0xbfe00190
@ -598,6 +598,8 @@ bsp_start:
nop
#endif
//WatchDog_Enable
move a1, t2
bal reset_ht_link
nop
@ -617,12 +619,18 @@ bsp_start:
TTYDBG("LS3A-7A linkup.")
//setup LS3A - 7A HT link done.
bal beep_off
nop
//WatchDog_Close
//#define TEST_REBOOT
#ifdef TEST_REBOOT
bal tgt_testchar
nop
bnez v0, no_reboot
nop
TTYDBG("\r\nenable watchdog.")
WatchDog_Enable

7
Targets/Bonito3a3000_7a/pci/ls7a_pci.c
View File

@ -70,10 +70,9 @@ u32 _pci_conf_readn(device_t tag, int reg, int width)
if(bus == 0 && (device >=9 && device <= 20) && reg == 0x8){
return 0x06040001;
}
//workaround LPC BAR4
if(bus == 0 && device == 23 && function == 0 && reg == 0x20){
val_raw = pci_read_type0_config32(device, function, reg);
return val_raw & ~0xf | 0x4;
//workaround LPC BAR4/5
if(bus == 0 && device == 23 && function == 0 && (reg >= 0x10 && reg <= 0x24)){
return 0;
}
if (bus == 0) {

2
Targets/Bonito3a3000_7a/pci/pci_machdep.c
View File

@ -109,7 +109,7 @@ _pci_hwinit(initialise, iot, memt)
#ifdef LS3_HT /* whd */
pb->minpcimemaddr = BONITO_PCILO0_BASE; //7a:0x4000 0000 2k:0x1000 0000
pb->nextpcimemaddr = BONITO_PCILO0_BASE + BONITO_PCILO_SIZE; //7a:0x4000 0000 2k:0x0800 0000
pb->minpciioaddr = PCI_IO_SPACE_BASE + 0x0004000; //7a:0x0+0x4000 2k:0x1800 0000
pb->minpciioaddr = PCI_IO_SPACE_BASE + 0x0020000; //7a:0x0+0x4000 2k:0x1800 0000
pb->nextpciioaddr = PCI_IO_SPACE_BASE + BONITO_PCIIO_SIZE; //7a:0x0+0x02000000 2k:0x1800 ffff
pb->pci_mem_base = BONITO_PCILO_BASE_VA; //7a:0xc000 0000 2k:0x1000 0000
pb->pci_io_base = BONITO_PCIIO_BASE_VA; //7a:0xb800 0000 2k:0x1810 0000

8
pmon/arch/mips/ls7a/ls3a7a_ht_init.S
View File

@ -122,6 +122,12 @@ ls3a7a_ht_init:
sw a0, (LS3A_HT_RX_UNCACHE_WIN2_OFFSET+0)(t0)
#endif
#endif
//set csr_dw_write to 1'b0 to transfer write mask infomation when write data less than 32Byte
TTYDBG("Disable 3A HT dw_write.\r\n")
lw a0, 0x50(t0)
li a1, 0xff7fffff
and a0, a0,a1
sw a0, 0x50(t0)
//2. 7A side HT configure begin
//!!!note: use t1 store 7A side HT controller address as global variable
@ -149,7 +155,7 @@ ls3a7a_ht_init:
#endif
//set csr_dw_write to 1'b0 to transfer write mask infomation when write data less than 32Byte
TTYDBG("Enable 7A HT dw_write.\r\n")
TTYDBG("Disable 7A HT dw_write.\r\n")
lw a0, 0x1c0(t1)
li a1, 0xfbffffff
and a0, a0,a1

53
pmon/arch/mips/ls7a/ls3a7a_setup_ht_link.S
View File

@ -81,6 +81,31 @@ config_ht_link:
bne t5, t6, 1b
nop
#endif
#ifdef CHECK_HT_PLL_LOCK
//check HT PLL lock
move t5, $0
lw a0, 0x178(t0)
srl a0, a0, 3
and a0, a0, 0x1
bnez a0, 2f
nop
PRINTSTR("\r\nError: After reconfigure, 3A HT PLL not locked!!!")
add t5, t5, 1
2:
#ifdef CHECK_7A_HT_PLL_LOCK
lw a0, 0x1F4(t1)
srl a0, a0, 3
and a0, a0, 0x1
bnez a0, 2f
nop
PRINTSTR("\r\nError: After reconfigure, 7A HT PLL not locked!!!")
add t5, t5, 1
2:
#endif
bnez t5, 2b
nop
TTYDBG("\r\nPLL check success.")
#endif
//wait until HT link up
TTYDBG("\r\nWait HT bus up.")
@ -108,7 +133,7 @@ config_ht_link:
nop
TTYDBG("\r\n")
#if 1 //HT1_RECONNECT
#if HT1_RECONNECT
and a0, t2, 0x1
beqz a0, 8f
nop
@ -347,7 +372,6 @@ config_ht_link:
nop
2:
#endif
8:
#endif
@ -593,6 +617,31 @@ reset_ht_link:
nop
#endif
#endif
#ifdef CHECK_HT_PLL_LOCK
//check HT PLL lock
move t5, $0
lw a0, 0x178(t0)
srl a0, a0, 3
and a0, a0, 0x1
bnez a0, 2f
nop
PRINTSTR("\r\nError: After reconfigure, 3A HT PLL not locked!!!")
add t5, t5, 1
2:
#ifdef CHECK_7A_HT_PLL_LOCK
lw a0, 0x1F4(t1)
srl a0, a0, 3
and a0, a0, 0x1
bnez a0, 2f
nop
PRINTSTR("\r\nError: After reconfigure, 7A HT PLL not locked!!!")
add t5, t5, 1
2:
#endif
bnez t5, 2b
nop
TTYDBG("\r\nAfter reconnect, PLL check success.")
#endif
#if 1//Check if CRC error bit set and reset it
TTYDBG("Checking Node 0 HT1 CRC error.")

3
pmon/arch/mips/ls7a/ls7a_define.h
View File

@ -2,6 +2,7 @@
#define LS7A_CONFIG_
#define LS7A_UC_ACC
#define OVRD_SATA_PHY
#define LS7A_PLL_DIV_REFC_OFFSET 0
#define LS7A_PLL_LOCK_OFFSET 7
@ -31,8 +32,10 @@
#define INT_BASE_ADDR 0x10000000
#define HPET_BASE_ADDR 0x10001000
#define LPC_CNTL_BASE_ADDR 0x10002000
#define CONFBUS_BASE_ADDR 0x10010000
#define MISC_BASE_ADDR 0x10080000
#define LPC_MEM_BASE_ADDR 0x12000000
#define LS7A_CONFBUS_BASE_ADDR (HT1_MEM_BASE_ADDR | CONFBUS_BASE_ADDR)
#define LS7A_MISC_BASE_ADDR (HT1_MEM_BASE_ADDR | MISC_BASE_ADDR)

52
pmon/arch/mips/ls7a/ls7a_init.S
View File

@ -135,9 +135,10 @@
nop
1:
//PIX0, default 38.2MHz for x800x600
daddu a0, t0, CONF_PLL3_OFFSET
li a2, 0x5
li a1, LS7A_PLL_VALUE(57, 30, 30, 30)
li a2, 0x4
li a1, LS7A_PLL_VALUE(104, 68, 68, 68)
bal ls7a_config_one_pll
nop
beqz v0, 1f
@ -148,9 +149,10 @@
nop
1:
//PIX1, default 64.1MHz for x1024x768
daddu a0, t0, CONF_PLL4_OFFSET
li a2, 0x5
li a1, LS7A_PLL_VALUE(57, 30, 30, 30)
li a2, 0x4
li a1, LS7A_PLL_VALUE(100, 39, 39, 39)
bal ls7a_config_one_pll
nop
beqz v0, 1f
@ -204,10 +206,27 @@
sb a2, 0x32ce(t0)
sb a2, 0x330e(t0)
sb a2, 0x334e(t0)
//fix GPU/DC header
li a2, 0x04000000
sw a2, 0x31c8(t0)
li a2, 0x03800000
sw a2, 0x3208(t0)
//fix LPC class code
//fix LPC header
li a2, 0x06010000
sw a2, 0x3448(t0)
li a2, 0xfc000000
sw a2, 0x3460(t0)
li a2, 0xfd
sw a2, 0x3464(t0)
li a2, LPC_CNTL_BASE_ADDR
sw a2, 0x3450(t0)
li a2, LPC_MEM_BASE_ADDR
sw a2, 0x3458(t0)
lw a2, 0x3444(t0)
or a2, a2, 0x3
sw a2, 0x3444(t0)
//disable pci scan of MISC and confbus
lw a0, 0x3800(t0)
@ -242,12 +261,11 @@
sw $0, 0x383c(t0)
//special take care of GPU-BAR3(64)
lw a0, 0x3844(t0)
or a0, 0xff
or a0, 0xfc
sw a0, 0x3844(t0)
//special take care of LPC
lw a2, 0x388c(t0)
or a2, a2, 0xff
sw a2, 0x388c(t0)
li a0, 0x0
sw a0, 0x3888(t0)
//disable write to part of header ---- end
//change INT and HPET fix address
@ -773,6 +791,16 @@
//use t0 as global variable
dli t0, LS7A_CONFBUS_BASE_ADDR
//configure sata phy parameter
li t1, 0x30c31cf9
sw t1, 0x744(t0)
sw t1, 0x754(t0)
sw t1, 0x764(t0)
li t1, 0xf3000403
sw t1, 0x740(t0)
sw t1, 0x750(t0)
sw t1, 0x760(t0)
#if (!LS7A_SATA0_DISABLE)
#ifndef USE_SATA_PAD_REFCLK
//power down phy
@ -835,11 +863,13 @@
or t1, t1, t2
sw t1, (CONF_SB_OFFSET+4)(t0)
#ifdef OVRD_SATA_PHY
//configure phy
daddu a0, t0, 0x748
li a1, 0x403f1002
bal ls7a_phy_cfg_write
nop
#endif
TTYDBG("SATA0 enabled\r\n")
#else
//powerdown phy
@ -919,11 +949,13 @@
or t1, t1, t2
sw t1, (CONF_SB_OFFSET+4)(t0)
#ifdef OVRD_SATA_PHY
//configure phy
daddu a0, t0, 0x758
li a1, 0x403f1002
bal ls7a_phy_cfg_write
nop
#endif
TTYDBG("SATA1 enabled\r\n")
#else
//powerdown phy
@ -1003,11 +1035,13 @@
or t1, t1, t2
sw t1, (CONF_SB_OFFSET+4)(t0)
#ifdef OVRD_SATA_PHY
//configure phy
daddu a0, t0, 0x768
li a1, 0x403f1002
bal ls7a_phy_cfg_write
nop
#endif
TTYDBG("SATA2 enabled\r\n")
#else
//powerdown phy

11
x86emu/int10/generic.c
View File

@ -294,10 +294,17 @@ int vga_bios_init(void)
base = INTPriv(pInt)->base = malloc(0x100000);
#if defined(LS7A) || defined(LOONGSON_2K)
unsigned int b_io_lo_val, b_io_hi_val, d_val;
unsigned int lpc_old_cmd;
if(pcie_dev != NULL) {
unsigned int vga_tmp = _pci_make_tag(pcie_dev->parent->pa.pa_bus, pcie_dev->parent->pa.pa_device, pcie_dev->parent->pa.pa_function);//get the brige data
//printf("bridge tag: 0x%x\n", vga_tmp);
#if defined(LS7A)
//disable LPC IO space
unsigned int lpc_tag = _pci_make_tag(0, 23, 0);//get the brige data
lpc_old_cmd = _pci_conf_read(lpc_tag, 0x4);
_pci_conf_write(lpc_tag, 0x4, lpc_old_cmd & ~0x1);
#endif
//set io limit and io base to zero.
//store old value first
b_io_lo_val = _pci_conf_read(vga_tmp, 0x1c);
@ -713,6 +720,10 @@ int vga_bios_init(void)
#if defined(LS7A) || defined(LOONGSON_2K)
if(pcie_dev != NULL) {
#if defined(LS7A)
unsigned int lpc_tag = _pci_make_tag(0, 23, 0);//get the brige data
_pci_conf_write(lpc_tag, 0x4, lpc_old_cmd);
#endif
unsigned int vga_tmp = _pci_make_tag(pcie_dev->parent->pa.pa_bus, pcie_dev->parent->pa.pa_device, pcie_dev->parent->pa.pa_function);//get the brige data
_pci_conf_write(vga_tmp, 0x1c, b_io_lo_val);
_pci_conf_write(vga_tmp, 0x30, b_io_hi_val);

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