ls2k ddr 32bit.

Change-Id: I07b6cb6480a2d8f3bac195656a5c6b343ec16b12
Signed-off-by: QiaoChong <qiaochong@loongson.cn>

Targets/LS2K/ls2k/ddr_dir/ddr_leveling_define.h

@@ -1,5 +1,18 @@
 #define GET_NUMBER_OF_SLICES	\
     li      t0, 0x8;\
+    lb	    a0, 0x1f2(t8);\
+    bne	    a0, 0x3, 1f;\
+    nop;\
+    li      t0, 0x2;\
+    b       933f;\
+    nop;\
+1:;\
+    bne     a0, 0x5, 934f;\
+    nop;\
+    li      t0, 0x4;\
+    b       933f;\
+    nop;\
+934:;\
     dli     t1, 0x250;\
     or      t1, t1, t8;\
     lb      a0, 0x2(t1);\

Targets/LS2K/ls2k/ddr_dir/loongson3C_ddr3_leveling.S

@@ -17,7 +17,7 @@
 /* in hexserial: ra, a0, a1, a2, a3 will be changed*/
 
 #include "ddr_leveling_define.h"
-#define	PREAMBLE_CHECK_DEBUG
+//#define	PREAMBLE_CHECK_DEBUG
 //#define	PRINT_PREAMBLE_CHECK
 //#define PRINT_DDR_LEVELING
 //#define SIGNAL_DEPICT_DEBUG
@@ -2337,7 +2337,8 @@ dll_gate_sub20:
 gate_sub_end:
 #endif
 
-#ifdef NO_EDGE_CHECK
+#define NO_EDGE_CHECK
+#ifdef NO_EDGE_CHECK	
 #else
 #if 1
 /* unknown reason to reset init_start */

Targets/LS2K/ls2k/ddr_dir/lsmc_config_param.S

@@ -804,42 +804,42 @@ x8:
 1:
 #endif
 #endif
-    //set data bus width
-    ld      a2, DATA_WIDTH_32_ADDR(t8)
-    dli     a1, 0x1
-    dsll    a1, a1, DATA_WIDTH_32_OFFSET
-    not     a1, a1
-    and     a2, a2, a1
-    GET_DIMM_WIDTH
-    dsll    a1, a1, DATA_WIDTH_32_OFFSET
-    or      a2, a2, a1
-    sd      a2, DATA_WIDTH_32_ADDR(t8)
-#ifndef MC_MULTI_CHANNEL
-    //rewrite multi_channel mode
-    ld      a2, MC_MULTI_CHANNEL_ADDR(t8)
-    dli     a1, 0x1
-    dsll    a1, a1, MC_MULTI_CHANNEL_OFFSET
-    not     a1, a1
-    and     a2, a2, a1
-    GET_DIMM_WIDTH
-    dsll    a1, a1, MC_MULTI_CHANNEL_OFFSET
-    or      a2, a2, a1
-    sd      a2, MC_MULTI_CHANNEL_ADDR(t8)
-#endif
-#ifndef MC_MULTI_CHANNEL
-    //rewrite pm_addr_win(data width)
-    ld      a2, ADDR_WIN_DATA_WIDTH_ADDR(t8)
-    dli     a1, 0x3
-    dsll    a1, a1, ADDR_WIN_DATA_WIDTH_OFFSET
-    not     a1, a1
-    and     a2, a2, a1
-    dli     v0, 0x3
-    GET_DIMM_WIDTH
-    xor     a1, v0, a1
-    dsll    a1, a1, ADDR_WIN_DATA_WIDTH_OFFSET
-    or      a2, a2, a1
-    sd      a2, ADDR_WIN_DATA_WIDTH_ADDR(t8)
-#endif
+//    //set data bus width
+//    ld      a2, DATA_WIDTH_32_ADDR(t8)
+//    dli     a1, 0x1
+//    dsll    a1, a1, DATA_WIDTH_32_OFFSET
+//    not     a1, a1
+//    and     a2, a2, a1
+//    GET_DIMM_WIDTH
+//    dsll    a1, a1, DATA_WIDTH_32_OFFSET
+//    or      a2, a2, a1
+//    sd      a2, DATA_WIDTH_32_ADDR(t8)
+//#ifndef MC_MULTI_CHANNEL
+//    //rewrite multi_channel mode
+//    ld      a2, MC_MULTI_CHANNEL_ADDR(t8)
+//    dli     a1, 0x1
+//    dsll    a1, a1, MC_MULTI_CHANNEL_OFFSET
+//    not     a1, a1
+//    and     a2, a2, a1
+//    GET_DIMM_WIDTH
+//    dsll    a1, a1, MC_MULTI_CHANNEL_OFFSET
+//    or      a2, a2, a1
+//    sd      a2, MC_MULTI_CHANNEL_ADDR(t8)
+//#endif
+//#ifndef MC_MULTI_CHANNEL
+//    //rewrite pm_addr_win(data width)
+//    ld      a2, ADDR_WIN_DATA_WIDTH_ADDR(t8)
+//    dli     a1, 0x3
+//    dsll    a1, a1, ADDR_WIN_DATA_WIDTH_OFFSET
+//    not     a1, a1
+//    and     a2, a2, a1
+//    dli     v0, 0x3
+//    GET_DIMM_WIDTH
+//    xor     a1, v0, a1
+//    dsll    a1, a1, ADDR_WIN_DATA_WIDTH_OFFSET
+//    or      a2, a2, a1
+//    sd      a2, ADDR_WIN_DATA_WIDTH_ADDR(t8)
+//#endif
     //disable ECC module here for leveling, ECC will be enabled later
     ld      a2, ECC_ENABLE_ADDR(t8)
     dli     a1, 0x7