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1:add Targets / Bonito2g1a director 2:add zloader .2 g1a director 3:add LOONGSON2G1A configure option 4:add start_2g1a.S and modify some config window 5:fixup some problem to support 2 g1a in start_2g1a.S 6:disable some funtions, then the pmon can run on command line Change-Id: I19ee7a6d90c7efda3d6e986d12903da20ccc6ad5 Target:LS2G1Amaster
lixuefeng
10 years ago
131 changed files with 42685 additions and 69 deletions
File diff suppressed because it is too large
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####################################### |
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#define REG_ADDRESS 0x0 |
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//#define CONFIG_BASE 0xaff00000 |
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//#define CONFIG_BASE 0x900000002ff00000 |
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#define CONFIG_BASE 0x900000000ff00000 |
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.global ddr2_config |
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.ent ddr2_config |
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.set noreorder |
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.set mips3 |
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ddr2_config: |
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dli a0, CONFIG_BASE |
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la a2, ddr2_reg_data |
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addu a2, a2, s0 |
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li t1, 152 |
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daddiu v0, a0, 0x0 |
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reg_write: |
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ld a1, 0x0(a2) |
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sd a1, REG_ADDRESS(v0) |
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subu t1, t1, 0x1 |
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addiu a2, a2, 0x8 |
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bne t1, $0, reg_write |
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daddiu v0, v0, 0x10 |
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#define DEBUG_DDR_MC0 |
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#ifdef DEBUG_DDR_MC0 |
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/* store the a0,ra */ |
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move t8, a0 |
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move t1, ra |
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PRINTSTR("Change some parameters of MC0:"); |
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1: |
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PRINTSTR("\r\nPlease input the register number you want to change!!!(0:jump out.1~0x97): "); |
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li t6, 0x00 |
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bal inputaddress #input value stored in v0 |
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nop |
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move t5, v0 #store v0 to t5 |
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beqz t5, 2f #if input 0,jump out |
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nop |
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dsll t5, t5, 4 #t5 is the offset relative to a0 |
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daddu t5, t5, t8 |
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PRINTSTR("\r\nPlease input the data-hex: "); |
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li t6, 0x00 |
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bal inputaddress #input value stored in v0 |
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nop |
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sd v0, 0x0(t5) #v0 is the input value |
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b 1b |
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nop |
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2: |
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/* recover the a0,ra */ |
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move a0, t8 |
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move ra, t1 |
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#endif |
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############start########## |
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/***** set start to 1,start to initialize SDRAM *****/ |
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daddiu v0, a0, 0x0 |
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dli a2, 0x0000010000000000 |
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ld a1, 0x30(v0) |
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or a1, a1, a2 |
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sd a1, 0x30(v0) |
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daddiu v0, a0, 0x960 //wait initialization complete |
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1: |
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ld a1, 0x0(v0) |
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andi a1, a1, 0x100 |
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beqz a1, 1b |
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nop |
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//seems no need to do the following step |
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/** delay some time **/ |
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dli a2, 0xfff |
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1: |
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bnez a2, 1b |
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daddiu a2, a2, -1 |
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nop |
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daddiu v0, a0, 0x40 //write SDRAM mode register |
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dli a2, 0x0000000001000000 |
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ld a1, 0x0(v0) |
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or a1, a1, a2 |
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sd a1, 0x0(v0) |
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nop |
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sync |
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/** delay some time **/ |
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dli a2, 0xfff |
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1: |
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bnez a2, 1b |
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daddiu a2, a2, -1 |
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nop |
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############################### |
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jr ra |
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nop |
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.end ddr2_config |
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.rdata |
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.align 5 |
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.global ddr2_reg_data |
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//!!!!!!!!!!!!!!SDRAM 64Mb*16. Not use reduc!!!!!!!!!!!!!!!!!!!!! |
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ddr2_reg_data: |
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MC0_CTL_000 : .dword 0x0000010000010101 |
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//000000000000000_0 concurrentap(RW) 0000000_1 bank_split_en(RW) 0000000_0 auto_refresh_mode(RW) 0000000_0 arefresh(WR) 0000000_0 ap(RW) 0000000_1 addr_cmp_en(RW) 0000000_1 active_aging(RW) |
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MC0_CTL_010 : .dword 0x0000000100010000 |
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//0000000_0 fwc(WR) 0000000_0 fast_write(RW) 0000000_1 enable_quick_srefresh(RW) 0000000_1 eight_bank_mode(RW) 0000000_0 ecc_disable_w_uc_err(RW) 0000000_1 dqs_n_en(RW) 0000000_0 dll_bypass_mode(RW) 0000000_0 dlllockreg(RD) |
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MC0_CTL_020 : .dword 0x0100010101000000 |
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//0000000_1 priority_en(RW) 0000000_0 power_down(RW) 0000000_1 placement_en(RW) 0000000_1 odt_add_turn_clk_en(RW) 0000000_0 no_cmd_init(RW) 0000000_0 intrptwritea(RW) 0000000_0 intrptreada(RW) 0000000_0 intrptapburst(RW) |
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MC0_CTL_030 : .dword 0x0101000001000000 |
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//0000000_1 swap_port_rw_same_en(RW) 0000000_1 swap_en(RW) 0000000_0 start(RW) 0000000_0 srefresh(RW+) 0000000_1 rw_same_en(RW) 0000000_0 reg_dimm_enable(RW) 0000000_0 reduc(RW) 0000000_0 pwrup_srefresh_exit(RW) |
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MC0_CTL_040 : .dword 0x0102010200000100 |
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//000000_01 rtt_0(RW) 000000_11 ctrl_raw(RW) 000000_01 axi0_w_priority(RW) 000000_01 axi0_r_priority(RW) 0000000_0 write_modereg(WR) 0000000_1 writeinterp(RW) 0000000_1 tref_enable(RW) 0000000_1 tras_lockout(RW) |
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MC0_CTL_050 : .dword 0x0700000004060200 |
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//00000_000 q_fullness(RW) 00000_000 port_data_error_type(RD) 000_00000 out_of_range_type(RD) 00000_000 max_cs_reg(RD) 00000_100 column_size(RW) 0000_0101 caslat(RW) 00000_010 addr_pins(RW) 00000000 |
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MC0_CTL_060 : .dword 0x0a05050604040003 |
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//0000_1010 aprebit(RW) 0000_0101 wrlat(RW) 0000_0100 twtr(RW) 000_00110 twr_int(RW) 00000_011 trtp(RW) 00000_100 trrd(RW) 0000000000000_011 tcke(RW) |
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MC0_CTL_070 : .dword 0x0000020000030c0c |
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//0000_0000 max_row_reg(RD) 0000_0000 max_col_reg(RD) 0000_0000 initaref(RW) 00000000000000000000_1111 cs_map(RW) 000_01010 caslat_lin_gate(RW) 000_01010 caslat_lin(RW) |
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//MC0_CTL_080 : .dword 0x0804020100000000 |
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MC0_CTL_080 : .dword 0x0804020108040201 |
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//0000_0001 odt_wr_map_cs3(RW) 0000_0010 odt_wr_map_cs2(RW) 0000_0100 odt_wr_map_cs1(RW) 0000_1000 odt_wr_map_cs0(RW) 0000_0001 odt_rd_map_cs3(RW) 0000_0010 odt_rd_map_cs2(RW) 0000_0100 odt_rd_map_cs1(RW) 0000_1000 odt_rd_map_cs0(RW) |
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MC0_CTL_090 : .dword 0x0000070d00000000 |
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//000_00000 ocd_adjust_pup_cs_0(RW) 000_00000 ocd_adjust_pdn_cs_0(RW) 0000_0101 trp(RW) 000_01011 tdal(RW) 000000000000_0000 port_cmd_error_type(RD) 0000000000000000 |
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MC0_CTL_0a0 : .dword 0x0000003f3f180614 |
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//00000000000000000000000000_111111 command_age_count(RW) 00_111111 age_count(RW) 000_10100 trc(RW) 000_00110 tmrd(RW) 000_10010 tfaw(RW) |
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MC0_CTL_0b0 : .dword 0x0000000000000000 |
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MC0_CTL_0c0 : .dword 0x0000330612000000 |
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//000000000000000000101100 trfc(RW) 00000101 trcd_int(RW) 00001111 tras_min(RW) 00000000 out_of_range_length(RD) 00000000 ecc_u_synd(RD) 00000000 ecc_c_synd(RD) |
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MC0_CTL_0d0 : .dword 0x0000000000000000 |
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MC0_CTL_0e0 : .dword 0x0000000000000000 |
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MC0_CTL_0f0 : .dword 0x0000000000000000 |
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//Bit 21:16 dll_lock(RD) |
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MC0_CTL_100 : .dword 0x0000000000000000 |
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//MC0_CTL_110 : .dword 0x00000000000002f0 #100M+ |
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MC0_CTL_110 : .dword 0x0000000000000600 #200M+ |
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//MC0_CTL_110 : .dword 0x0000000000000910 #300M+ |
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//MC0_CTL_110 : .dword 0x0000000000000c20 #400M |
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//0_000000000000000 emrs2_data_1(RW) 0_000000000000000 emrs2_data_0(RW) 000000000000000000_00110000101101 tref(RW) |
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MC0_CTL_120 : .dword 0x001c000000000000 |
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//0000000000011100 axi0_en_size_lt_width_instr(RW) 00000000000000000_000000000000000 emrs2_data_3(RW) 0_000000000000000 emrs2_data_2(RW) |
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//MC0_CTL_130 : .dword 0x1b200003020000c8 #100M+ |
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MC0_CTL_130 : .dword 0x36800003020000c8 #200M+ |
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//MC0_CTL_130 : .dword 0x51d00003020000c8 #300M+ |
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//MC0_CTL_130 : .dword 0x6d300003020000c8 #400M |
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//0110110101010110 tras_max(RW) 0000000000000011 tpdex(RW) 0000001000000000 tdll(RW) 0000000000000000 tcpd(RW) |
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MC0_CTL_140 : .dword 0x0000204002000060 |
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//0000000000000000 xor_check_bits(RW) 0000000000000000 version(RD) 0000001000000000 txsr(RW) 0000000000110000 txsnr(RW) |
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MC0_CTL_150 : .dword 0x0000000000027100 |
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//000_0000000000000000000000000000000000000 ecc_c_addr(RD) 000000000000000000011011 tinit(RW) |
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MC0_CTL_160 : .dword 0x0000000000000000 |
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//000000000000000000000000000_0000000000000000000000000000000000000 ecc_u_addr(RD) |
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MC0_CTL_170 : .dword 0x0000000000000000 |
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//000000000000000000000000000_0000000000000000000000000000000000000 out_of_range_addr(RD) |
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MC0_CTL_180 : .dword 0x0000000000000000 |
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//000000000000000000000000000_0000000000000000000000000000000000000 port_cmd_error_addr(RD) |
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MC0_CTL_190 : .dword 0x0000000000000000 |
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//0000000000000000000000000000000000000000000000000000000000000000 ecc_c_data(RD) |
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MC0_CTL_1a0 : .dword 0x0000000000000000 |
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//0000000000000000000000000000000000000000000000000000000000000000 ecc_u_data(RD) |
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MC0_CTL_1b0 : .dword 0x0000000000000007 |
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//0000000000000000000000000000000000000000000000000000000000000_000 cke_delay(RW) |
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MC0_CTL_1c0 : .dword 0x0000000000000000 |
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MC0_CTL_1d0 : .dword 0x0200070000000001 |
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//0000_0010 tdfi_phy_wrlat_base(RW) 0000_0000 tdfi_phy_wrlat(RD) 000_00111 tdfi_phy_rdlat(RW) 0000_0000 tdfi_ctrlupd_min(RD) 000000000000_0000 dram_clk_disable(RW) 0000000_1 odt_alt_en(RW) 0000000_1 drive_dq_dqs(RW) |
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MC0_CTL_1e0 : .dword 0x0000000000000200 |
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//00_00000000000000 tdfi_phyupd_type0(RD) 00_00000000000000 tdfi_phyupd_resp(RD) 00_00000000000000 tdfi_ctrlupd_max(RD) 000_00000 tdfi_rddata_en_base(RW) 000_00000 tdfi_rddata_en(RD) |
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MC0_CTL_1f0 : .dword 0x001a188000000000 |
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MC0_CTL_200 : .dword 0x001a1880001a1880 |
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MC0_CTL_210 : .dword 0x001a1880001a1880 |
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MC0_CTL_220 : .dword 0x001a1880001a1880 |
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MC0_CTL_230 : .dword 0x001a1880001a1880 |
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MC0_CTL_240 : .dword 0x0000120000001200 |
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MC0_CTL_250 : .dword 0x0000120000001200 |
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MC0_CTL_260 : .dword 0x0000120000001200 |
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MC0_CTL_270 : .dword 0x0000120000001200 |
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MC0_CTL_280 : .dword 0x0000000000001200 |
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//hXXXXXXX 00_00 dll_obs_reg_0_0(RW) 00000000000000000000111000000000 dll_ctrl_reg_1_8(RW) |
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MC0_CTL_290 : .dword 0x0000000000000000 |
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//hXXXXXXX 00_00 dll_obs_reg_0_2(RW) hXXXXXXX 00_00 dll_obs_reg_0_1(RW) |
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MC0_CTL_2a0 : .dword 0x0000000000000000 |
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//hXXXXXXX 00_00 dll_obs_reg_0_4(RW) hXXXXXXX 00_00 dll_obs_reg_0_3(RW) |
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MC0_CTL_2b0 : .dword 0x0000000000000000 |
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//hXXXXXXX 00_00 dll_obs_reg_0_6(RW) hXXXXXXX 00_00 dll_obs_reg_0_5(RW) |
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MC0_CTL_2c0 : .dword 0x0000000000000000 |
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//hXXXXXXX 00_00 dll_obs_reg_0_8(RW) hXXXXXXX 00_00 dll_obs_reg_0_7(RW) |
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#if 1 |
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MC0_CTL_2d0 : .dword 0xc400483303c009b4 |
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MC0_CTL_2e0 : .dword 0xc4004833c4004833 |
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MC0_CTL_2f0 : .dword 0xc4004833c4004833 |
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MC0_CTL_300 : .dword 0xc4004833c4004833 |
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MC0_CTL_310 : .dword 0xc4004833c4004833 |
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#endif |
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#if 0 |
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MC0_CTL_2d0 : .dword 0x1300483303c009b4 |
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MC0_CTL_2e0 : .dword 0x1300483313004833 |
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MC0_CTL_2f0 : .dword 0x1300483313004833 |
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MC0_CTL_300 : .dword 0x1300483313004833 |
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MC0_CTL_310 : .dword 0x1300483313004833 |
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#endif |
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MC0_CTL_320 : .dword 0x26c0000126c00001 |
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MC0_CTL_330 : .dword 0x26c0000126c00001 |
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MC0_CTL_340 : .dword 0x26c0000126c00001 |
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MC0_CTL_350 : .dword 0x26c0000126c00001 |
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MC0_CTL_360 : .dword 0x0800c00026c00001 |
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//00000000000000001100000000000101 phy_ctrl_reg_2(RW) 00000111110000000000001100000001 phy_ctrl_reg_1_8(RD) |
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//-------------- |
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MC0_CTL_370 : .dword 0x0000000000000000 |
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MC0_CTL_380 : .dword 0x0000000000000000 |
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MC0_CTL_390 : .dword 0x0000000000000000 |
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MC0_CTL_3a0 : .dword 0x0000000000000000 |
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MC0_CTL_3b0 : .dword 0x0000000000000000 |
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MC0_CTL_3c0 : .dword 0x0000000000000000 |
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MC0_CTL_3d0 : .dword 0x0000000000000000 |
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MC0_CTL_3e0 : .dword 0x0000000000000000 |
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MC0_CTL_3f0 : .dword 0x0000000000000000 |
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MC0_CTL_400 : .dword 0x0000000000000000 |
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MC0_CTL_410 : .dword 0x0000000000000000 |
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MC0_CTL_420 : .dword 0x0000000000000000 |
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MC0_CTL_430 : .dword 0x0000000000000000 |
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MC0_CTL_440 : .dword 0x0000000000000000 |
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MC0_CTL_450 : .dword 0x0000000000000000 |
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MC0_CTL_460 : .dword 0x0000000000000000 |
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MC0_CTL_470 : .dword 0x0000000000000000 |
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MC0_CTL_480 : .dword 0x0000000000000000 |
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MC0_CTL_490 : .dword 0x0000000000000000 |
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MC0_CTL_4a0 : .dword 0x0000000000000000 |
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MC0_CTL_4b0 : .dword 0x0000000000000000 |
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MC0_CTL_4c0 : .dword 0x0000000000000000 |
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MC0_CTL_4d0 : .dword 0x0000000000000000 |
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MC0_CTL_4e0 : .dword 0x0000000000000000 |
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MC0_CTL_4f0 : .dword 0x0000000000000000 |
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MC0_CTL_500 : .dword 0x0000000000000000 |
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MC0_CTL_510 : .dword 0x0000000000000000 |
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MC0_CTL_520 : .dword 0x0000000000000000 |
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MC0_CTL_530 : .dword 0x0000000000000000 |
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MC0_CTL_540 : .dword 0x0000000000000000 |
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MC0_CTL_550 : .dword 0x0000000000000000 |
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MC0_CTL_560 : .dword 0x0000000000000000 |
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MC0_CTL_570 : .dword 0x0000000000000000 |
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MC0_CTL_580 : .dword 0x0000000000000000 |
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MC0_CTL_590 : .dword 0x0000000000000000 |
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MC0_CTL_5a0 : .dword 0x0000000000000000 |
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MC0_CTL_5b0 : .dword 0x0000000000000000 |
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MC0_CTL_5c0 : .dword 0x0000000000000000 |
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MC0_CTL_5d0 : .dword 0x0000000000000000 |
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MC0_CTL_5e0 : .dword 0x0000000000000000 |
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MC0_CTL_5f0 : .dword 0x0000000000000000 |
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MC0_CTL_600 : .dword 0x0000000000000000 |
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MC0_CTL_610 : .dword 0x0000000000000000 |
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MC0_CTL_620 : .dword 0x0000000000000000 |
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MC0_CTL_630 : .dword 0x0000000000000000 |
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MC0_CTL_640 : .dword 0x0000000000000000 |
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MC0_CTL_650 : .dword 0x0000000000000000 |
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MC0_CTL_660 : .dword 0x0000000000000000 |
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MC0_CTL_670 : .dword 0x0000000000000000 |
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MC0_CTL_680 : .dword 0x0000000000000000 |
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MC0_CTL_690 : .dword 0x0000000000000000 |
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MC0_CTL_6a0 : .dword 0x0000000000000000 |
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MC0_CTL_6b0 : .dword 0x0000000000000000 |
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MC0_CTL_6c0 : .dword 0x0000000000000000 |
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MC0_CTL_6d0 : .dword 0x0000000000000000 |
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MC0_CTL_6e0 : .dword 0x0000000000000000 |
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MC0_CTL_6f0 : .dword 0x0000000000000000 |
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MC0_CTL_700 : .dword 0x0000000000000000 |
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//------------- |
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MC0_CTL_710 : .dword 0x0000000000000000 |
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//bit 48 en_wr_leveling(RW) |
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MC0_CTL_720 : .dword 0x0000000000000000 |
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//0000000_0 rdlvl_gate_req(WR) 0000000_0 rdlvl_gate_preamble_check_en(RW) 0000000_0 rdlvl_gate_en(RW) 0000000_0 rdlvl_en(RW) 0000000_0 rdlvl_begin_delay_en(RW) 00000000 00000000 0000000_0 swlvl_op_done(RD) |
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MC0_CTL_730 : .dword 0x0000000000000000 |
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//0000000_0 rdlvl_offset_dir_7(RW) 0000000_0 rdlvl_offset_dir_6(RW) 0000000_0 rdlvl_offset_dir_5(RW)0000000_0 rdlvl_offset_dir_4(RW) 0000000_0 rdlvl_offset_dir_3(RW) 0000000_0 rdlvl_offset_dir_2(RW) 0000000_0 rdlvl_offset_dir_1(RW) 0000000_0 rdlvl_offset_dir_0(RW) |
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MC0_CTL_740 : .dword 0x0100000000000000 |
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//000000_00 axi1_port_ordering(RW) 000000_00 axi0_port_ordering(RW) 0000000_0 wrlvl_req(WR) 0000000_0 wrlvl_interval_ct_en(RW) 0000000_0 weight_round_robin_weight_sharing(RW) 0000000_0 weight_round_robin_latency_control 0000000_0(RW) rdlvl_req 0000000_0(WR) rdlvl_offset_dir_8(RW) |
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MC0_CTL_750 : .dword 0x0000000101020101 |
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//000000_01 wrlvl_cs(RW) 000000_00 sw_leveling_mode(RW) 000000_00 rdlvl_cs(RW) 000000_01 axi2_w_priority(RW) 000000_01 axi2_r_priority(RW) 000000_10 axi2_port_ordering(RW) 000000_01 axi1_w_priority(RW) 000000_01 axi1_r_priority(RW) |
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MC0_CTL_760 : .dword 0x0303030000020000 |
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//0000_0011 axi0_priority2_relative_priority(RW) 0000_0011 axi0_priority1_relative_priority(RW) 0000_0011 axi0_priority0_relative_priority(RW) 0000_0000 address_mirroring(RW) 00000_000 tdfi_dram_clk_disable(RW) 00000_010 bstlen(RW) 000000_00 zq_req(WR) 000000_01 zq_on_sref_exit(RW) |
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MC0_CTL_770 : .dword 0x0101010202020203 |
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//0000_0001 axi2_priority2_relative_priority(RW) 0000_0001 axi2_priority1_relative_priority(RW) 0000_0001 axi2_priority0_relative_priority(RW) 0000_0010 axi1_priority3_relative_priority(RW) 0000_0010 axi1_priority2_relative_priority(RW) 0000_0010 axi1_priority1_relative_priority(RW) 0000_0010 axi1_priority0_relative_priority(RW) 0000_0011 axi0_priority3_relative_priority(RW) |
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MC0_CTL_780 : .dword 0x0102000000040001 |
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//0000_0001 tdfi_dram_clk_enable(RW) 0000_0010 tdfi_ctrl_delay(RW) 0000_0010 rdlvl_gate_dq_zero_count(RW) 0000_0100 rdlvl_dq_zero_count(RW) 0000_0000 lowpower_refresh_enable(RW) 0000_0110 dram_class(RW) 0000_1100 burst_on_fly_bit(RW) 0000_0001 axi2_priority3_relative_priority(RW) |
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MC0_CTL_790 : .dword 0x0000000000000000 |
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//00_101000 wlmrd(RW) 00_011001 wldqsen(RW) 000_00000 lowpower_control(RW) 000_00000 lowpower_auto_enable(RW) 0000_1111 zqcs_chip(RW) 0000_0000 wrr_param_value_err(RD) 0000_0011 tdfi_wrlvl_dll(RW) 0000_0011 tdfi_rdlvl_dll(RW) |
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MC0_CTL_7a0 : .dword 0x0000000000000000 |
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//_00000000 swlvl_resp_6(RW) _00000000 swlvl_resp_5(RW) _00000000 swlvl_resp_4 _00000000 swlvl_resp_3(RW) _00000000 swlvl_resp_2(RW) _00000000 swlvl_resp_1(RW) _00000000 swlvl_resp_0(RW) _00000000 dfi_wrlvl_max_delay(RW) |
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MC0_CTL_7b0 : .dword 0x0000000000000000 |
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//_00000000 rdlvl_begin_delay_5(RW) _00000000 rdlvl_begin_delay_4(RW) _00000000 rdlvl_begin_delay_3(RW) _00000000 rdlvl_begin_delay_2(RW) _00000000 rdlvl_begin_delay_1(RW) _00000000 rdlvl_begin_delay_0(RW) _00000000 swlvl_resp_8(RW) _00000000 swlvl_resp_7(RW) |
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MC0_CTL_7c0 : .dword 0x0000000000000000 |
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//_00000000 rdlvl_end_delay_4(RW) _00000000 rdlvl_end_delay_3(RW) _00000000 rdlvl_end_delay_2(RW) _00000000 rdlvl_end_delay_1(RW) _00000000 rdlvl_end_delay_0(RW) _00000000 rdlvl_begin_delay_8(RW) _00000000 rdlvl_begin_delay_7(RW) _00000000 rdlvl_begin_delay_6(RW) |
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MC0_CTL_7d0 : .dword 0x0000000000000000 |
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//_00000000 rdlvl_gate_clk_adjust_3(RW) _00000000 rdlvl_gate_clk_adjust_2(RW) _00000000 rdlvl_gate_clk_adjust_1(RW) _00000000 rdlvl_gate_clk_adjust_0(RW) _00000000 rdlvl_end_delay_8(RW) _00000000 rdlvl_end_delay_7(RW) _00000000 rdlvl_end_delay_6(RW) 00000000 rdlvl_end_delay_5(RW) |
|||
MC0_CTL_7e0 : .dword 0x0000000000000000 |
|||
//00000000 rdlvl_gate_delay_2(RD) 00000000 rdlvl_gate_delay_1(RD) 00000000 rdlvl_gate_delay_0(RD) 00000000 rdlvl_gate_clk_adjust_8(RW) 00000000 rdlvl_gate_clk_adjust_7(RW) 00000000 rdlvl_gate_clk_adjust_6(RW) 00000000 rdlvl_gate_clk_adjust_5(RW) 00000000 rdlvl_gate_clk_adjust_4(RW) |
|||
MC0_CTL_7f0 : .dword 0x0000000000000000 |
|||
//11111111 rdlvl_max_delay(RW) 00001000 rdlvl_gate_max_delay(RW) 00000000 rdlvl_gate_delay_8(RD) 00000000 rdlvl_gate_delay_7(RD) 00000000 rdlvl_gate_delay_6(RD) 00000000 rdlvl_gate_delay_5(RD) 00000000 rdlvl_gate_delay_4(RD) 00000000 rdlvl_gate_delay_3(RD) |
|||
MC0_CTL_800 : .dword 0x0000000000000000 |
|||
//00000000 rdlvl_midpoint_delay_7(RD) 00000000 rdlvl_midpoint_delay_6(RD) 00000000 rdlvl_midpoint_delay_5(RD) 00000000 rdlvl_midpoint_delay_4(RD) 00000000 rdlvl_midpoint_delay_3(RD) 00000000 rdlvl_midpoint_delay_2(RD) 00000000 rdlvl_midpoint_delay_1(RD) 00000000 rdlvl_midpoint_delay_0(RD) |
|||
MC0_CTL_810 : .dword 0x0000000000000000 |
|||
//00000000 rdlvl_offset_delay_6(RW) 00000000 rdlvl_offset_delay_5(RW) 00000000 rdlvl_offset_delay_4(RW) 00000000 rdlvl_offset_delay_3(RW) 00000000 rdlvl_offset_delay_2(RW) 00000000 rdlvl_offset_delay_1(RW) 00000000 rdlvl_offset_delay_0(RW) 00000000 rdlvl_midpoint_delay_8(RD) |
|||
MC0_CTL_820 : .dword 0x0000000000000000 |
|||
//00000100 tdfi_wrlvl_resplat(RW) 00000000 tdfi_wrlvl_resp(RD) 00000000 tdfi_rdlvl_rr(RW) 00001100 tdfi_rdlvl_resplat(RW) 00000000 tdfi_rdlvl_resp(RD) 01000000 refresh_per_zq(RW) 00000000 rdlvl_offset_delay_8(RW) 00000000 rdlvl_offset_delay_7(RW) |
|||
MC0_CTL_830 : .dword 0x282828282828050a |
|||
//00000000 wrlvl_delay_5(RD) 00000000 wrlvl_delay_4(RD) 00000000 wrlvl_delay_3(RD) 00000000 wrlvl_delay_2(RD) 00000000 wrlvl_delay_1(RD) 00000000 wrlvl_delay_0(RD) 00000010 tmod(RW) 00001010 tdfi_wrlvl_ww(RW) |
|||
MC0_CTL_840 : .dword 0x0000640064282828 |
|||
//00000000000000_0001100100 axi1_priority_relax(RW) 000000_0001100100 axi0_priority_relax(RW) 00000000 wrlvl_delay_8(RD) 00000000 wrlvl_delay_7(RD) 00000000 wrlvl_delay_6(RD) |
|||
MC0_CTL_850 : .dword 0x0000000000000064 |
|||
//000000_0000000000 out_of_range_source_id(RD) 000000_0000000000 ecc_u_id(RD) 000000_0000000000 ecc_c_id(RD) 000000_0000000000 axi2_priority_relax(RW) |
|||
MC0_CTL_860 : .dword 0x0000000000000000 |
|||
//0000_000000000000 zqini(RW) 0000_000000000000 zqcs(RW) 000000_0000000000 port_data_error_id(RD) 000000_0000000000 port_cmd_error_id(RD) |
|||
MC0_CTL_870 : .dword 0x0044004400440044 |
|||
//0_000000000000010 emrs1_data_3(RW) 0_000000000000010 emrs1_data_2(RW) 0_000000000000010 emrs1_data_1(RW) 0_000000000000010 emrs1_data_0(RW) |
|||
MC0_CTL_880 : .dword 0x0000000000000000 |
|||
//0_000000000000010 emrs3_data_3(RW) 0_000000000000010 emrs3_data_2(RW) 0_000000000000010 emrs3_data_1(RW) 0_000000000000010 emrs3_data_0(RW) |
|||
MC0_CTL_890 : .dword 0x0a620a620a620a62 |
|||
//0_000010000010000 mrs_data_3(RW) 0_000010000010000 mrs_data_2(RW) 0_000010000010000 mrs_data_1(RW) 0_000010000010000 mrs_data_0(RW) |
|||
MC0_CTL_8a0 : .dword 0x00000000001c001c |
|||
//hXXXX lowpower_internal_cnt(RW) hXXXX lowpower_external_cnt(RW) hXXXX axi2_en_size_lt_width_instr(RW) hXXXX axi1_en_size_lt_width_instr(RW) |
|||
MC0_CTL_8b0 : .dword 0x0000000000000000 |
|||
//hXXXX refresh_per_rdlvl(RW) hXXXX lowpower_self_refresh_cnt(RW) hXXXX lowpower_refresh_hold(RW) hXXXX lowpower_power_down_cnt(RW) |
|||
MC0_CTL_8c0 : .dword 0x0000000000000000 |
|||
//hXXXX wrlvl_interval(RW) hXXXX tdfi_wrlvl_max(RW) hXXXX tdfi_rdlvl_max(RW) hXXXX refresh_per_rdlvl_gate(RW) |
|||
MC0_CTL_8d0 : .dword 0x002faf0800000000 |
|||
//h00_XXXXXXXX cke_inactive(RW) 000000_000000000000000000 wrlvl_status(RD) |
|||
MC0_CTL_8e0 : .dword 0x0000000023c34600 |
|||
//h00000000_XXXXXXXX trst_pwron(RW) |
|||
MC0_CTL_8f0 : .dword 0x0000000020202080 |
|||
//MC0_CTL_8f0 : .dword 0x0000000030343080 |
|||
//hXXXXXXX 000_0 XXXXXXXX dll_ctrl_reg_2(RW) |
|||
MC0_CTL_900 : .dword 0x0000000000000000 |
|||
//h000000 00_00 X XXXXXXXX rdlvl_error_status(RW) |
|||
MC0_CTL_910 : .dword 0x0000000000000000 |
|||
//hXXXXXXXX XXXXXXXX rdlvl_gate_resp_mask[63:0](RW) |
|||
MC0_CTL_920 : .dword 0x0000000000000000 |
|||
//h00000000000000_XX rdlvl_gate_resp_mask[71:64](RW) |
|||
MC0_CTL_930 : .dword 0x0000000000000000 |
|||
//hXXXXXXXX XXXXXXXX rdlvl_resp_mask[63:0](RW) |
|||
MC0_CTL_940 : .dword 0x0006060000050500 |
|||
//0000_0000 tdfi_rdlvl_en(RW) 00000_000 w2r_samecs_delay(RW) 00000_000 w2r_diffcs_delay(RW) 00000_000 lvl_status(RD) 0000000_0 rdlvl_edge(RW) 0000_0000 cksrx(RW) 0000_0000 cksre(RW) _00000000 rdlvl_resp_mask[71:64](RW) |
|||
MC0_CTL_950 : .dword 0x0000000000001000 |
|||
//hXXXXX 00_00 XXXX mask_int[17:0](RW) hXXXX txpdll(RW) 0000_0000 tdfi_wrlvl_en(RW) |
|||
MC0_CTL_960 : .dword 0x0705000000000000 |
|||
//000_00101 rdlat_adj(RW) 0000_0100 wrlat_adj(RW) 0000000_0 swlvl_start(WR) 0000000_0 swlvl_load(WR) 0000000_0 swlvl_exit(WR) 000000_000000000000000000 int_status(RD) |
|||
MC0_CTL_970 : .dword 0x000000000003e805 |
|||
//h00000 000_0 XXXX int_ack[16:0](WR) hXXXX dll_rst_delay(RW) hXX dll_rst_adj_dly(RW) |
|||
@ -0,0 +1,370 @@ |
|||
####################################### |
|||
#define REG_ADDRESS 0x0 |
|||
//#define CONFIG_BASE 0xaff00000 |
|||
//#define CONFIG_BASE 0x900000002ff00000 |
|||
#define CONFIG_BASE 0x900000000ff00000 |
|||
|
|||
|
|||
.global ddr2_config |
|||
.ent ddr2_config |
|||
.set noreorder |
|||
.set mips3 |
|||
ddr2_config: |
|||
dli a0, CONFIG_BASE |
|||
la a2, ddr2_reg_data |
|||
addu a2, a2, s0 |
|||
li t1, 152 |
|||
daddiu v0, a0, 0x0 |
|||
|
|||
reg_write: |
|||
|
|||
ld a1, 0x0(a2) |
|||
sd a1, REG_ADDRESS(v0) |
|||
|
|||
subu t1, t1, 0x1 |
|||
addiu a2, a2, 0x8 |
|||
bne t1, $0, reg_write |
|||
daddiu v0, v0, 0x10 |
|||
|
|||
//#define DEBUG_DDR_MC0 |
|||
#ifdef DEBUG_DDR_MC0 |
|||
/* store the a0,ra */ |
|||
move t8, a0 |
|||
move t1, ra |
|||
|
|||
PRINTSTR("Change some parameters of MC0:"); |
|||
1: |
|||
PRINTSTR("\r\nPlease input the register number you want to change!!!(0:jump out.1~0x97): "); |
|||
li t6, 0x00 |
|||
bal inputaddress #input value stored in v0 |
|||
nop |
|||
move t5, v0 #store v0 to t5 |
|||
|
|||
beqz t5, 2f #if input 0,jump out |
|||
nop |
|||
dsll t5, t5, 4 #t5 is the offset relative to a0 |
|||
daddu t5, t5, t8 |
|||
|
|||
PRINTSTR("\r\nPlease input the data-hex: "); |
|||
li t6, 0x00 |
|||
bal inputaddress #input value stored in v0 |
|||
nop |
|||
sd v0, 0x0(t5) #v0 is the input value |
|||
b 1b |
|||
nop |
|||
2: |
|||
/* recover the a0,ra */ |
|||
move a0, t8 |
|||
move ra, t1 |
|||
#endif |
|||
|
|||
############start########## |
|||
/***** set start to 1,start to initialize SDRAM *****/ |
|||
daddiu v0, a0, 0x0 |
|||
dli a2, 0x0000010000000000 |
|||
ld a1, 0x30(v0) |
|||
or a1, a1, a2 |
|||
sd a1, 0x30(v0) |
|||
|
|||
daddiu v0, a0, 0x960 //wait initialization complete |
|||
1: |
|||
ld a1, 0x0(v0) |
|||
andi a1, a1, 0x100 |
|||
beqz a1, 1b |
|||
nop |
|||
|
|||
//seems no need to do the following step |
|||
/** delay some time **/ |
|||
dli a2, 0xfff |
|||
1: |
|||
bnez a2, 1b |
|||
daddiu a2, a2, -1 |
|||
nop |
|||
|
|||
daddiu v0, a0, 0x40 //write SDRAM mode register |
|||
dli a2, 0x0000000001000000 |
|||
ld a1, 0x0(v0) |
|||
or a1, a1, a2 |
|||
sd a1, 0x0(v0) |
|||
nop |
|||
sync |
|||
|
|||
/** delay some time **/ |
|||
dli a2, 0xfff |
|||
1: |
|||
bnez a2, 1b |
|||
daddiu a2, a2, -1 |
|||
nop |
|||
############################### |
|||
|
|||
jr ra |
|||
nop |
|||
.end ddr2_config |
|||
|
|||
.rdata |
|||
.align 5 |
|||
.global ddr2_reg_data |
|||
//!!!!!!!!!!!!!!SDRAM 64Mb*16. Not use reduc!!!!!!!!!!!!!!!!!!!!! |
|||
ddr2_reg_data: |
|||
MC0_CTL_000 : .dword 0x0000010000010101 |
|||
//000000000000000_0 concurrentap(RW) 0000000_1 bank_split_en(RW) 0000000_0 auto_refresh_mode(RW) 0000000_0 arefresh(WR) 0000000_0 ap(RW) 0000000_1 addr_cmp_en(RW) 0000000_1 active_aging(RW) |
|||
MC0_CTL_010 : .dword 0x0000000100010000 |
|||
//0000000_0 fwc(WR) 0000000_0 fast_write(RW) 0000000_1 enable_quick_srefresh(RW) 0000000_1 eight_bank_mode(RW) 0000000_0 ecc_disable_w_uc_err(RW) 0000000_1 dqs_n_en(RW) 0000000_0 dll_bypass_mode(RW) 0000000_0 dlllockreg(RD) |
|||
MC0_CTL_020 : .dword 0x0000000101000000 |
|||
//0000000_1 priority_en(RW) 0000000_0 power_down(RW) 0000000_1 placement_en(RW) 0000000_1 odt_add_turn_clk_en(RW) 0000000_0 no_cmd_init(RW) 0000000_0 intrptwritea(RW) 0000000_0 intrptreada(RW) 0000000_0 intrptapburst(RW) |
|||
MC0_CTL_030 : .dword 0x0001000001000000 |
|||
//0000000_1 swap_port_rw_same_en(RW) 0000000_1 swap_en(RW) 0000000_0 start(RW) 0000000_0 srefresh(RW+) 0000000_1 rw_same_en(RW) 0000000_0 reg_dimm_enable(RW) 0000000_0 reduc(RW) 0000000_0 pwrup_srefresh_exit(RW) |
|||
MC0_CTL_040 : .dword 0x0100010200000100 |
|||
//000000_01 rtt_0(RW) 000000_11 ctrl_raw(RW) 000000_01 axi0_w_priority(RW) 000000_01 axi0_r_priority(RW) 0000000_0 write_modereg(WR) 0000000_1 writeinterp(RW) 0000000_1 tref_enable(RW) 0000000_1 tras_lockout(RW) |
|||
MC0_CTL_050 : .dword 0x0200000004050200 |
|||
//00000_000 q_fullness(RW) 00000_000 port_data_error_type(RD) 000_00000 out_of_range_type(RD) 00000_000 max_cs_reg(RD) 00000_100 column_size(RW) 0000_0101 caslat(RW) 00000_010 addr_pins(RW) 00000000 |
|||
MC0_CTL_060 : .dword 0x0a04050604040003 |
|||
//0000_1010 aprebit(RW) 0000_0101 wrlat(RW) 0000_0100 twtr(RW) 000_00110 twr_int(RW) 00000_011 trtp(RW) 00000_100 trrd(RW) 0000000000000_011 tcke(RW) |
|||
MC0_CTL_070 : .dword 0x0000020000030a0a |
|||
//0000_0000 max_row_reg(RD) 0000_0000 max_col_reg(RD) 0000_0000 initaref(RW) 00000000000000000000_1111 cs_map(RW) 000_01010 caslat_lin_gate(RW) 000_01010 caslat_lin(RW) |
|||
//MC0_CTL_080 : .dword 0x0804020100000000 |
|||
MC0_CTL_080 : .dword 0x0804020108040201 |
|||
//0000_0001 odt_wr_map_cs3(RW) 0000_0010 odt_wr_map_cs2(RW) 0000_0100 odt_wr_map_cs1(RW) 0000_1000 odt_wr_map_cs0(RW) 0000_0001 odt_rd_map_cs3(RW) 0000_0010 odt_rd_map_cs2(RW) 0000_0100 odt_rd_map_cs1(RW) 0000_1000 odt_rd_map_cs0(RW) |
|||
MC0_CTL_090 : .dword 0x0000070d00000000 |
|||
//000_00000 ocd_adjust_pup_cs_0(RW) 000_00000 ocd_adjust_pdn_cs_0(RW) 0000_0101 trp(RW) 000_01011 tdal(RW) 000000000000_0000 port_cmd_error_type(RD) 0000000000000000 |
|||
MC0_CTL_0a0 : .dword 0x0000003f3f180614 |
|||
//00000000000000000000000000_111111 command_age_count(RW) 00_111111 age_count(RW) 000_10100 trc(RW) 000_00110 tmrd(RW) 000_10010 tfaw(RW) |
|||
MC0_CTL_0b0 : .dword 0x0000000000000000 |
|||
MC0_CTL_0c0 : .dword 0x0000330612000000 |
|||
//000000000000000000101100 trfc(RW) 00000101 trcd_int(RW) 00001111 tras_min(RW) 00000000 out_of_range_length(RD) 00000000 ecc_u_synd(RD) 00000000 ecc_c_synd(RD) |
|||
MC0_CTL_0d0 : .dword 0x0000000000000000 |
|||
MC0_CTL_0e0 : .dword 0x0000000000000000 |
|||
MC0_CTL_0f0 : .dword 0x0000000000000000 |
|||
//Bit 21:16 dll_lock(RD) |
|||
MC0_CTL_100 : .dword 0x0000000000000000 |
|||
//MC0_CTL_110 : .dword 0x0000000000000300 #100M+ |
|||
MC0_CTL_110 : .dword 0x0000000000000618 #200M+ |
|||
//MC0_CTL_110 : .dword 0x0000000000000924 #300M+ |
|||
//MC0_CTL_110 : .dword 0x0000000000000c30 #400M |
|||
//0_000000000000000 emrs2_data_1(RW) 0_000000000000000 emrs2_data_0(RW) 000000000000000000_00110000101101 tref(RW) |
|||
MC0_CTL_120 : .dword 0xffff000000000000 |
|||
//0000000000011100 axi0_en_size_lt_width_instr(RW) 00000000000000000_000000000000000 emrs2_data_3(RW) 0_000000000000000 emrs2_data_2(RW) |
|||
//MC0_CTL_130 : .dword 0x1a00000202000000 #100M+ |
|||
MC0_CTL_130 : .dword 0x36800003020000c8 #200M+ |
|||
//MC0_CTL_130 : .dword 0x36b0000202000000 #200M+ |
|||
//MC0_CTL_130 : .dword 0x51f0000202000000 #300M+ |
|||
//MC0_CTL_130 : .dword 0x6d60000202000000 #400M |
|||
//0110110101010110 tras_max(RW) 0000000000000011 tpdex(RW) 0000001000000000 tdll(RW) 0000000000000000 tcpd(RW) |
|||
MC0_CTL_140 : .dword 0x0000204002000060 |
|||
//0000000000000000 xor_check_bits(RW) 0000000000000000 version(RD) 0000001000000000 txsr(RW) 0000000000110000 txsnr(RW) |
|||
MC0_CTL_150 : .dword 0x0000000000027100 |
|||
//000_0000000000000000000000000000000000000 ecc_c_addr(RD) 000000000000000000011011 tinit(RW) |
|||
MC0_CTL_160 : .dword 0x0000000000000000 |
|||
//000000000000000000000000000_0000000000000000000000000000000000000 ecc_u_addr(RD) |
|||
MC0_CTL_170 : .dword 0x0000000000000000 |
|||
//000000000000000000000000000_0000000000000000000000000000000000000 out_of_range_addr(RD) |
|||
MC0_CTL_180 : .dword 0x0000000000000000 |
|||
//000000000000000000000000000_0000000000000000000000000000000000000 port_cmd_error_addr(RD) |
|||
MC0_CTL_190 : .dword 0x0000000000000000 |
|||
//0000000000000000000000000000000000000000000000000000000000000000 ecc_c_data(RD) |
|||
MC0_CTL_1a0 : .dword 0x0000000000000000 |
|||
//0000000000000000000000000000000000000000000000000000000000000000 ecc_u_data(RD) |
|||
MC0_CTL_1b0 : .dword 0x0000000000000000 |
|||
//0000000000000000000000000000000000000000000000000000000000000_000 cke_delay(RW) |
|||
MC0_CTL_1c0 : .dword 0x0000000000000000 |
|||
MC0_CTL_1d0 : .dword 0x0200070000000001 |
|||
//0000_0010 tdfi_phy_wrlat_base(RW) 0000_0000 tdfi_phy_wrlat(RD) 000_00111 tdfi_phy_rdlat(RW) 0000_0000 tdfi_ctrlupd_min(RD) 000000000000_0000 dram_clk_disable(RW) 0000000_1 odt_alt_en(RW) 0000000_1 drive_dq_dqs(RW) |
|||
MC0_CTL_1e0 : .dword 0x0000000000000200 |
|||
//00_00000000000000 tdfi_phyupd_type0(RD) 00_00000000000000 tdfi_phyupd_resp(RD) 00_00000000000000 tdfi_ctrlupd_max(RD) 000_00000 tdfi_rddata_en_base(RW) 000_00000 tdfi_rddata_en(RD) |
|||
|
|||
MC0_CTL_1f0 : .dword 0x001a188000000000 |
|||
MC0_CTL_200 : .dword 0x001a1880001a1880 |
|||
MC0_CTL_210 : .dword 0x001a1880001a1880 |
|||
MC0_CTL_220 : .dword 0x001a1880001a1880 |
|||
//MC0_CTL_230 : .dword 0x001a1880001a1880 |
|||
MC0_CTL_230 : .dword 0x001a188000241880 |
|||
MC0_CTL_240 : .dword 0x0000120000001200 |
|||
MC0_CTL_250 : .dword 0x0000120000001200 |
|||
MC0_CTL_260 : .dword 0x0000120000001200 |
|||
MC0_CTL_270 : .dword 0x0000120000001200 |
|||
MC0_CTL_280 : .dword 0x0000000000001200 |
|||
//hXXXXXXX 00_00 dll_obs_reg_0_0(RW) 00000000000000000000111000000000 dll_ctrl_reg_1_8(RW) |
|||
MC0_CTL_290 : .dword 0x0000000000000000 |
|||
//hXXXXXXX 00_00 dll_obs_reg_0_2(RW) hXXXXXXX 00_00 dll_obs_reg_0_1(RW) |
|||
MC0_CTL_2a0 : .dword 0x0000000000000000 |
|||
//hXXXXXXX 00_00 dll_obs_reg_0_4(RW) hXXXXXXX 00_00 dll_obs_reg_0_3(RW) |
|||
MC0_CTL_2b0 : .dword 0x0000000000000000 |
|||
//hXXXXXXX 00_00 dll_obs_reg_0_6(RW) hXXXXXXX 00_00 dll_obs_reg_0_5(RW) |
|||
MC0_CTL_2c0 : .dword 0x0000000000000000 |
|||
//hXXXXXXX 00_00 dll_obs_reg_0_8(RW) hXXXXXXX 00_00 dll_obs_reg_0_7(RW) |
|||
#if 1 |
|||
MC0_CTL_2d0 : .dword 0xc400483303c009b4 |
|||
MC0_CTL_2e0 : .dword 0xc4004833c4004833 |
|||
MC0_CTL_2f0 : .dword 0xc4004833c4004833 |
|||
MC0_CTL_300 : .dword 0xc4004833c4004833 |
|||
MC0_CTL_310 : .dword 0xc4004833c4004833 |
|||
#endif |
|||
#if 0 |
|||
MC0_CTL_2d0 : .dword 0x1300483303c009b4 |
|||
MC0_CTL_2e0 : .dword 0x1300483313004833 |
|||
MC0_CTL_2f0 : .dword 0x1300483313004833 |
|||
MC0_CTL_300 : .dword 0x1300483313004833 |
|||
MC0_CTL_310 : .dword 0x1300483313004833 |
|||
#endif |
|||
MC0_CTL_320 : .dword 0x26c0000126c00001 |
|||
MC0_CTL_330 : .dword 0x26c0000126c00001 |
|||
MC0_CTL_340 : .dword 0x26c0000126c00001 |
|||
MC0_CTL_350 : .dword 0x26c0000126c00001 |
|||
MC0_CTL_360 : .dword 0x0800c00026c00001 |
|||
//00000000000000001100000000000101 phy_ctrl_reg_2(RW) 00000111110000000000001100000001 phy_ctrl_reg_1_8(RD) |
|||
//-------------- |
|||
MC0_CTL_370 : .dword 0x0000000000000000 |
|||
MC0_CTL_380 : .dword 0x0000000000000000 |
|||
MC0_CTL_390 : .dword 0x0000000000000000 |
|||
MC0_CTL_3a0 : .dword 0x0000000000000000 |
|||
MC0_CTL_3b0 : .dword 0x0000000000000000 |
|||
MC0_CTL_3c0 : .dword 0x0000000000000000 |
|||
MC0_CTL_3d0 : .dword 0x0000000000000000 |
|||
MC0_CTL_3e0 : .dword 0x0000000000000000 |
|||
MC0_CTL_3f0 : .dword 0x0000000000000000 |
|||
MC0_CTL_400 : .dword 0x0000000000000000 |
|||
MC0_CTL_410 : .dword 0x0000000000000000 |
|||
MC0_CTL_420 : .dword 0x0000000000000000 |
|||
MC0_CTL_430 : .dword 0x0000000000000000 |
|||
MC0_CTL_440 : .dword 0x0000000000000000 |
|||
MC0_CTL_450 : .dword 0x0000000000000000 |
|||
MC0_CTL_460 : .dword 0x0000000000000000 |
|||
MC0_CTL_470 : .dword 0x0000000000000000 |
|||
MC0_CTL_480 : .dword 0x0000000000000000 |
|||
MC0_CTL_490 : .dword 0x0000000000000000 |
|||
MC0_CTL_4a0 : .dword 0x0000000000000000 |
|||
MC0_CTL_4b0 : .dword 0x0000000000000000 |
|||
MC0_CTL_4c0 : .dword 0x0000000000000000 |
|||
MC0_CTL_4d0 : .dword 0x0000000000000000 |
|||
MC0_CTL_4e0 : .dword 0x0000000000000000 |
|||
MC0_CTL_4f0 : .dword 0x0000000000000000 |
|||
MC0_CTL_500 : .dword 0x0000000000000000 |
|||
MC0_CTL_510 : .dword 0x0000000000000000 |
|||
MC0_CTL_520 : .dword 0x0000000000000000 |
|||
MC0_CTL_530 : .dword 0x0000000000000000 |
|||
MC0_CTL_540 : .dword 0x0000000000000000 |
|||
MC0_CTL_550 : .dword 0x0000000000000000 |
|||
MC0_CTL_560 : .dword 0x0000000000000000 |
|||
MC0_CTL_570 : .dword 0x0000000000000000 |
|||
MC0_CTL_580 : .dword 0x0000000000000000 |
|||
MC0_CTL_590 : .dword 0x0000000000000000 |
|||
MC0_CTL_5a0 : .dword 0x0000000000000000 |
|||
MC0_CTL_5b0 : .dword 0x0000000000000000 |
|||
MC0_CTL_5c0 : .dword 0x0000000000000000 |
|||
MC0_CTL_5d0 : .dword 0x0000000000000000 |
|||
MC0_CTL_5e0 : .dword 0x0000000000000000 |
|||
MC0_CTL_5f0 : .dword 0x0000000000000000 |
|||
MC0_CTL_600 : .dword 0x0000000000000000 |
|||
MC0_CTL_610 : .dword 0x0000000000000000 |
|||
MC0_CTL_620 : .dword 0x0000000000000000 |
|||
MC0_CTL_630 : .dword 0x0000000000000000 |
|||
MC0_CTL_640 : .dword 0x0000000000000000 |
|||
MC0_CTL_650 : .dword 0x0000000000000000 |
|||
MC0_CTL_660 : .dword 0x0000000000000000 |
|||
MC0_CTL_670 : .dword 0x0000000000000000 |
|||
MC0_CTL_680 : .dword 0x0000000000000000 |
|||
MC0_CTL_690 : .dword 0x0000000000000000 |
|||
MC0_CTL_6a0 : .dword 0x0000000000000000 |
|||
MC0_CTL_6b0 : .dword 0x0000000000000000 |
|||
MC0_CTL_6c0 : .dword 0x0000000000000000 |
|||
MC0_CTL_6d0 : .dword 0x0000000000000000 |
|||
MC0_CTL_6e0 : .dword 0x0000000000000000 |
|||
MC0_CTL_6f0 : .dword 0x0000000000000000 |
|||
MC0_CTL_700 : .dword 0x0000000000000000 |
|||
//------------- |
|||
MC0_CTL_710 : .dword 0x0000000000000000 |
|||
//bit 48 en_wr_leveling(RW) |
|||
MC0_CTL_720 : .dword 0x0000000000000000 |
|||
//0000000_0 rdlvl_gate_req(WR) 0000000_0 rdlvl_gate_preamble_check_en(RW) 0000000_0 rdlvl_gate_en(RW) 0000000_0 rdlvl_en(RW) 0000000_0 rdlvl_begin_delay_en(RW) 00000000 00000000 0000000_0 swlvl_op_done(RD) |
|||
MC0_CTL_730 : .dword 0x0000000000000000 |
|||
//0000000_0 rdlvl_offset_dir_7(RW) 0000000_0 rdlvl_offset_dir_6(RW) 0000000_0 rdlvl_offset_dir_5(RW)0000000_0 rdlvl_offset_dir_4(RW) 0000000_0 rdlvl_offset_dir_3(RW) 0000000_0 rdlvl_offset_dir_2(RW) 0000000_0 rdlvl_offset_dir_1(RW) 0000000_0 rdlvl_offset_dir_0(RW) |
|||
MC0_CTL_740 : .dword 0x0100000000000000 |
|||
//000000_00 axi1_port_ordering(RW) 000000_00 axi0_port_ordering(RW) 0000000_0 wrlvl_req(WR) 0000000_0 wrlvl_interval_ct_en(RW) 0000000_0 weight_round_robin_weight_sharing(RW) 0000000_0 weight_round_robin_latency_control 0000000_0(RW) rdlvl_req 0000000_0(WR) rdlvl_offset_dir_8(RW) |
|||
MC0_CTL_750 : .dword 0x0000000101020101 |
|||
//000000_01 wrlvl_cs(RW) 000000_00 sw_leveling_mode(RW) 000000_00 rdlvl_cs(RW) 000000_01 axi2_w_priority(RW) 000000_01 axi2_r_priority(RW) 000000_10 axi2_port_ordering(RW) 000000_01 axi1_w_priority(RW) 000000_01 axi1_r_priority(RW) |
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MC0_CTL_760 : .dword 0x0303030000020000 |
|||
//0000_0011 axi0_priority2_relative_priority(RW) 0000_0011 axi0_priority1_relative_priority(RW) 0000_0011 axi0_priority0_relative_priority(RW) 0000_0000 address_mirroring(RW) 00000_000 tdfi_dram_clk_disable(RW) 00000_010 bstlen(RW) 000000_00 zq_req(WR) 000000_01 zq_on_sref_exit(RW) |
|||
MC0_CTL_770 : .dword 0x0101010202020203 |
|||
//0000_0001 axi2_priority2_relative_priority(RW) 0000_0001 axi2_priority1_relative_priority(RW) 0000_0001 axi2_priority0_relative_priority(RW) 0000_0010 axi1_priority3_relative_priority(RW) 0000_0010 axi1_priority2_relative_priority(RW) 0000_0010 axi1_priority1_relative_priority(RW) 0000_0010 axi1_priority0_relative_priority(RW) 0000_0011 axi0_priority3_relative_priority(RW) |
|||
MC0_CTL_780 : .dword 0x0102000000040001 |
|||
//0000_0001 tdfi_dram_clk_enable(RW) 0000_0010 tdfi_ctrl_delay(RW) 0000_0010 rdlvl_gate_dq_zero_count(RW) 0000_0100 rdlvl_dq_zero_count(RW) 0000_0000 lowpower_refresh_enable(RW) 0000_0110 dram_class(RW) 0000_1100 burst_on_fly_bit(RW) 0000_0001 axi2_priority3_relative_priority(RW) |
|||
MC0_CTL_790 : .dword 0x0000000000000000 |
|||
//00_101000 wlmrd(RW) 00_011001 wldqsen(RW) 000_00000 lowpower_control(RW) 000_00000 lowpower_auto_enable(RW) 0000_1111 zqcs_chip(RW) 0000_0000 wrr_param_value_err(RD) 0000_0011 tdfi_wrlvl_dll(RW) 0000_0011 tdfi_rdlvl_dll(RW) |
|||
MC0_CTL_7a0 : .dword 0x0000000000000000 |
|||
//_00000000 swlvl_resp_6(RW) _00000000 swlvl_resp_5(RW) _00000000 swlvl_resp_4 _00000000 swlvl_resp_3(RW) _00000000 swlvl_resp_2(RW) _00000000 swlvl_resp_1(RW) _00000000 swlvl_resp_0(RW) _00000000 dfi_wrlvl_max_delay(RW) |
|||
MC0_CTL_7b0 : .dword 0x0000000000000000 |
|||
//_00000000 rdlvl_begin_delay_5(RW) _00000000 rdlvl_begin_delay_4(RW) _00000000 rdlvl_begin_delay_3(RW) _00000000 rdlvl_begin_delay_2(RW) _00000000 rdlvl_begin_delay_1(RW) _00000000 rdlvl_begin_delay_0(RW) _00000000 swlvl_resp_8(RW) _00000000 swlvl_resp_7(RW) |
|||
MC0_CTL_7c0 : .dword 0x0000000000000000 |
|||
//_00000000 rdlvl_end_delay_4(RW) _00000000 rdlvl_end_delay_3(RW) _00000000 rdlvl_end_delay_2(RW) _00000000 rdlvl_end_delay_1(RW) _00000000 rdlvl_end_delay_0(RW) _00000000 rdlvl_begin_delay_8(RW) _00000000 rdlvl_begin_delay_7(RW) _00000000 rdlvl_begin_delay_6(RW) |
|||
MC0_CTL_7d0 : .dword 0x0000000000000000 |
|||
//_00000000 rdlvl_gate_clk_adjust_3(RW) _00000000 rdlvl_gate_clk_adjust_2(RW) _00000000 rdlvl_gate_clk_adjust_1(RW) _00000000 rdlvl_gate_clk_adjust_0(RW) _00000000 rdlvl_end_delay_8(RW) _00000000 rdlvl_end_delay_7(RW) _00000000 rdlvl_end_delay_6(RW) 00000000 rdlvl_end_delay_5(RW) |
|||
MC0_CTL_7e0 : .dword 0x0000000000000000 |
|||
//00000000 rdlvl_gate_delay_2(RD) 00000000 rdlvl_gate_delay_1(RD) 00000000 rdlvl_gate_delay_0(RD) 00000000 rdlvl_gate_clk_adjust_8(RW) 00000000 rdlvl_gate_clk_adjust_7(RW) 00000000 rdlvl_gate_clk_adjust_6(RW) 00000000 rdlvl_gate_clk_adjust_5(RW) 00000000 rdlvl_gate_clk_adjust_4(RW) |
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MC0_CTL_7f0 : .dword 0x0000000000000000 |
|||
//11111111 rdlvl_max_delay(RW) 00001000 rdlvl_gate_max_delay(RW) 00000000 rdlvl_gate_delay_8(RD) 00000000 rdlvl_gate_delay_7(RD) 00000000 rdlvl_gate_delay_6(RD) 00000000 rdlvl_gate_delay_5(RD) 00000000 rdlvl_gate_delay_4(RD) 00000000 rdlvl_gate_delay_3(RD) |
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MC0_CTL_800 : .dword 0x0000000000000000 |
|||
//00000000 rdlvl_midpoint_delay_7(RD) 00000000 rdlvl_midpoint_delay_6(RD) 00000000 rdlvl_midpoint_delay_5(RD) 00000000 rdlvl_midpoint_delay_4(RD) 00000000 rdlvl_midpoint_delay_3(RD) 00000000 rdlvl_midpoint_delay_2(RD) 00000000 rdlvl_midpoint_delay_1(RD) 00000000 rdlvl_midpoint_delay_0(RD) |
|||
MC0_CTL_810 : .dword 0x0000000000000000 |
|||
//00000000 rdlvl_offset_delay_6(RW) 00000000 rdlvl_offset_delay_5(RW) 00000000 rdlvl_offset_delay_4(RW) 00000000 rdlvl_offset_delay_3(RW) 00000000 rdlvl_offset_delay_2(RW) 00000000 rdlvl_offset_delay_1(RW) 00000000 rdlvl_offset_delay_0(RW) 00000000 rdlvl_midpoint_delay_8(RD) |
|||
MC0_CTL_820 : .dword 0x0000000000000000 |
|||
//00000100 tdfi_wrlvl_resplat(RW) 00000000 tdfi_wrlvl_resp(RD) 00000000 tdfi_rdlvl_rr(RW) 00001100 tdfi_rdlvl_resplat(RW) 00000000 tdfi_rdlvl_resp(RD) 01000000 refresh_per_zq(RW) 00000000 rdlvl_offset_delay_8(RW) 00000000 rdlvl_offset_delay_7(RW) |
|||
MC0_CTL_830 : .dword 0x282828282828050a |
|||
//MC0_CTL_830 : .dword 0x000000000000020a |
|||
//MC0_CTL_830 : .dword 0x1c24241c1c1c0c0a |
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//MC0_CTL_830 : .dword 0x40444b474543020a |
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//00000000 wrlvl_delay_5(RD) 00000000 wrlvl_delay_4(RD) 00000000 wrlvl_delay_3(RD) 00000000 wrlvl_delay_2(RD) 00000000 wrlvl_delay_1(RD) 00000000 wrlvl_delay_0(RD) 00000010 tmod(RW) 00001010 tdfi_wrlvl_ww(RW) |
|||
MC0_CTL_840 : .dword 0x0000640064282828 |
|||
//MC0_CTL_840 : .dword 0x0000640064000000 |
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//MC0_CTL_840 : .dword 0x0000640064001c1c |
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//MC0_CTL_840 : .dword 0x0000640064003b3c |
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//00000000000000_0001100100 axi1_priority_relax(RW) 000000_0001100100 axi0_priority_relax(RW) 00000000 wrlvl_delay_8(RD) 00000000 wrlvl_delay_7(RD) 00000000 wrlvl_delay_6(RD) |
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MC0_CTL_850 : .dword 0x0000000000000064 |
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//000000_0000000000 out_of_range_source_id(RD) 000000_0000000000 ecc_u_id(RD) 000000_0000000000 ecc_c_id(RD) 000000_0000000000 axi2_priority_relax(RW) |
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MC0_CTL_860 : .dword 0x0000000000000000 |
|||
//0000_000000000000 zqini(RW) 0000_000000000000 zqcs(RW) 000000_0000000000 port_data_error_id(RD) 000000_0000000000 port_cmd_error_id(RD) |
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//MC0_CTL_870 : .dword 0x0046004600460046 |
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MC0_CTL_870 : .dword 0x0044004400440044 |
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//0_000000000000010 emrs1_data_3(RW) 0_000000000000010 emrs1_data_2(RW) 0_000000000000010 emrs1_data_1(RW) 0_000000000000010 emrs1_data_0(RW) |
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MC0_CTL_880 : .dword 0x0000000000000000 |
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//0_000000000000010 emrs3_data_3(RW) 0_000000000000010 emrs3_data_2(RW) 0_000000000000010 emrs3_data_1(RW) 0_000000000000010 emrs3_data_0(RW) |
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//MC0_CTL_890 : .dword 0x0a620a620a620a62 |
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MC0_CTL_890 : .dword 0x0a520a520a520a52 |
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//0_000010000010000 mrs_data_3(RW) 0_000010000010000 mrs_data_2(RW) 0_000010000010000 mrs_data_1(RW) 0_000010000010000 mrs_data_0(RW) |
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MC0_CTL_8a0 : .dword 0x00000000001c001c |
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//hXXXX lowpower_internal_cnt(RW) hXXXX lowpower_external_cnt(RW) hXXXX axi2_en_size_lt_width_instr(RW) hXXXX axi1_en_size_lt_width_instr(RW) |
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MC0_CTL_8b0 : .dword 0x0000000000000000 |
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//hXXXX refresh_per_rdlvl(RW) hXXXX lowpower_self_refresh_cnt(RW) hXXXX lowpower_refresh_hold(RW) hXXXX lowpower_power_down_cnt(RW) |
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MC0_CTL_8c0 : .dword 0x0000000000000000 |
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//hXXXX wrlvl_interval(RW) hXXXX tdfi_wrlvl_max(RW) hXXXX tdfi_rdlvl_max(RW) hXXXX refresh_per_rdlvl_gate(RW) |
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//MC0_CTL_8d0 : .dword 0x00000000c8000000 |
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MC0_CTL_8d0 : .dword 0x002faf0800000000 |
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//h00_XXXXXXXX cke_inactive(RW) 000000_000000000000000000 wrlvl_status(RD) |
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MC0_CTL_8e0 : .dword 0x0000000023c34600 |
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//MC0_CTL_8e0 : .dword 0x0000000000000050 |
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//MC0_CTL_8f0 : .dword 0x0000000020202080 |
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MC0_CTL_8f0 : .dword 0x0000000024242480 |
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//h00000000_XXXXXXXX trst_powon(RW) |
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//MC0_CTL_8f0 : .dword 0x0000000020242080 |
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//MC0_CTL_8f0 : .dword 0x000000002b352180 |
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//MC0_CTL_8f0 : .dword 0x0000000030303080 |
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//MC0_CTL_8f0 : .dword 0x0000000030343080 |
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//hXXXXXXX 000_0 XXXXXXXX dll_ctrl_reg_2(RW) |
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MC0_CTL_900 : .dword 0x0000000000000000 |
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//h000000 00_00 X XXXXXXXX rdlvl_error_status(RW) |
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MC0_CTL_910 : .dword 0x0000000000000000 |
|||
//hXXXXXXXX XXXXXXXX rdlvl_gate_resp_mask[63:0](RW) |
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MC0_CTL_920 : .dword 0x0000000000000000 |
|||
//h00000000000000_XX rdlvl_gate_resp_mask[71:64](RW) |
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MC0_CTL_930 : .dword 0x0000000000000000 |
|||
//hXXXXXXXX XXXXXXXX rdlvl_resp_mask[63:0](RW) |
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//MC0_CTL_940 : .dword 0x0007070000050500 |
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MC0_CTL_940 : .dword 0x0006060000050500 |
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//0000_0000 tdfi_rdlvl_en(RW) 00000_000 w2r_samecs_delay(RW) 00000_000 w2r_diffcs_delay(RW) 00000_000 lvl_status(RD) 0000000_0 rdlvl_edge(RW) 0000_0000 cksrx(RW) 0000_0000 cksre(RW) _00000000 rdlvl_resp_mask[71:64](RW) |
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//MC0_CTL_950 : .dword 0x0000000000000a00 |
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MC0_CTL_950 : .dword 0x0000000000001000 |
|||
//hXXXXX 00_00 XXXX mask_int[17:0](RW) hXXXX txpdll(RW) 0000_0000 tdfi_wrlvl_en(RW) |
|||
//MC0_CTL_960 : .dword 0x0705000000000000 |
|||
MC0_CTL_960 : .dword 0x0604000000000000 |
|||
//000_00101 rdlat_adj(RW) 0000_0100 wrlat_adj(RW) 0000000_0 swlvl_start(WR) 0000000_0 swlvl_load(WR) 0000000_0 swlvl_exit(WR) 000000_000000000000000000 int_status(RD) |
|||
MC0_CTL_970 : .dword 0x000000000003e805 |
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//h00000 000_0 XXXX int_ack[16:0](WR) hXXXX dll_rst_delay(RW) hXX dll_rst_adj_dly(RW) |
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@ -0,0 +1,348 @@ |
|||
####################################### |
|||
#define REG_ADDRESS 0x0 |
|||
//#define CONFIG_BASE 0xaff00000 |
|||
//#define CONFIG_BASE 0x900000002ff00000 |
|||
#define CONFIG_BASE 0x900000000ff00000 |
|||
|
|||
|
|||
.global ddr2_config |
|||
.ent ddr2_config |
|||
.set noreorder |
|||
.set mips3 |
|||
ddr2_config: |
|||
dli a0, CONFIG_BASE |
|||
la a2, ddr2_reg_data |
|||
addu a2, a2, s0 |
|||
li t1, 152 |
|||
daddiu v0, a0, 0x0 |
|||
|
|||
reg_write: |
|||
|
|||
ld a1, 0x0(a2) |
|||
sd a1, REG_ADDRESS(v0) |
|||
|
|||
subu t1, t1, 0x1 |
|||
addiu a2, a2, 0x8 |
|||
bne t1, $0, reg_write |
|||
daddiu v0, v0, 0x10 |
|||
|
|||
//#define DEBUG_DDR_MC0 |
|||
#ifdef DEBUG_DDR_MC0 |
|||
/* store the a0,ra */ |
|||
move t8, a0 |
|||
move t1, ra |
|||
|
|||
PRINTSTR("Change some parameters of MC0:"); |
|||
1: |
|||
PRINTSTR("\r\nPlease input the register number you want to change!!!(0:jump out.1~0x97): "); |
|||
li t6, 0x00 |
|||
bal inputaddress #input value stored in v0 |
|||
nop |
|||
move t5, v0 #store v0 to t5 |
|||
|
|||
beqz t5, 2f #if input 0,jump out |
|||
nop |
|||
dsll t5, t5, 4 #t5 is the offset relative to a0 |
|||
daddu t5, t5, t8 |
|||
|
|||
PRINTSTR("\r\nPlease input the data-hex: "); |
|||
li t6, 0x00 |
|||
bal inputaddress #input value stored in v0 |
|||
nop |
|||
sd v0, 0x0(t5) #v0 is the input value |
|||
b 1b |
|||
nop |
|||
2: |
|||
/* recover the a0,ra */ |
|||
move a0, t8 |
|||
move ra, t1 |
|||
#endif |
|||
|
|||
############start########## |
|||
/***** set start to 1,start to initialize SDRAM *****/ |
|||
daddiu v0, a0, 0x0 |
|||
dli a2, 0x0000010000000000 |
|||
ld a1, 0x30(v0) |
|||
or a1, a1, a2 |
|||
sd a1, 0x30(v0) |
|||
|
|||
daddiu v0, a0, 0x960 //wait initialization complete |
|||
1: |
|||
ld a1, 0x0(v0) |
|||
andi a1, a1, 0x100 |
|||
beqz a1, 1b |
|||
nop |
|||
############################### |
|||
|
|||
jr ra |
|||
nop |
|||
.end ddr2_config |
|||
|
|||
.rdata |
|||
.align 5 |
|||
.global ddr2_reg_data |
|||
ddr2_reg_data: |
|||
MC0_CTL_000 : .dword 0x0000010000010101 |
|||
//000000000000000_0 concurrentap(RW) 0000000_1 bank_split_en(RW) 0000000_0 auto_refresh_mode(RW) 0000000_0 arefresh(WR) 0000000_0 ap(RW) 0000000_1 addr_cmp_en(RW) 0000000_1 active_aging(RW) |
|||
MC0_CTL_010 : .dword 0x0000000100010000 |
|||
//0000000_0 fwc(WR) 0000000_0 fast_write(RW) 0000000_1 enable_quick_srefresh(RW) 0000000_1 eight_bank_mode(RW) 0000000_0 ecc_disable_w_uc_err(RW) 0000000_1 dqs_n_en(RW) 0000000_0 dll_bypass_mode(RW) 0000000_0 dlllockreg(RD) |
|||
MC0_CTL_020 : .dword 0x0100010101000000 |
|||
//0000000_1 priority_en(RW) 0000000_0 power_down(RW) 0000000_1 placement_en(RW) 0000000_1 odt_add_turn_clk_en(RW) 0000000_0 no_cmd_init(RW) 0000000_0 intrptwritea(RW) 0000000_0 intrptreada(RW) 0000000_0 intrptapburst(RW) |
|||
MC0_CTL_030 : .dword 0x0001000001000000 |
|||
//0000000_1 swap_port_rw_same_en(RW) 0000000_1 swap_en(RW) 0000000_0 start(RW) 0000000_0 srefresh(RW+) 0000000_1 rw_same_en(RW) 0000000_0 reg_dimm_enable(RW) 0000000_0 reduc(RW) 0000000_0 pwrup_srefresh_exit(RW) |
|||
MC0_CTL_040 : .dword 0x0100010200000100 |
|||
//000000_01 rtt_0(RW) 000000_11 ctrl_raw(RW) 000000_01 axi0_w_priority(RW) 000000_01 axi0_r_priority(RW) 0000000_0 write_modereg(WR) 0000000_1 writeinterp(RW) 0000000_1 tref_enable(RW) 0000000_1 tras_lockout(RW) |
|||
MC0_CTL_050 : .dword 0x0200000004060100 |
|||
//00000_000 q_fullness(RW) 00000_000 port_data_error_type(RD) 000_00000 out_of_range_type(RD) 00000_000 max_cs_reg(RD) 00000_100 column_size(RW) 0000_0101 caslat(RW) 00000_010 addr_pins(RW) 00000000 |
|||
MC0_CTL_060 : .dword 0x0a05030503030003 |
|||
//0000_1010 aprebit(RW) 0000_0101 wrlat(RW) 0000_0100 twtr(RW) 000_00110 twr_int(RW) 00000_011 trtp(RW) 00000_100 trrd(RW) 0000000000000_011 tcke(RW) |
|||
MC0_CTL_070 : .dword 0x0000020000030c0c |
|||
//0000_0000 max_row_reg(RD) 0000_0000 max_col_reg(RD) 0000_0000 initaref(RW) 00000000000000000000_1111 cs_map(RW) 000_01010 caslat_lin_gate(RW) 000_01010 caslat_lin(RW) |
|||
MC0_CTL_080 : .dword 0x0804020108040201 |
|||
//0000_0001 odt_wr_map_cs3(RW) 0000_0010 odt_wr_map_cs2(RW) 0000_0100 odt_wr_map_cs1(RW) 0000_1000 odt_wr_map_cs0(RW) 0000_0001 odt_rd_map_cs3(RW) 0000_0010 odt_rd_map_cs2(RW) 0000_0100 odt_rd_map_cs1(RW) 0000_1000 odt_rd_map_cs0(RW) |
|||
MC0_CTL_090 : .dword 0x0000060c00000000 |
|||
//000_00000 ocd_adjust_pup_cs_0(RW) 000_00000 ocd_adjust_pdn_cs_0(RW) 0000_0101 trp(RW) 000_01011 tdal(RW) 000000000000_0000 port_cmd_error_type(RD) 0000000000000000 |
|||
MC0_CTL_0a0 : .dword 0x0000003f3f18020e |
|||
//00000000000000000000000000_111111 command_age_count(RW) 00_111111 age_count(RW) 000_10100 trc(RW) 000_00110 tmrd(RW) 000_10010 tfaw(RW) |
|||
MC0_CTL_0b0 : .dword 0x0000000000000000 |
|||
MC0_CTL_0c0 : .dword 0x0000330612000000 |
|||
//000000000000000000101100 trfc(RW) 00000101 trcd_int(RW) 00001111 tras_min(RW) 00000000 out_of_range_length(RD) 00000000 ecc_u_synd(RD) 00000000 ecc_c_synd(RD) |
|||
MC0_CTL_0d0 : .dword 0x0000000000000000 |
|||
MC0_CTL_0e0 : .dword 0x0000000000000000 |
|||
MC0_CTL_0f0 : .dword 0x0000000000000000 |
|||
//Bit 21:16 dll_lock(RD) |
|||
MC0_CTL_100 : .dword 0x0000000000000000 |
|||
MC0_CTL_110 : .dword 0x0000000000000300 #100M+ |
|||
//MC0_CTL_110 : .dword 0x0000000000000618 #200M+ |
|||
//MC0_CTL_110 : .dword 0x0000000000000924 #300M+ |
|||
//MC0_CTL_110 : .dword 0x0000000000000c30 #400M |
|||
//0_000000000000000 emrs2_data_1(RW) 0_000000000000000 emrs2_data_0(RW) 000000000000000000_00110000101101 tref(RW) |
|||
MC0_CTL_120 : .dword 0xffff000000000000 |
|||
//0000000000011100 axi0_en_size_lt_width_instr(RW) 00000000000000000_000000000000000 emrs2_data_3(RW) 0_000000000000000 emrs2_data_2(RW) |
|||
MC0_CTL_130 : .dword 0x1a00000202000000 #100M+ |
|||
//MC0_CTL_130 : .dword 0x36b0000202000000 #200M+ |
|||
//MC0_CTL_130 : .dword 0x51f0000202000000 #300M+ |
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//MC0_CTL_130 : .dword 0x6d60000202000000 #400M |
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//0110110101010110 tras_max(RW) 0000000000000011 tpdex(RW) 0000001000000000 tdll(RW) 0000000000000000 tcpd(RW) |
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MC0_CTL_140 : .dword 0x0000204000c80037 |
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//0000000000000000 xor_check_bits(RW) 0000000000000000 version(RD) 0000001000000000 txsr(RW) 0000000000110000 txsnr(RW) |
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MC0_CTL_150 : .dword 0x0000000000020000 |
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//000_0000000000000000000000000000000000000 ecc_c_addr(RD) 000000000000000000011011 tinit(RW) |
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MC0_CTL_160 : .dword 0x0000000000000000 |
|||
//000000000000000000000000000_0000000000000000000000000000000000000 ecc_u_addr(RD) |
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MC0_CTL_170 : .dword 0x0000000000000000 |
|||
//000000000000000000000000000_0000000000000000000000000000000000000 out_of_range_addr(RD) |
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MC0_CTL_180 : .dword 0x0000000000000000 |
|||
//000000000000000000000000000_0000000000000000000000000000000000000 port_cmd_error_addr(RD) |
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MC0_CTL_190 : .dword 0x0000000000000000 |
|||
//0000000000000000000000000000000000000000000000000000000000000000 ecc_c_data(RD) |
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MC0_CTL_1a0 : .dword 0x0000000000000000 |
|||
//0000000000000000000000000000000000000000000000000000000000000000 ecc_u_data(RD) |
|||
MC0_CTL_1b0 : .dword 0x0000000000000000 |
|||
//0000000000000000000000000000000000000000000000000000000000000_000 cke_delay(RW) |
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MC0_CTL_1c0 : .dword 0x0000000000000000 |
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MC0_CTL_1d0 : .dword 0x0200070000000001 |
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//0000_0010 tdfi_phy_wrlat_base(RW) 0000_0000 tdfi_phy_wrlat(RD) 000_00111 tdfi_phy_rdlat(RW) 0000_0000 tdfi_ctrlupd_min(RD) 000000000000_0000 dram_clk_disable(RW) 0000000_1 odt_alt_en(RW) 0000000_1 drive_dq_dqs(RW) |
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MC0_CTL_1e0 : .dword 0x0000000000000200 |
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//00_00000000000000 tdfi_phyupd_type0(RD) 00_00000000000000 tdfi_phyupd_resp(RD) 00_00000000000000 tdfi_ctrlupd_max(RD) 000_00000 tdfi_rddata_en_base(RW) 000_00000 tdfi_rddata_en(RD) |
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|
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/******** |
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MC0_CTL_1f0 : .dword 0x0020208000000000 |
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MC0_CTL_200 : .dword 0x0020208000202080 |
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MC0_CTL_210 : .dword 0x0020208000202080 |
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MC0_CTL_220 : .dword 0x0020208000202080 |
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MC0_CTL_230 : .dword 0x0020208000202080 |
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|
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MC0_CTL_240 : .dword 0x00000e0000000e00 |
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MC0_CTL_250 : .dword 0x00000e0000000e00 |
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MC0_CTL_260 : .dword 0x00000e0000000e00 |
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MC0_CTL_270 : .dword 0x00000e0000000e00 |
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MC0_CTL_280 : .dword 0x0000000000000e00 |
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**********/ |
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MC0_CTL_1f0 : .dword 0x0014148000000000 |
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//hXXXXXXXX dll_ctrl_reg_0_0(RW) h000000 hXX dft_ctrl_reg(RW) |
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MC0_CTL_200 : .dword 0x0014148000141480 |
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MC0_CTL_210 : .dword 0x0014148000141480 |
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MC0_CTL_220 : .dword 0x0014148000141480 |
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MC0_CTL_230 : .dword 0x0014148000141480 |
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//00000000001000000000111510000000 dll_ctrl_reg_0_8(RW) 00000000001000000000111010000000 dll_ctrl_reg_0_7(RW) |
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MC0_CTL_240 : .dword 0x0000140000001400 |
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MC0_CTL_250 : .dword 0x0000140000001400 |
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MC0_CTL_260 : .dword 0x0000140000001400 |
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MC0_CTL_270 : .dword 0x0000140000001400 |
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MC0_CTL_280 : .dword 0x0000000000001400 |
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//hXXXXXXX 00_00 dll_obs_reg_0_0(RW) 00000000000000000000111000000000 dll_ctrl_reg_1_8(RW) |
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MC0_CTL_290 : .dword 0x0000000000000000 |
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//hXXXXXXX 00_00 dll_obs_reg_0_2(RW) hXXXXXXX 00_00 dll_obs_reg_0_1(RW) |
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MC0_CTL_2a0 : .dword 0x0000000000000000 |
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//hXXXXXXX 00_00 dll_obs_reg_0_4(RW) hXXXXXXX 00_00 dll_obs_reg_0_3(RW) |
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MC0_CTL_2b0 : .dword 0x0000000000000000 |
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//hXXXXXXX 00_00 dll_obs_reg_0_6(RW) hXXXXXXX 00_00 dll_obs_reg_0_5(RW) |
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MC0_CTL_2c0 : .dword 0x0000000000000000 |
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//hXXXXXXX 00_00 dll_obs_reg_0_8(RW) hXXXXXXX 00_00 dll_obs_reg_0_7(RW) |
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//MC0_CTL_2d0 : .dword 0xf300494603c0019d |
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MC0_CTL_2d0 : .dword 0xc400484403fc09b4 |
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//11110100000000000011101100100111 phy_ctrl_reg_0_0(RD) 000000_00000000000000000110011101 pad_ctrl_reg_0(RW) |
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MC0_CTL_2e0 : .dword 0xc4004844c4004844 |
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MC0_CTL_2f0 : .dword 0xc4004844c4004844 |
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MC0_CTL_300 : .dword 0xc4004844c4004844 |
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MC0_CTL_310 : .dword 0xc4004844c4004844 |
|||
/******** |
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MC0_CTL_2d0 : .dword 0x1300483303c009b4 |
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//11110100000000000011101100100111 phy_ctrl_reg_0_0(RD) 000000_00000000000000000110011101 pad_ctrl_reg_0(RW) |
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MC0_CTL_2e0 : .dword 0x1300483313004833 |
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MC0_CTL_2f0 : .dword 0x1300483313004833 |
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MC0_CTL_300 : .dword 0x1300483313004833 |
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MC0_CTL_310 : .dword 0x1300483313004833 |
|||
**********/ |
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MC0_CTL_320 : .dword 0x26c0000126c00001 |
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MC0_CTL_330 : .dword 0x26c0000126c00001 |
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MC0_CTL_340 : .dword 0x26c0000126c00001 |
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MC0_CTL_350 : .dword 0x26c0000126c00001 |
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MC0_CTL_360 : .dword 0x0800e00526c00001 |
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//00000000000000001100000000000101 phy_ctrl_reg_2(RW) 00000111110000000000001100000001 phy_ctrl_reg_1_8(RD) |
|||
//-------------- |
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MC0_CTL_370 : .dword 0x0000000000000000 |
|||
MC0_CTL_380 : .dword 0x0000000000000000 |
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MC0_CTL_390 : .dword 0x0000000000000000 |
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MC0_CTL_3a0 : .dword 0x0000000000000000 |
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MC0_CTL_3b0 : .dword 0x0000000000000000 |
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MC0_CTL_3c0 : .dword 0x0000000000000000 |
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MC0_CTL_3d0 : .dword 0x0000000000000000 |
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MC0_CTL_3e0 : .dword 0x0000000000000000 |
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MC0_CTL_3f0 : .dword 0x0000000000000000 |
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MC0_CTL_400 : .dword 0x0000000000000000 |
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MC0_CTL_410 : .dword 0x0000000000000000 |
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MC0_CTL_420 : .dword 0x0000000000000000 |
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MC0_CTL_430 : .dword 0x0000000000000000 |
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MC0_CTL_440 : .dword 0x0000000000000000 |
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MC0_CTL_450 : .dword 0x0000000000000000 |
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MC0_CTL_460 : .dword 0x0000000000000000 |
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MC0_CTL_470 : .dword 0x0000000000000000 |
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MC0_CTL_480 : .dword 0x0000000000000000 |
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MC0_CTL_490 : .dword 0x0000000000000000 |
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MC0_CTL_4a0 : .dword 0x0000000000000000 |
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MC0_CTL_4b0 : .dword 0x0000000000000000 |
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MC0_CTL_4c0 : .dword 0x0000000000000000 |
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MC0_CTL_4d0 : .dword 0x0000000000000000 |
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MC0_CTL_4e0 : .dword 0x0000000000000000 |
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MC0_CTL_4f0 : .dword 0x0000000000000000 |
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MC0_CTL_500 : .dword 0x0000000000000000 |
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MC0_CTL_510 : .dword 0x0000000000000000 |
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MC0_CTL_520 : .dword 0x0000000000000000 |
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MC0_CTL_530 : .dword 0x0000000000000000 |
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MC0_CTL_540 : .dword 0x0000000000000000 |
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MC0_CTL_550 : .dword 0x0000000000000000 |
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MC0_CTL_560 : .dword 0x0000000000000000 |
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MC0_CTL_570 : .dword 0x0000000000000000 |
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MC0_CTL_580 : .dword 0x0000000000000000 |
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MC0_CTL_590 : .dword 0x0000000000000000 |
|||
MC0_CTL_5a0 : .dword 0x0000000000000000 |
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MC0_CTL_5b0 : .dword 0x0000000000000000 |
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MC0_CTL_5c0 : .dword 0x0000000000000000 |
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MC0_CTL_5d0 : .dword 0x0000000000000000 |
|||
MC0_CTL_5e0 : .dword 0x0000000000000000 |
|||
MC0_CTL_5f0 : .dword 0x0000000000000000 |
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MC0_CTL_600 : .dword 0x0000000000000000 |
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MC0_CTL_610 : .dword 0x0000000000000000 |
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MC0_CTL_620 : .dword 0x0000000000000000 |
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MC0_CTL_630 : .dword 0x0000000000000000 |
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MC0_CTL_640 : .dword 0x0000000000000000 |
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MC0_CTL_650 : .dword 0x0000000000000000 |
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MC0_CTL_660 : .dword 0x0000000000000000 |
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MC0_CTL_670 : .dword 0x0000000000000000 |
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MC0_CTL_680 : .dword 0x0000000000000000 |
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MC0_CTL_690 : .dword 0x0000000000000000 |
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MC0_CTL_6a0 : .dword 0x0000000000000000 |
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MC0_CTL_6b0 : .dword 0x0000000000000000 |
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MC0_CTL_6c0 : .dword 0x0000000000000000 |
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MC0_CTL_6d0 : .dword 0x0000000000000000 |
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MC0_CTL_6e0 : .dword 0x0000000000000000 |
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MC0_CTL_6f0 : .dword 0x0000000000000000 |
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MC0_CTL_700 : .dword 0x0000000000000000 |
|||
//------------- |
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MC0_CTL_710 : .dword 0x0000000000000000 |
|||
//bit 48 en_wr_leveling(RW) |
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MC0_CTL_720 : .dword 0x0000000000000000 |
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//0000000_0 rdlvl_gate_req(WR) 0000000_0 rdlvl_gate_preamble_check_en(RW) 0000000_0 rdlvl_gate_en(RW) 0000000_0 rdlvl_en(RW) 0000000_0 rdlvl_begin_delay_en(RW) 00000000 00000000 0000000_0 swlvl_op_done(RD) |
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MC0_CTL_730 : .dword 0x0000000000000000 |
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//0000000_0 rdlvl_offset_dir_7(RW) 0000000_0 rdlvl_offset_dir_6(RW) 0000000_0 rdlvl_offset_dir_5(RW)0000000_0 rdlvl_offset_dir_4(RW) 0000000_0 rdlvl_offset_dir_3(RW) 0000000_0 rdlvl_offset_dir_2(RW) 0000000_0 rdlvl_offset_dir_1(RW) 0000000_0 rdlvl_offset_dir_0(RW) |
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MC0_CTL_740 : .dword 0x0100000000000000 |
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//000000_00 axi1_port_ordering(RW) 000000_00 axi0_port_ordering(RW) 0000000_0 wrlvl_req(WR) 0000000_0 wrlvl_interval_ct_en(RW) 0000000_0 weight_round_robin_weight_sharing(RW) 0000000_0 weight_round_robin_latency_control 0000000_0(RW) rdlvl_req 0000000_0(WR) rdlvl_offset_dir_8(RW) |
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MC0_CTL_750 : .dword 0x0000000101020101 |
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//000000_01 wrlvl_cs(RW) 000000_00 sw_leveling_mode(RW) 000000_00 rdlvl_cs(RW) 000000_01 axi2_w_priority(RW) 000000_01 axi2_r_priority(RW) 000000_10 axi2_port_ordering(RW) 000000_01 axi1_w_priority(RW) 000000_01 axi1_r_priority(RW) |
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MC0_CTL_760 : .dword 0x0303030000020000 |
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//0000_0011 axi0_priority2_relative_priority(RW) 0000_0011 axi0_priority1_relative_priority(RW) 0000_0011 axi0_priority0_relative_priority(RW) 0000_0000 address_mirroring(RW) 00000_000 tdfi_dram_clk_disable(RW) 00000_010 bstlen(RW) 000000_00 zq_req(WR) 000000_01 zq_on_sref_exit(RW) |
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MC0_CTL_770 : .dword 0x0101010202020203 |
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//0000_0001 axi2_priority2_relative_priority(RW) 0000_0001 axi2_priority1_relative_priority(RW) 0000_0001 axi2_priority0_relative_priority(RW) 0000_0010 axi1_priority3_relative_priority(RW) 0000_0010 axi1_priority2_relative_priority(RW) 0000_0010 axi1_priority1_relative_priority(RW) 0000_0010 axi1_priority0_relative_priority(RW) 0000_0011 axi0_priority3_relative_priority(RW) |
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MC0_CTL_780 : .dword 0x0102000000040001 |
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//0000_0001 tdfi_dram_clk_enable(RW) 0000_0010 tdfi_ctrl_delay(RW) 0000_0010 rdlvl_gate_dq_zero_count(RW) 0000_0100 rdlvl_dq_zero_count(RW) 0000_0000 lowpower_refresh_enable(RW) 0000_0110 dram_class(RW) 0000_1100 burst_on_fly_bit(RW) 0000_0001 axi2_priority3_relative_priority(RW) |
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MC0_CTL_790 : .dword 0x0000000000000000 |
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//00_101000 wlmrd(RW) 00_011001 wldqsen(RW) 000_00000 lowpower_control(RW) 000_00000 lowpower_auto_enable(RW) 0000_1111 zqcs_chip(RW) 0000_0000 wrr_param_value_err(RD) 0000_0011 tdfi_wrlvl_dll(RW) 0000_0011 tdfi_rdlvl_dll(RW) |
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MC0_CTL_7a0 : .dword 0x0000000000000000 |
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//_00000000 swlvl_resp_6(RW) _00000000 swlvl_resp_5(RW) _00000000 swlvl_resp_4 _00000000 swlvl_resp_3(RW) _00000000 swlvl_resp_2(RW) _00000000 swlvl_resp_1(RW) _00000000 swlvl_resp_0(RW) _00000000 dfi_wrlvl_max_delay(RW) |
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MC0_CTL_7b0 : .dword 0x0000000000000000 |
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//_00000000 rdlvl_begin_delay_5(RW) _00000000 rdlvl_begin_delay_4(RW) _00000000 rdlvl_begin_delay_3(RW) _00000000 rdlvl_begin_delay_2(RW) _00000000 rdlvl_begin_delay_1(RW) _00000000 rdlvl_begin_delay_0(RW) _00000000 swlvl_resp_8(RW) _00000000 swlvl_resp_7(RW) |
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MC0_CTL_7c0 : .dword 0x0000000000000000 |
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//_00000000 rdlvl_end_delay_4(RW) _00000000 rdlvl_end_delay_3(RW) _00000000 rdlvl_end_delay_2(RW) _00000000 rdlvl_end_delay_1(RW) _00000000 rdlvl_end_delay_0(RW) _00000000 rdlvl_begin_delay_8(RW) _00000000 rdlvl_begin_delay_7(RW) _00000000 rdlvl_begin_delay_6(RW) |
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MC0_CTL_7d0 : .dword 0x0000000000000000 |
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//_00000000 rdlvl_gate_clk_adjust_3(RW) _00000000 rdlvl_gate_clk_adjust_2(RW) _00000000 rdlvl_gate_clk_adjust_1(RW) _00000000 rdlvl_gate_clk_adjust_0(RW) _00000000 rdlvl_end_delay_8(RW) _00000000 rdlvl_end_delay_7(RW) _00000000 rdlvl_end_delay_6(RW) 00000000 rdlvl_end_delay_5(RW) |
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MC0_CTL_7e0 : .dword 0x0000000000000000 |
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//00000000 rdlvl_gate_delay_2(RD) 00000000 rdlvl_gate_delay_1(RD) 00000000 rdlvl_gate_delay_0(RD) 00000000 rdlvl_gate_clk_adjust_8(RW) 00000000 rdlvl_gate_clk_adjust_7(RW) 00000000 rdlvl_gate_clk_adjust_6(RW) 00000000 rdlvl_gate_clk_adjust_5(RW) 00000000 rdlvl_gate_clk_adjust_4(RW) |
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MC0_CTL_7f0 : .dword 0x0000000000000000 |
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//11111111 rdlvl_max_delay(RW) 00001000 rdlvl_gate_max_delay(RW) 00000000 rdlvl_gate_delay_8(RD) 00000000 rdlvl_gate_delay_7(RD) 00000000 rdlvl_gate_delay_6(RD) 00000000 rdlvl_gate_delay_5(RD) 00000000 rdlvl_gate_delay_4(RD) 00000000 rdlvl_gate_delay_3(RD) |
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MC0_CTL_800 : .dword 0x0000000000000000 |
|||
//00000000 rdlvl_midpoint_delay_7(RD) 00000000 rdlvl_midpoint_delay_6(RD) 00000000 rdlvl_midpoint_delay_5(RD) 00000000 rdlvl_midpoint_delay_4(RD) 00000000 rdlvl_midpoint_delay_3(RD) 00000000 rdlvl_midpoint_delay_2(RD) 00000000 rdlvl_midpoint_delay_1(RD) 00000000 rdlvl_midpoint_delay_0(RD) |
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MC0_CTL_810 : .dword 0x0000000000000000 |
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//00000000 rdlvl_offset_delay_6(RW) 00000000 rdlvl_offset_delay_5(RW) 00000000 rdlvl_offset_delay_4(RW) 00000000 rdlvl_offset_delay_3(RW) 00000000 rdlvl_offset_delay_2(RW) 00000000 rdlvl_offset_delay_1(RW) 00000000 rdlvl_offset_delay_0(RW) 00000000 rdlvl_midpoint_delay_8(RD) |
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MC0_CTL_820 : .dword 0x0000000000000000 |
|||
//00000100 tdfi_wrlvl_resplat(RW) 00000000 tdfi_wrlvl_resp(RD) 00000000 tdfi_rdlvl_rr(RW) 00001100 tdfi_rdlvl_resplat(RW) 00000000 tdfi_rdlvl_resp(RD) 01000000 refresh_per_zq(RW) 00000000 rdlvl_offset_delay_8(RW) 00000000 rdlvl_offset_delay_7(RW) |
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//MC0_CTL_830 : .dword 0x000000000000020a |
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MC0_CTL_830 : .dword 0x1c24241c1c1c0c0a |
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//MC0_CTL_830 : .dword 0x40444b474543020a |
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//00000000 wrlvl_delay_5(RD) 00000000 wrlvl_delay_4(RD) 00000000 wrlvl_delay_3(RD) 00000000 wrlvl_delay_2(RD) 00000000 wrlvl_delay_1(RD) 00000000 wrlvl_delay_0(RD) 00000010 tmod(RW) 00001010 tdfi_wrlvl_ww(RW) |
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//MC0_CTL_840 : .dword 0x0000640064000000 |
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MC0_CTL_840 : .dword 0x0000640064001c1c |
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//MC0_CTL_840 : .dword 0x0000640064003b3c |
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//00000000000000_0001100100 axi1_priority_relax(RW) 000000_0001100100 axi0_priority_relax(RW) 00000000 wrlvl_delay_8(RD) 00000000 wrlvl_delay_7(RD) 00000000 wrlvl_delay_6(RD) |
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MC0_CTL_850 : .dword 0x0000000000000064 |
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//000000_0000000000 out_of_range_source_id(RD) 000000_0000000000 ecc_u_id(RD) 000000_0000000000 ecc_c_id(RD) 000000_0000000000 axi2_priority_relax(RW) |
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MC0_CTL_860 : .dword 0x0000000000000000 |
|||
//0000_000000000000 zqini(RW) 0000_000000000000 zqcs(RW) 000000_0000000000 port_data_error_id(RD) 000000_0000000000 port_cmd_error_id(RD) |
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MC0_CTL_870 : .dword 0x0046004600460046 |
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//0_000000000000010 emrs1_data_3(RW) 0_000000000000010 emrs1_data_2(RW) 0_000000000000010 emrs1_data_1(RW) 0_000000000000010 emrs1_data_0(RW) |
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MC0_CTL_880 : .dword 0x0000000000000000 |
|||
//0_000000000000010 emrs3_data_3(RW) 0_000000000000010 emrs3_data_2(RW) 0_000000000000010 emrs3_data_1(RW) 0_000000000000010 emrs3_data_0(RW) |
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MC0_CTL_890 : .dword 0x0a620a620a620a62 |
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//0_000010000010000 mrs_data_3(RW) 0_000010000010000 mrs_data_2(RW) 0_000010000010000 mrs_data_1(RW) 0_000010000010000 mrs_data_0(RW) |
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MC0_CTL_8a0 : .dword 0x00000000001c001c |
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//hXXXX lowpower_internal_cnt(RW) hXXXX lowpower_external_cnt(RW) hXXXX axi2_en_size_lt_width_instr(RW) hXXXX axi1_en_size_lt_width_instr(RW) |
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MC0_CTL_8b0 : .dword 0x0000000000000000 |
|||
//hXXXX refresh_per_rdlvl(RW) hXXXX lowpower_self_refresh_cnt(RW) hXXXX lowpower_refresh_hold(RW) hXXXX lowpower_power_down_cnt(RW) |
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MC0_CTL_8c0 : .dword 0x0000000000000000 |
|||
//hXXXX wrlvl_interval(RW) hXXXX tdfi_wrlvl_max(RW) hXXXX tdfi_rdlvl_max(RW) hXXXX refresh_per_rdlvl_gate(RW) |
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MC0_CTL_8d0 : .dword 0x00000000c8000000 |
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//h00_XXXXXXXX cke_inactive(RW) 000000_000000000000000000 wrlvl_status(RD) |
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MC0_CTL_8e0 : .dword 0x0000000000000050 |
|||
//h00000000_XXXXXXXX trst_powon(RW) |
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//MC0_CTL_8f0 : .dword 0x0000000020242080 |
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//MC0_CTL_8f0 : .dword 0x000000002b352180 |
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MC0_CTL_8f0 : .dword 0x0000000030303080 |
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//MC0_CTL_8f0 : .dword 0x0000000030343080 |
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//hXXXXXXX 000_0 XXXXXXXX dll_ctrl_reg_2(RW) |
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MC0_CTL_900 : .dword 0x0000000000000000 |
|||
//h000000 00_00 X XXXXXXXX rdlvl_error_status(RW) |
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MC0_CTL_910 : .dword 0x0000000000000000 |
|||
//hXXXXXXXX XXXXXXXX rdlvl_gate_resp_mask[63:0](RW) |
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MC0_CTL_920 : .dword 0x0000000000000000 |
|||
//h00000000000000_XX rdlvl_gate_resp_mask[71:64](RW) |
|||
MC0_CTL_930 : .dword 0x0000000000000000 |
|||
//hXXXXXXXX XXXXXXXX rdlvl_resp_mask[63:0](RW) |
|||
MC0_CTL_940 : .dword 0x0007070000050500 |
|||
//0000_0000 tdfi_rdlvl_en(RW) 00000_000 w2r_samecs_delay(RW) 00000_000 w2r_diffcs_delay(RW) 00000_000 lvl_status(RD) 0000000_0 rdlvl_edge(RW) 0000_0000 cksrx(RW) 0000_0000 cksre(RW) _00000000 rdlvl_resp_mask[71:64](RW) |
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MC0_CTL_950 : .dword 0x0000000000000a00 |
|||
//hXXXXX 00_00 XXXX mask_int[17:0](RW) hXXXX txpdll(RW) 0000_0000 tdfi_wrlvl_en(RW) |
|||
MC0_CTL_960 : .dword 0x0705000000000000 |
|||
//000_00101 rdlat_adj(RW) 0000_0100 wrlat_adj(RW) 0000000_0 swlvl_start(WR) 0000000_0 swlvl_load(WR) 0000000_0 swlvl_exit(WR) 000000_000000000000000000 int_status(RD) |
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MC0_CTL_970 : .dword 0x000000000003e805 |
|||
//h00000 000_0 XXXX int_ack[16:0](WR) hXXXX dll_rst_delay(RW) hXX dll_rst_adj_dly(RW) |
|||
@ -0,0 +1,451 @@ |
|||
#define CP0_HWRENA $7 |
|||
|
|||
#.align 7 /* bfc00480 */ |
|||
//////////////////////////////////////////// |
|||
/* only concern mem copy in bios now */ |
|||
/* used below addres to simulate virtual EJTAG registers */ |
|||
/* for DUMP ALL registers and restore context */ |
|||
/* COMMON USED REGISTERS */ |
|||
#define EJTAG_V0 0xff200000 |
|||
#define EJTAG_V1 0xff200008 |
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#define EJTAG_A0 0xff200010 |
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#define EJTAG_A1 0xff200018 |
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#define EJTAG_A2 0xff200020 |
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#define EJTAG_A3 0xff200028 |
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#define EJTAG_T0 0xff200030 |
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#define EJTAG_T1 0xff200038 |
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#define EJTAG_T2 0xff200040 |
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#define EJTAG_T3 0xff200048 |
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#define EJTAG_T4 0xff200050 |
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#define EJTAG_T5 0xff200058 |
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#define EJTAG_T6 0xff200060 |
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#define EJTAG_T7 0xff200068 |
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#define EJTAG_T8 0xff200070 |
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#define EJTAG_T9 0xff200078 |
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#define EJTAG_S0 0xff200080 |
|||
#define EJTAG_S1 0xff200088 |
|||
#define EJTAG_S2 0xff200090 |
|||
#define EJTAG_S3 0xff200098 |
|||
#define EJTAG_S4 0xff2000a0 |
|||
#define EJTAG_S5 0xff2000a8 |
|||
#define EJTAG_S6 0xff2000b0 |
|||
#define EJTAG_S7 0xff2000b8 |
|||
#define EJTAG_K0 0xff2000c0 |
|||
#define EJTAG_K1 0xff2000c8 |
|||
#define EJTAG_GP 0xff2000d0 |
|||
#define EJTAG_SP 0xff2000d8 |
|||
#define EJTAG_FP 0xff2000e0 |
|||
#define EJTAG_RA 0xff2000e8 |
|||
|
|||
/* CP0 registers */ |
|||
#define EJTAG_INDEX 0xff200100 |
|||
#define EJTAG_RANDOM 0xff200108 |
|||
#define EJTAG_ENTRYLO0 0xff200110 |
|||
#define EJTAG_ENTRYLO1 0xff200118 |
|||
#define EJTAG_CONTEXT 0xff200120 |
|||
#define EJTAG_PAGEMASK 0xff200128 |
|||
#define EJTAG_WIRED 0xff200130 |
|||
#define EJTAG_HWRENA 0xff200138 |
|||
#define EJTAG_BADVADDR 0xff200140 |
|||
#define EJTAG_COUNT 0xff200148 |
|||
#define EJTAG_ENTRYHI 0xff200150 |
|||
#define EJTAG_COMPARE 0xff200158 |
|||
#define EJTAG_STATUS 0xff200160 |
|||
#define EJTAG_CAUSE 0xff200168 |
|||
#define EJTAG_EPC 0xff200170 |
|||
#define EJTAG_PRID 0xff200178 |
|||
#define EJTAG_CONFIG 0xff200180 |
|||
#define EJTAG_CONFIG1 0xff200188 |
|||
#define EJTAG_CONFIG2 0xff200190 |
|||
#define EJTAG_LLADDR 0xff200198 |
|||
#define EJTAG_WATCHLO 0xff2001a0 |
|||
#define EJTAG_WATCHHI 0xff2001a8 |
|||
#define EJTAG_XCONTEXT 0xff2001b0 |
|||
#define EJTAG_DEPC 0xff2001b8 |
|||
#define EJTAG_ERROREPC 0xff2001c0 |
|||
#define EJTAG_DESAVE 0xff2001c8 |
|||
|
|||
#define DUMPREGS_START EJTAG_V0 |
|||
#define DUMPREGS_END EJTAG_DESAVE |
|||
#define CONTEXT_REGCNT 10 |
|||
#define REGS_TATOAL 47 |
|||
#define DUMP_CNT (REGS_TATOAL - CONTEXT_REGCNT) |
|||
|
|||
|
|||
/* for memory access */ |
|||
#define STATUSREG 0xff200200 /* identify wheter begin to start bios copying */ |
|||
#define ADDRREG 0xff200208 /* address to access memory or CP0 index */ |
|||
#define DATAREG 0xff200210 /* value to sotre to mem or move to CP0 */ |
|||
#define LENGREG 0xff200218 /* length of memory to access */ |
|||
#define TYPEREG 0xff200220 /* type for access mem or CP0 */ |
|||
#define DBGREG 0xff200228 /* get data during DBG modle */ |
|||
#define TLBENREG 0xff200230 /* identify wheterh use TLB */ |
|||
#define CMDCNTREG 0xff200238 /* identify wheter begin to start bios copying */ |
|||
#define EPCREG 0xff200240 /* identify wheter begin to start bios copying */ |
|||
|
|||
|
|||
#define CP0_DESAVE $31 |
|||
|
|||
//#define CONTEXTREG 0xff200000 |
|||
#define CONTEXTREG EJTAG_T0 |
|||
#define STATUSREG 0xff200200 /* identify wheter begin to start bios copying */ |
|||
#define ADDRREG 0xff200208 /* address to access memory or CP0 index */ |
|||
#define DATAREG 0xff200210 /* value to sotre to mem or move to CP0 */ |
|||
#define LENGREG 0xff200218 /* length of memory to access */ |
|||
#define TYPEREG 0xff200220 /* type for access mem or CP0 */ |
|||
#define DBGREG 0xff200228 /* type for access mem or CP0 */ |
|||
#define TLBENREG 0xff200230 /* identify whether enabel TLB DUMP */ |
|||
#define CMDCNTREG 0xff200238 /* cmd counter */ |
|||
#define EPCREG 0xff200240 /* cmd counter */ |
|||
|
|||
//#define BIOS_ENTRY 0xa1000000 /* cmd counter */ |
|||
#define BIOS_ENTRY 0x80010000 /* cmd counter */ |
|||
|
|||
/* below is memory accessint tyep */ |
|||
#define LDDW 0x3 |
|||
#define LDW 0x2 |
|||
#define STDW 0xb |
|||
#define STW 0xa |
|||
#define DUMPREGS 0x0f |
|||
#define ERET 0xf0 |
|||
|
|||
#define DEBUG //it seems has bug here, because cpu stop if not in DEBUG |
|||
|
|||
.set mips64 |
|||
// save context |
|||
dmtc0 t0, CP0_DESAVE |
|||
li t0, CONTEXTREG |
|||
sd t1, 0x08(t0) |
|||
sd t2, 0x10(t0) |
|||
sd t3, 0x18(t0) |
|||
sd t4, 0x20(t0) |
|||
sd t5, 0x28(t0) |
|||
sd t6, 0x30(t0) |
|||
sd t7, 0x38(t0) |
|||
dmfc0 t1, CP0_STATUS |
|||
li t0, EJTAG_STATUS |
|||
sd t1, 0x00(t0) |
|||
li t0, EJTAG_CONFIG |
|||
dmfc0 t1, CP0_CONFIG |
|||
sd t1, 0x00(t0) |
|||
li t0, EJTAG_CAUSE |
|||
dmfc0 t1, CP0_CAUSE |
|||
sd t1, 0x00(t0) |
|||
|
|||
li t0, TLBENREG |
|||
ld t1, 0x0(t0) |
|||
beqz t1, tlbdump_end |
|||
nop |
|||
tlbdump_end: |
|||
|
|||
/* t6 used as cmd counter */ |
|||
li t6,0x0 |
|||
|
|||
/* t7: get cmds total number to execute */ |
|||
li t0, STATUSREG |
|||
ld t7, 0x0(t0) |
|||
#ifdef DEBUG |
|||
li t0, DBGREG |
|||
sd t7, 0x0(t0) |
|||
#endif |
|||
beqz t7, 12f |
|||
nop |
|||
|
|||
11: |
|||
/* get cmds type */ |
|||
li t0, TYPEREG |
|||
ld t1, 0x0(t0) |
|||
#ifdef DEBUG |
|||
li t0, DBGREG |
|||
sd t1, 0x0(t0) |
|||
#endif |
|||
|
|||
/* check whether current cmds is "eret" */ |
|||
bne t1,ERET, 15f |
|||
nop |
|||
li t0, EPCREG |
|||
//lw t2, 0x0(t0) |
|||
ld t2, 0x0(t0) |
|||
//dmtc0 t2,CP0_DEXC_PC |
|||
dmtc0 t2, CP0_DEPC |
|||
|
|||
/* should avoid this because C client doesn't support */ |
|||
##ifdef DEBUG |
|||
# li t0, DBGREG |
|||
# sw t2, 0x0(t0) |
|||
##endif |
|||
#li t2,BIOS_ENTRY |
|||
// to check whether this cmds and below nop lead PC dead !!! |
|||
|
|||
#if 1 |
|||
#.set at |
|||
#.set push |
|||
#.set mips3 |
|||
#eret |
|||
#.set pop |
|||
#.set noreorder |
|||
#.set volatile |
|||
nop |
|||
// now not used jump |
|||
li t0, CONTEXTREG |
|||
ld t1, 0x08(t0) |
|||
ld t2, 0x10(t0) |
|||
ld t3, 0x18(t0) |
|||
ld t4, 0x20(t0) |
|||
ld t5, 0x28(t0) |
|||
ld t6, 0x30(t0) |
|||
ld t7, 0x38(t0) |
|||
#mtc0 t8, CP0_STATUS_REG |
|||
#ld t8, 0x48(t0) |
|||
#mtc0 t8, CP0_CONFIG |
|||
#ld t8, 0x50(t0) |
|||
#mtc0 t8, CP0_CAUSE_REG |
|||
dmfc0 t0, CP0_DESAVE |
|||
|
|||
#mtc0 t2,CP0_EXC_PC |
|||
.set mips64 |
|||
deret |
|||
.set mips3 |
|||
nop |
|||
nop |
|||
#endif |
|||
|
|||
#b 12f |
|||
#nop |
|||
|
|||
15: |
|||
/* first check whether local instruction is to dump registers */ |
|||
bne t1, DUMPREGS, 16f |
|||
nop |
|||
li t0, EJTAG_V0 |
|||
sd v0, 0x0(t0) |
|||
li t0, EJTAG_V1 |
|||
sd v1, 0x0(t0) |
|||
li t0, EJTAG_A0 |
|||
sd a0, 0x0(t0) |
|||
li t0, EJTAG_A1 |
|||
sd a1, 0x0(t0) |
|||
li t0, EJTAG_A2 |
|||
sd a2, 0x0(t0) |
|||
li t0, EJTAG_A3 |
|||
sd a3, 0x0(t0) |
|||
li t0, EJTAG_S0 |
|||
sd s0, 0x0(t0) |
|||
li t0, EJTAG_S1 |
|||
sd s1, 0x0(t0) |
|||
li t0, EJTAG_S2 |
|||
sd s2, 0x0(t0) |
|||
li t0, EJTAG_S3 |
|||
sd s3, 0x0(t0) |
|||
li t0, EJTAG_S4 |
|||
sd s4, 0x0(t0) |
|||
li t0, EJTAG_S5 |
|||
sd s5, 0x0(t0) |
|||
li t0, EJTAG_S6 |
|||
sd s6, 0x0(t0) |
|||
li t0, EJTAG_S7 |
|||
sd s7, 0x0(t0) |
|||
li t0, EJTAG_K0 |
|||
sd k0, 0x0(t0) |
|||
li t0, EJTAG_K1 |
|||
sd k1, 0x0(t0) |
|||
li t0, EJTAG_GP |
|||
sd gp, 0x0(t0) |
|||
li t0, EJTAG_SP |
|||
sd sp, 0x0(t0) |
|||
li t0, EJTAG_FP |
|||
sd s8, 0x0(t0) |
|||
li t0, EJTAG_RA |
|||
sd ra, 0x0(t0) |
|||
|
|||
li t0, EJTAG_INDEX |
|||
dmfc0 t1, CP0_INDEX |
|||
sd t1, 0x0(t0) |
|||
li t0, EJTAG_RANDOM |
|||
dmfc0 t1, CP0_RANDOM |
|||
sd t1, 0x0(t0) |
|||
li t0, EJTAG_RANDOM |
|||
dmfc0 t1, CP0_ENTRYLO0 |
|||
sd t1, 0x0(t0) |
|||
li t0, EJTAG_ENTRYLO1 |
|||
dmfc0 t1, CP0_ENTRYLO1 |
|||
sd t1, 0x0(t0) |
|||
li t0, EJTAG_CONTEXT |
|||
dmfc0 t1, CP0_CONTEXT |
|||
sd t1, 0x0(t0) |
|||
li t0, EJTAG_PAGEMASK |
|||
dmfc0 t1, CP0_PAGEMASK |
|||
sd t1, 0x0(t0) |
|||
li t0, EJTAG_WIRED |
|||
dmfc0 t1, CP0_WIRED |
|||
sd t1, 0x0(t0) |
|||
.set mips64 |
|||
li t0, EJTAG_HWRENA |
|||
mfc0 t1, CP0_HWRENA,0 |
|||
.set mips3 |
|||
sd t1, 0x0(t0) |
|||
li t0, EJTAG_BADVADDR |
|||
dmfc0 t1, CP0_BADVADDR |
|||
sd t1, 0x0(t0) |
|||
li t0, EJTAG_COUNT |
|||
dmfc0 t1, CP0_COUNT |
|||
sd t1, 0x0(t0) |
|||
li t0, EJTAG_ENTRYHI |
|||
dmfc0 t1, CP0_ENTRYHI |
|||
sd t1, 0x0(t0) |
|||
li t0, EJTAG_COMPARE |
|||
dmfc0 t1, CP0_COMPARE |
|||
sd t1, 0x0(t0) |
|||
li t0, EJTAG_STATUS |
|||
dmfc0 t1, CP0_STATUS |
|||
sd t1, 0x0(t0) |
|||
li t0, EJTAG_CAUSE |
|||
dmfc0 t1, CP0_CAUSE |
|||
sd t1, 0x0(t0) |
|||
li t0, EJTAG_EPC |
|||
dmfc0 t1, CP0_EPC |
|||
sd t1, 0x0(t0) |
|||
li t0, EJTAG_PRID |
|||
dmfc0 t1, CP0_PRID |
|||
sd t1, 0x0(t0) |
|||
li t0, EJTAG_CONFIG |
|||
dmfc0 t1, CP0_CONFIG |
|||
sd t1, 0x0(t0) |
|||
li t0, EJTAG_LLADDR |
|||
dmfc0 t1, CP0_LLADDR |
|||
sd t1, 0x0(t0) |
|||
li t0, EJTAG_WATCHLO |
|||
dmfc0 t1, CP0_WATCHLO |
|||
sd t1, 0x0(t0) |
|||
li t0, EJTAG_WATCHHI |
|||
dmfc0 t1, CP0_WATCHHI |
|||
sd t1, 0x0(t0) |
|||
li t0, EJTAG_XCONTEXT |
|||
dmfc0 t1, CP0_XCONTEXT |
|||
sd t1, 0x0(t0) |
|||
li t0, EJTAG_DEPC |
|||
dmfc0 t1, CP0_DEPC |
|||
sd t1, 0x0(t0) |
|||
li t0, EJTAG_ERROREPC |
|||
dmfc0 t1, CP0_ERROREPC |
|||
sd t1, 0x0(t0) |
|||
/* get t0 from CP0_DESAVE and save it */ |
|||
li t0, EJTAG_DESAVE |
|||
dmfc0 t1, CP0_DESAVE |
|||
sd t1, 0x0(t0) |
|||
|
|||
/* below dump TLB Registers */ |
|||
//#include "lookuptlb_ejtag.S" |
|||
#include "lookuptlb.S" |
|||
|
|||
|
|||
b 18f |
|||
nop |
|||
|
|||
16: |
|||
|
|||
/* do sd/sw/ld/lw according value in TYPEREG */ |
|||
andi t3, t1,0xf; |
|||
|
|||
/* get accessing mem length */ |
|||
li t0, LENGREG |
|||
ld t2, 0x0(t0) |
|||
#ifdef DEBUG |
|||
li t0, DBGREG |
|||
sd t2, 0x0(t0) |
|||
#endif |
|||
#beqz t2,11f |
|||
beqz t2,11b |
|||
nop |
|||
14: |
|||
/* t4: get address for a store or load instruction */ |
|||
li t0, ADDRREG |
|||
ld t4, 0x0(t0) |
|||
#ifdef DEBUG |
|||
li t0, DBGREG |
|||
sd t4, 0x0(t0) |
|||
#endif |
|||
|
|||
/* if ld/lw instruction, no need ld DATAREG */ |
|||
bge t3,0x8, 110f |
|||
|
|||
/* t5: get data for a store or load insturction */ |
|||
li t0, DATAREG |
|||
ld t5, 0x0(t0) //WARING HERRE!!!! first ld, but later lw maybe |
|||
//#ifdef DEBUG |
|||
#if 1 |
|||
li t0, DBGREG |
|||
sd t5, 0x0(t0) |
|||
#endif |
|||
|
|||
110: |
|||
beq t3, LDDW, 1110f |
|||
nop |
|||
beq t3, LDW, 1111f |
|||
nop |
|||
beq t3, STDW, 1112f |
|||
nop |
|||
beq t3, STW, 1113f |
|||
nop |
|||
|
|||
1110: |
|||
sd t5, 0x0(t4) |
|||
b 113f |
|||
nop |
|||
1111: |
|||
/* why using delay slot like below fail ? */ |
|||
sw t5, 0x0(t4) |
|||
b 113f |
|||
nop |
|||
1112: |
|||
ld t5, 0x0(t4) |
|||
##ifdef DEBUG |
|||
# li t0, DBGREG |
|||
# sd t5, 0x0(t0) |
|||
##endif |
|||
li t0, DATAREG |
|||
sd t5, 0x0(t0) |
|||
b 113f |
|||
nop |
|||
1113: |
|||
lw t5, 0x0(t4) |
|||
li t0, DATAREG |
|||
sw t5, 0x0(t0) |
|||
b 113f |
|||
nop |
|||
113: |
|||
subu t2, t2, 0x1 |
|||
bne t2, $0, 14b |
|||
nop |
|||
|
|||
18: |
|||
/* added for cmd executed counter */ |
|||
addu t6, t6,0x1; |
|||
li t0, CMDCNTREG |
|||
sd t6, 0x0(t0) |
|||
/* to check whether all cmds is done */ |
|||
bne t6, t7, 11b |
|||
nop |
|||
|
|||
// restore context |
|||
12: |
|||
li t0, CONTEXTREG |
|||
ld t1, 0x08(t0) |
|||
ld t2, 0x10(t0) |
|||
ld t3, 0x18(t0) |
|||
ld t4, 0x20(t0) |
|||
ld t5, 0x28(t0) |
|||
ld t6, 0x30(t0) |
|||
ld t7, 0x38(t0) |
|||
#mtc0 t8, CP0_STATUS_REG |
|||
#ld t8, 0x48(t0) |
|||
#mtc0 t8, CP0_CONFIG |
|||
#ld t8, 0x50(t0) |
|||
#mtc0 t8, CP0_CAUSE_REG |
|||
|
|||
dmfc0 t0, CP0_DESAVE |
|||
|
|||
.set mips64 |
|||
deret |
|||
.set mips3 |
|||
//////////////////////////////////////////// |
|||
@ -0,0 +1,307 @@ |
|||
#define I2C_NACK 0x08 |
|||
#define I2C_RD 0x20 |
|||
#define I2C_WR 0x10 |
|||
#define I2C_START 0x80 |
|||
#define I2C_STOP 0x40 |
|||
#if 1 |
|||
unsigned char atp8620_i2c_read(unsigned char slave_addr,unsigned char sub_addr,unsigned char* buf ,int count) |
|||
{ |
|||
pcitag_t tag; |
|||
int i; |
|||
volatile unsigned char * iog; |
|||
volatile unsigned char tmp; |
|||
tag = _pci_make_tag(0,9,0); |
|||
iog = _pci_conf_readn(tag,0x10,4); |
|||
#define CTR (volatile unsigned char *)(iog + 0x0) |
|||
#define TXR (volatile unsigned char *)(iog + 0x1) |
|||
#define RXR (volatile unsigned char *)(iog + 0x2) |
|||
// printf("iog %x \n",iog);
|
|||
iog =((unsigned int )iog|0xbfd00000|0xb0)&0xfffffffe; |
|||
for(i=0;i<count;i++) |
|||
{ |
|||
tmp = *CTR; |
|||
while(tmp&0x1) |
|||
tmp=*CTR; |
|||
delay(10); |
|||
|
|||
*TXR = slave_addr; |
|||
*CTR = I2C_WR|I2C_START; |
|||
|
|||
if(word_addr){ |
|||
|
|||
tmp = *CTR; |
|||
while(tmp&0x1) |
|||
tmp=*CTR; |
|||
delay(10); |
|||
|
|||
*TXR = 0; |
|||
*CTR = I2C_WR; |
|||
} |
|||
tmp = *CTR; |
|||
while(tmp&0x1) |
|||
tmp=*CTR; |
|||
delay(10); |
|||
*TXR = sub_addr; |
|||
*CTR = I2C_WR; |
|||
|
|||
tmp = *CTR; |
|||
while(tmp&0x1) |
|||
tmp=*CTR; |
|||
delay(10); |
|||
*TXR = slave_addr+1; |
|||
*CTR = I2C_WR|I2C_START; |
|||
|
|||
delay(1); |
|||
///
|
|||
*CTR = I2C_RD; |
|||
tmp = *CTR; |
|||
while(tmp&0x1) |
|||
tmp=*CTR; |
|||
delay(10); |
|||
|
|||
tmp = *RXR; |
|||
buf[i] = tmp; |
|||
|
|||
*CTR = I2C_STOP; |
|||
|
|||
} |
|||
} |
|||
|
|||
#else |
|||
unsigned char atp8620_i2c_read(unsigned char slave_addr,unsigned char sub_addr,unsigned char* buf ,int count) |
|||
{ |
|||
pcitag_t tag; |
|||
int i; |
|||
volatile unsigned int * iog; |
|||
volatile unsigned int tmp; |
|||
tag = _pci_make_tag(0,9,0); |
|||
iog = _pci_conf_readn(tag,0x10,4); |
|||
// printf("iog %x \n",iog);
|
|||
iog =((unsigned int )iog|0xbfd00000|0xb0)&0xfffffffe; |
|||
// printf("iog %x \n",iog);
|
|||
for(i=0;i<count;i++) |
|||
{ |
|||
tmp = *iog; |
|||
// printf("tmp %x \n",tmp);
|
|||
while(tmp&0x1) |
|||
{tmp = *iog; |
|||
} |
|||
delay(10); |
|||
|
|||
tmp = (slave_addr&0xff)<<8; |
|||
tmp = tmp|I2C_WR|I2C_START|I2C_NACK; |
|||
*iog = tmp; |
|||
|
|||
if(word_addr) |
|||
{ |
|||
tmp = *iog; |
|||
while(tmp&0x1) |
|||
tmp = *iog; |
|||
delay(10); |
|||
|
|||
tmp = 0; |
|||
tmp = tmp|I2C_WR|I2C_NACK; |
|||
*iog = tmp; |
|||
|
|||
} |
|||
|
|||
tmp = *iog; |
|||
while(tmp&0x1) |
|||
tmp = *iog; |
|||
delay(10); |
|||
|
|||
tmp = (sub_addr&0xff)<<8; |
|||
tmp = tmp|I2C_WR|I2C_NACK; |
|||
*iog = tmp; |
|||
|
|||
tmp = *iog; |
|||
while(tmp&0x1) |
|||
tmp = *iog; |
|||
delay(10); |
|||
|
|||
tmp = ((slave_addr&0xff)+1)<<8; |
|||
tmp = tmp|I2C_WR|I2C_START|I2C_NACK; |
|||
*iog = tmp; |
|||
|
|||
tmp = *iog; |
|||
while(tmp&0x1) |
|||
tmp = *iog; |
|||
delay(10); |
|||
|
|||
tmp = I2C_RD|I2C_STOP; |
|||
*iog = tmp; |
|||
|
|||
tmp = *iog; |
|||
while(tmp&0x1) |
|||
tmp = *iog; |
|||
delay(10); |
|||
|
|||
tmp = *iog; |
|||
tmp = tmp&0xffff0000; |
|||
tmp = tmp>>16; |
|||
buf[i] = tmp&0xff; |
|||
|
|||
/*
|
|||
tmp = I2C_STOP; |
|||
*iog = tmp; |
|||
|
|||
tmp = *iog; |
|||
while(tmp&0x1) |
|||
tmp = *iog; |
|||
delay(10); |
|||
*/ |
|||
} |
|||
return 0; |
|||
|
|||
|
|||
} |
|||
|
|||
#endif |
|||
|
|||
unsigned char atp8620_i2c_write(unsigned char slave_addr,unsigned char sub_addr,unsigned char * buf ,int count) |
|||
{ |
|||
pcitag_t tag; |
|||
int i; |
|||
volatile unsigned int * iog; |
|||
volatile unsigned int tmp; |
|||
tag = _pci_make_tag(0,9,0); |
|||
iog = _pci_conf_readn(tag,0x10,4); |
|||
iog = ((unsigned int )iog|0xbfd00000|0xb0)&0xfffffffe; |
|||
|
|||
for(i=0;i<count;i++) |
|||
{ |
|||
tmp = *iog; |
|||
while(tmp&0x1) |
|||
tmp = *iog; |
|||
|
|||
tmp = (slave_addr&0xff)<<8; |
|||
tmp = tmp|I2C_WR|I2C_START|I2C_NACK; |
|||
*iog = tmp; |
|||
|
|||
if(word_addr) |
|||
{ |
|||
tmp = *iog; |
|||
while(tmp&0x1) |
|||
tmp = *iog; |
|||
|
|||
tmp = 0; |
|||
tmp = tmp|I2C_WR|I2C_NACK; |
|||
*iog = tmp; |
|||
|
|||
} |
|||
|
|||
tmp = *iog; |
|||
while(tmp&0x1) |
|||
tmp = *iog; |
|||
|
|||
tmp = (sub_addr&0xff)<<8; |
|||
tmp = tmp|I2C_WR|I2C_NACK; |
|||
*iog = tmp; |
|||
|
|||
tmp = *iog; |
|||
while(tmp&0x1) |
|||
tmp = *iog; |
|||
|
|||
tmp = buf[i]<<8; |
|||
tmp = tmp|I2C_WR|I2C_NACK; |
|||
*iog = tmp; |
|||
|
|||
tmp = *iog; |
|||
while(tmp&0x1) |
|||
tmp = *iog; |
|||
|
|||
|
|||
tmp = I2C_STOP; |
|||
*iog = tmp; |
|||
} |
|||
|
|||
return 0; |
|||
} |
|||
|
|||
|
|||
static int firewall_i2c_read(int type,long long addr,union commondata *mydata) |
|||
{ |
|||
char c; |
|||
switch(type) |
|||
{ |
|||
case 1: |
|||
atp8620_i2c_read((unsigned char)slave_addr,(unsigned char)addr,&c,1); |
|||
memcpy(&mydata->data1,&c,1); |
|||
return 0; |
|||
default: |
|||
return -1; |
|||
|
|||
} |
|||
|
|||
} |
|||
static int firewall_i2c_write(int type,long long addr,union commondata *mydata) |
|||
{ |
|||
char c; |
|||
switch(type) |
|||
{ |
|||
case 1: |
|||
memcpy(&c,&mydata->data1,1); |
|||
atp8620_i2c_write((unsigned char)slave_addr,(unsigned char)addr,&c,1); |
|||
return 0; |
|||
default : |
|||
return -1; |
|||
|
|||
} |
|||
|
|||
} |
|||
static int i2cs(int argc,char *argv[]) |
|||
{ |
|||
if(argc<2) |
|||
return -1; |
|||
printf("i2c\n"); |
|||
|
|||
i2cslot=strtoul(argv[1],0,0); |
|||
|
|||
switch(i2cslot) |
|||
{ |
|||
case 0: |
|||
slave_addr = strtoul(argv[2],0,0); |
|||
if(slave_addr==0xde||slave_addr == 0xae) |
|||
{ |
|||
word_addr = 1; |
|||
printf("rtc opreation!\n"); |
|||
} |
|||
else |
|||
word_addr = 0; |
|||
syscall1 = (void *)firewall_i2c_read; |
|||
syscall2 = (void *)firewall_i2c_write; |
|||
break; |
|||
case 1: |
|||
slave_addr = strtoul(argv[2],0,0); |
|||
if(slave_addr==0xde||slave_addr == 0xae) |
|||
{ |
|||
word_addr = 1; |
|||
printf("rtc opreation!\n"); |
|||
} |
|||
else |
|||
word_addr = 0; |
|||
syscall1 = (void *)sm502SPDRead; |
|||
syscall2 = (void *)sm502SPDWrite; |
|||
break; |
|||
case 2: |
|||
i2c_test(); |
|||
break; |
|||
case 3: |
|||
syscall1=(void *)rom_ddr_reg_read; |
|||
syscall2=(void *)rom_ddr_reg_write; |
|||
if(argc==3 && !strcmp(argv[2][2],"revert")) |
|||
{ |
|||
extern char ddr2_reg_data,_start; |
|||
extern char ddr2_reg_data1; |
|||
printf("revert to default ddr setting\n"); |
|||
// tgt_flashprogram(0xbfc00000+((int)&ddr2_reg_data -(int)&_start),30*8,&ddr2_reg_data1,TRUE);
|
|||
} |
|||
break; |
|||
|
|||
default: |
|||
return -1; |
|||
} |
|||
|
|||
return 0; |
|||
} |
|||
#else |
|||
@ -0,0 +1,210 @@ |
|||
int SMB_BASE_ADDR=0; |
|||
#define SMB_SDA 0x00 |
|||
#define SMB_STS 0x01 |
|||
#define SMB_STS_SLVSTP (1 << 7) |
|||
#define SMB_STS_SDAST (1 << 6) |
|||
#define SMB_STS_BER (1 << 5) |
|||
#define SMB_STS_NEGACK (1 << 4) |
|||
#define SMB_STS_STASTR (1 << 3) |
|||
#define SMB_STS_NMATCH (1 << 2) |
|||
#define SMB_STS_MASTER (1 << 1) |
|||
#define SMB_STS_XMIT (1 << 0) |
|||
#define SMB_CTRL_STS 0x02 |
|||
#define SMB_CSTS_TGSTL (1 << 5) |
|||
#define SMB_CSTS_TSDA (1 << 4) |
|||
#define SMB_CSTS_GCMTCH (1 << 3) |
|||
#define SMB_CSTS_MATCH (1 << 2) |
|||
#define SMB_CSTS_BB (1 << 1) |
|||
#define SMB_CSTS_BUSY (1 << 0) |
|||
#define SMB_CTRL1 0x03 |
|||
#define SMB_CTRL1_STASTRE (1 << 7) |
|||
#define SMB_CTRL1_NMINTE (1 << 6) |
|||
#define SMB_CTRL1_GCMEN (1 << 5) |
|||
#define SMB_CTRL1_ACK (1 << 4) |
|||
#define SMB_CTRL1_RSVD (1 << 3) |
|||
#define SMB_CTRL1_INTEN (1 << 2) |
|||
#define SMB_CTRL1_STOP (1 << 1) |
|||
#define SMB_CTRL1_START (1 << 0) |
|||
#define SMB_ADDR 0x04 |
|||
#define SMB_ADDR_SAEN (1 << 7) |
|||
#define SMB_CTRL2 0x05 |
|||
#define SMB_ENABLE (1 << 0) |
|||
#define SMB_CTRL3 0x06 |
|||
|
|||
|
|||
//p395
|
|||
static int i2c_wait() |
|||
{ |
|||
char c; |
|||
int i; |
|||
delay(1000); |
|||
for(i=0;i<20;i++) |
|||
{ |
|||
c = linux_inb(SMB_BASE_ADDR|SMB_STS); |
|||
if(c&SMB_STS_BER)return -1; |
|||
if(c&SMB_STS_SDAST)return 0; |
|||
delay(100); |
|||
} |
|||
return -2; |
|||
} |
|||
|
|||
|
|||
|
|||
|
|||
static int i2c_read_single(int addr, int regNo,char *value) |
|||
{ |
|||
int i; |
|||
unsigned char c; |
|||
int j; |
|||
linux_outb(SMB_CTRL1_START,SMB_BASE_ADDR|SMB_CTRL1); |
|||
i2c_wait(); |
|||
linux_outb(addr&0xfe,SMB_BASE_ADDR); |
|||
i2c_wait(); |
|||
linux_outb(regNo,SMB_BASE_ADDR); |
|||
i2c_wait(); |
|||
linux_outb(SMB_CTRL1_ACK|SMB_CTRL1_START,SMB_BASE_ADDR|SMB_CTRL1); |
|||
i2c_wait(); |
|||
linux_outb(addr|1,SMB_BASE_ADDR); |
|||
i2c_wait(); |
|||
*value=linux_inb(SMB_BASE_ADDR); |
|||
linux_outb(2,SMB_BASE_ADDR|SMB_CTRL1); |
|||
i2c_wait(); |
|||
//clear error
|
|||
//linux_outb(0x10,SMB_BASE_ADDR|SMB_STS);
|
|||
c=linux_inb(SMB_BASE_ADDR|SMB_STS); |
|||
linux_outb(0x30,SMB_BASE_ADDR|SMB_STS); |
|||
return 0; |
|||
} |
|||
|
|||
static int i2c_write_single(int addr, int regNo,char *value) |
|||
{ |
|||
int i; |
|||
unsigned char c; |
|||
int j; |
|||
linux_outb(SMB_CTRL1_START,SMB_BASE_ADDR|SMB_CTRL1); |
|||
i2c_wait(); |
|||
linux_outb(addr&0xfe,SMB_BASE_ADDR); |
|||
i2c_wait(); |
|||
linux_outb(regNo,SMB_BASE_ADDR); |
|||
i2c_wait(); |
|||
linux_outb(*value,SMB_BASE_ADDR); |
|||
i2c_wait(); |
|||
linux_outb(2,SMB_BASE_ADDR|SMB_CTRL1); |
|||
i2c_wait(); |
|||
//clear error
|
|||
//linux_outb(0x10,SMB_BASE_ADDR|SMB_STS);
|
|||
c=linux_inb(SMB_BASE_ADDR|SMB_STS); |
|||
linux_outb(0x30,SMB_BASE_ADDR|SMB_STS); |
|||
return 0; |
|||
} |
|||
|
|||
|
|||
static int i2c_read_smbblock(int addr,int regNo,unsigned char *buf,char len) { |
|||
int i; |
|||
unsigned char c,count; |
|||
int j; |
|||
|
|||
linux_outb(SMB_CTRL1_START,SMB_BASE_ADDR|SMB_CTRL1); |
|||
i2c_wait(); |
|||
linux_outb(addr&0xfe,SMB_BASE_ADDR); |
|||
i2c_wait(); |
|||
linux_outb(regNo,SMB_BASE_ADDR); |
|||
i2c_wait(); |
|||
linux_outb(SMB_CTRL1_START,SMB_BASE_ADDR|SMB_CTRL1); |
|||
i2c_wait(); |
|||
linux_outb(addr|1,SMB_BASE_ADDR); |
|||
i2c_wait(); |
|||
count = linux_inb((SMB_BASE_ADDR)); |
|||
delay(4000); |
|||
i2c_wait(); |
|||
for(i = 0; i < count+20; i++) |
|||
{ |
|||
if(i2c_wait()<0){printf("i=%d\n",i);break;} |
|||
c=linux_inb((SMB_BASE_ADDR)); |
|||
if(i<len)buf[i]=c; |
|||
} |
|||
i2c_wait(); |
|||
c=linux_inb((SMB_BASE_ADDR)); |
|||
|
|||
linux_outb(2,SMB_BASE_ADDR|SMB_CTRL1); |
|||
|
|||
i2c_wait(); |
|||
//clear error
|
|||
c=linux_inb(SMB_BASE_ADDR|SMB_STS); |
|||
linux_outb(0x30,SMB_BASE_ADDR|SMB_STS); |
|||
return count; |
|||
} |
|||
|
|||
static int i2c_write_smbblock(int addr,int regNo, char *buf,int len) { |
|||
int i, j; |
|||
unsigned char c; |
|||
|
|||
|
|||
linux_outb(SMB_CTRL1_START,SMB_BASE_ADDR|SMB_CTRL1); |
|||
i2c_wait(); |
|||
linux_outb(addr&0xfe,SMB_BASE_ADDR); |
|||
i2c_wait(); |
|||
linux_outb(regNo,SMB_BASE_ADDR); |
|||
i2c_wait(); |
|||
|
|||
linux_outb(len,SMB_BASE_ADDR); |
|||
i2c_wait(); |
|||
|
|||
for(i=0;i<len;i++) |
|||
{ |
|||
linux_outb(buf[i],SMB_BASE_ADDR); |
|||
i2c_wait(); |
|||
} |
|||
|
|||
linux_outb(2,SMB_BASE_ADDR|SMB_CTRL1); |
|||
|
|||
i2c_wait(); |
|||
//clear error
|
|||
c=linux_inb(SMB_BASE_ADDR|SMB_STS); |
|||
linux_outb(0x30,SMB_BASE_ADDR|SMB_STS); |
|||
|
|||
|
|||
return len; |
|||
} |
|||
|
|||
|
|||
int tgt_i2cread(int type,unsigned char *addr,int addrlen,unsigned char reg,unsigned char *buf,int count) |
|||
{ |
|||
int i; |
|||
if(!SMB_BASE_ADDR)SMB_BASE_ADDR=(_pci_conf_read(_pci_make_tag(0,14,0),0x10))&~3; |
|||
memset(buf,-1,count); |
|||
switch(type) |
|||
{ |
|||
case I2C_SINGLE: |
|||
for(i=0;i<count;i++) |
|||
{ |
|||
i2c_read_single(addr[0],reg+i,buf+i); |
|||
} |
|||
break; |
|||
case I2C_SMB_BLOCK: |
|||
i2c_read_smbblock(addr[0],reg,buf,count); |
|||
default: return 0;break; |
|||
} |
|||
return count; |
|||
} |
|||
|
|||
int tgt_i2cwrite(int type,unsigned char *addr,int addrlen,unsigned char reg,unsigned char *buf,int count) |
|||
{ |
|||
int i; |
|||
if(!SMB_BASE_ADDR)SMB_BASE_ADDR=(_pci_conf_read(_pci_make_tag(0,14,0),0x10))&~3; |
|||
switch(type) |
|||
{ |
|||
case I2C_SINGLE: |
|||
for(i=0;i<count;i++) |
|||
{ |
|||
i2c_write_single(addr[0],reg,buf+i); |
|||
} |
|||
break; |
|||
case I2C_SMB_BLOCK: |
|||
i2c_write_smbblock(addr[0],reg,buf,count); |
|||
break; |
|||
default:return -1;break; |
|||
} |
|||
return count; |
|||
} |
|||
|
|||
@ -0,0 +1,209 @@ |
|||
|
|||
PRINTSTR("DIMM read\r\n") |
|||
|
|||
/* only one memory slot, slave address is 1010000b */ |
|||
|
|||
li a1, 0x0 |
|||
1: |
|||
li a0,0xa1 |
|||
bal i2cread |
|||
nop |
|||
|
|||
# save a1 |
|||
move t1, a1 |
|||
|
|||
#print |
|||
move a0, v0 |
|||
bal hexserial |
|||
nop |
|||
|
|||
PRINTSTR("\r\n") |
|||
|
|||
# restore a1 |
|||
move a1,t1 |
|||
addiu a1,a1,1 |
|||
|
|||
li v0, 0x20 |
|||
bleu a1, v0, 1b |
|||
nop |
|||
|
|||
li msize,0 |
|||
# set some parameters for DDR333 |
|||
# rank number and DDR type field will be filled later |
|||
# to check: fix TCAS? |
|||
# li sdCfg, 0x341043df |
|||
|
|||
# li sdCfg, 0x255043df /* zgj */ |
|||
|
|||
li sdCfg,0x055043df /* zgj-8-7-14-13 */ |
|||
|
|||
|
|||
li a0,0xa1 |
|||
|
|||
/* read DIMM memory type (must be DDRAM) */ |
|||
#li a1,2 |
|||
#bal i2cread |
|||
#nop |
|||
#bne v0,7,.nodimm |
|||
#nop |
|||
PRINTSTR("read memory type\r\n") |
|||
|
|||
/* read DIMM number of rows */ |
|||
li a0,0xa1 |
|||
li a1,3 |
|||
bal i2cread |
|||
nop |
|||
move a0, v0 |
|||
subu v0, 12 |
|||
move s1, v0 |
|||
|
|||
bgtu v0, 2,.nodimm |
|||
nop |
|||
PRINTSTR("read number of rows\r\n") |
|||
|
|||
2: /* read DIMM number of cols */ |
|||
li a0,0xa1 |
|||
li a1,4 |
|||
bal i2cread |
|||
nop |
|||
|
|||
subu v0, 8 |
|||
bgtu v0, 4,.nodimm |
|||
nop |
|||
|
|||
move t1, s1 |
|||
|
|||
PRINTSTR("DDR type 10 bal\r\n"); |
|||
|
|||
bne t1, 0, 10f |
|||
nop |
|||
PRINTSTR("DDR type 20 bal\r\n"); /* zgj */ |
|||
|
|||
bne v0, 2, 20f |
|||
nop |
|||
li v0, 0 |
|||
PRINTSTR("DDR type 2022 bal\r\n"); /* zgj */ |
|||
b .ddrtype |
|||
nop |
|||
|
|||
PRINTSTR("DDR type 21 bal\r\n"); /* zgj */ |
|||
20: bne v0, 1, 21f |
|||
nop |
|||
PRINTSTR("DDR type 22 bal\r\n"); /* zgj */ |
|||
li v0, 1 |
|||
b .ddrtype |
|||
nop |
|||
21: bne v0, 0, 22f |
|||
nop |
|||
|
|||
PRINTSTR("DDR type 33 bal\r\n"); /* zgj */ |
|||
|
|||
li v0, 2 |
|||
b .ddrtype |
|||
nop |
|||
22: bne v0, 3, 33f |
|||
nop |
|||
li v0, 3 |
|||
b .ddrtype |
|||
nop |
|||
10: bne t1, 1, 11f |
|||
nop |
|||
bne v0, 3, 20f |
|||
nop |
|||
li v0, 4 |
|||
b .ddrtype |
|||
nop |
|||
20: bne v0, 2, 21f |
|||
nop |
|||
li v0, 5 |
|||
b .ddrtype |
|||
nop |
|||
21: bne v0, 1, 22f |
|||
nop |
|||
li v0, 6 |
|||
b .ddrtype |
|||
nop |
|||
22: bne v0, 4, 33f |
|||
nop |
|||
li v0, 7 |
|||
b .ddrtype |
|||
nop |
|||
11: bne t1, 2, 33f |
|||
nop |
|||
bne v0, 4, 20f |
|||
nop |
|||
li v0, 8 |
|||
b .ddrtype |
|||
nop |
|||
20: bne v0, 3, 21f |
|||
nop |
|||
li v0, 9 |
|||
b .ddrtype |
|||
nop |
|||
21: bne v0, 2, 33f |
|||
nop |
|||
li v0, 10 |
|||
b .ddrtype |
|||
nop |
|||
33: PRINTSTR("DDR type not supported!\r\n"); |
|||
34: b 34b |
|||
nop |
|||
|
|||
.ddrtype: |
|||
#bit 25:22 is DDR type field |
|||
sll v0, 22 |
|||
and v0,0x03c00000 |
|||
or sdCfg,v0 |
|||
|
|||
|
|||
PRINTSTR("sdcfg11="); |
|||
move a0,sdCfg |
|||
bal hexserial |
|||
nop |
|||
PRINTSTR("\r\n"); |
|||
|
|||
/* read DIMM memory size per side */ |
|||
li a0,0xa1 |
|||
li a1,31 |
|||
bal i2cread |
|||
nop |
|||
beqz v0,.nodimm |
|||
nop |
|||
sll tmpsize,v0,22 # multiply by 4M |
|||
PRINTSTR("read memory size per side\r\n") |
|||
|
|||
2: /* read DIMM number of blocks-per-ddrram */ |
|||
li a1,17 |
|||
bal i2cread |
|||
nop |
|||
beq v0,2,2f |
|||
nop |
|||
bne v0,4,.nodimm |
|||
nop |
|||
PRINTSTR("read blocks per ddrram\r\n") |
|||
|
|||
2: /* read DIMM number of sides (banks) */ |
|||
li a1,5 |
|||
bal i2cread |
|||
nop |
|||
beq v0,1,2f |
|||
nop |
|||
bne v0,2,.nodimm |
|||
nop |
|||
sll tmpsize,1 # msize *= 2 |
|||
or sdCfg, 0x1<<27 |
|||
PRINTSTR("read number of sides\r\n") |
|||
|
|||
2: /* read DIMM width */ |
|||
li a1,6 |
|||
bal i2cread |
|||
nop |
|||
bleu v0,36,2f |
|||
nop |
|||
bgtu v0,72,.nodimm |
|||
nop |
|||
PRINTSTR("read width\r\n") |
|||
|
|||
2: addu msize,tmpsize |
|||
b 2f |
|||
nop |
|||
@ -0,0 +1,409 @@ |
|||
#ifdef DEVBD2F_SM502 |
|||
static volatile char *mmio = 0; |
|||
|
|||
#define GPIO_DIR_REG (volatile unsigned int *)(mmio + 0x1000c) |
|||
#define GPIO_DATA_REG (volatile unsigned int *)(mmio + 0x10004) |
|||
#define G_OUTPUT 1 |
|||
#define G_INPUT 0 |
|||
#define GPIO_SDA_DIR_SHIFT 15 |
|||
#define GPIO_SCL_DIR_SHIFT 14 |
|||
#define GPIO_SDA_DATA_SHIFT 15 |
|||
#define GPIO_SCL_DATA_SHIFT 14 |
|||
|
|||
#elif defined(DEVBD2F_FIREWALL) |
|||
|
|||
#define GPIO_DIR_REG (volatile unsigned int *)(0xbfe00120) |
|||
#define GPIO_DATA_REG (volatile unsigned int *)(0xbfe0011c) |
|||
|
|||
#define G_OUTPUT 0 |
|||
#define G_INPUT 1 |
|||
#define GPIO_SDA_DIR_SHIFT 2 |
|||
#define GPIO_SCL_DIR_SHIFT 3 |
|||
#define GPIO_SDA_DATA_SHIFT 2 |
|||
#define GPIO_SCL_DATA_SHIFT 3 |
|||
//extern int word_addr = 0;
|
|||
|
|||
#endif |
|||
|
|||
static void i2c_sleep(int ntime) |
|||
{ |
|||
int i,j=0; |
|||
for(i=0; i<300*ntime; i++) |
|||
{ |
|||
j=i; |
|||
j+=i; |
|||
} |
|||
} |
|||
|
|||
void sda_dir(int ivalue) |
|||
{ |
|||
int tmp; |
|||
tmp = *GPIO_DIR_REG; |
|||
if(ivalue == 1) |
|||
*GPIO_DIR_REG = tmp|(0x1<<GPIO_SDA_DIR_SHIFT); |
|||
else |
|||
*GPIO_DIR_REG = tmp&(~(0x1<<GPIO_SDA_DIR_SHIFT)); |
|||
} |
|||
void scl_dir(int ivalue) |
|||
{ |
|||
int tmp; |
|||
tmp = *GPIO_DIR_REG; |
|||
if(ivalue == 1) |
|||
*GPIO_DIR_REG = tmp|(0x1<<GPIO_SCL_DIR_SHIFT); |
|||
else |
|||
*GPIO_DIR_REG = tmp&(~(0x1<<GPIO_SCL_DIR_SHIFT)); |
|||
} |
|||
|
|||
void sda_bit(int ivalue) |
|||
{ |
|||
int tmp; |
|||
tmp = *GPIO_DATA_REG; |
|||
if(ivalue == 1) |
|||
*GPIO_DATA_REG = tmp|(0x1<<GPIO_SDA_DATA_SHIFT); |
|||
else |
|||
*GPIO_DATA_REG = tmp&(~(0x1<<GPIO_SDA_DATA_SHIFT)); |
|||
} |
|||
void scl_bit(int ivalue) |
|||
{ |
|||
int tmp; |
|||
tmp = *GPIO_DATA_REG; |
|||
if(ivalue == 1) |
|||
*GPIO_DATA_REG = tmp|(0x1<<GPIO_SCL_DATA_SHIFT); |
|||
else |
|||
*GPIO_DATA_REG = tmp&(~(0x1<<GPIO_SCL_DATA_SHIFT)); |
|||
} |
|||
|
|||
|
|||
static void i2c_start(void) |
|||
{ |
|||
sda_dir(G_OUTPUT); |
|||
scl_dir(G_OUTPUT); |
|||
scl_bit(0); |
|||
i2c_sleep(1); |
|||
sda_bit(1); |
|||
i2c_sleep(1); |
|||
scl_bit(1); |
|||
i2c_sleep(5); |
|||
sda_bit(0); |
|||
i2c_sleep(5); |
|||
scl_bit(0); |
|||
i2c_sleep(2); |
|||
|
|||
} |
|||
static void i2c_stop(void) |
|||
{ |
|||
sda_dir(G_OUTPUT); |
|||
scl_dir(G_OUTPUT); |
|||
scl_bit(0); |
|||
i2c_sleep(1); |
|||
sda_bit(0); |
|||
i2c_sleep(1); |
|||
scl_bit(1); |
|||
i2c_sleep(5); |
|||
sda_bit(1); |
|||
i2c_sleep(5); |
|||
scl_bit(0); |
|||
i2c_sleep(2); |
|||
|
|||
|
|||
} |
|||
|
|||
static void i2c_send_ack(int ack) |
|||
{ |
|||
sda_dir(G_OUTPUT); |
|||
sda_bit(ack); |
|||
i2c_sleep(3); |
|||
scl_bit(1); |
|||
i2c_sleep(5); |
|||
scl_bit(0); |
|||
i2c_sleep(2); |
|||
} |
|||
|
|||
static char i2c_rec_ack() |
|||
{ |
|||
char res = 1; |
|||
int num=10; |
|||
int tmp; |
|||
sda_dir(G_INPUT); |
|||
i2c_sleep(3); |
|||
scl_bit(1); |
|||
i2c_sleep(5); |
|||
#ifdef DEVBD2F_SM502 |
|||
tmp = ((*GPIO_DATA_REG)&(0x1<<GPIO_SDA_DATA_SHIFT)); |
|||
#elif DEVBD2F_FIREWALL |
|||
tmp = ((*GPIO_DATA_REG)&(0x1<<(GPIO_SDA_DATA_SHIFT+16))); |
|||
#endif |
|||
//wait for a ack signal from slave
|
|||
|
|||
while(tmp) |
|||
{ |
|||
i2c_sleep(1); |
|||
num--; |
|||
if(!num) |
|||
{ |
|||
res = 0; |
|||
break; |
|||
} |
|||
#ifdef DEVBD2F_SM502 |
|||
tmp = ((*GPIO_DATA_REG)&(0x1<<GPIO_SDA_DATA_SHIFT)); |
|||
#elif DEVBD2F_FIREWALL |
|||
tmp = ((*GPIO_DATA_REG)&(0x1<<(GPIO_SDA_DATA_SHIFT+16))); |
|||
#endif |
|||
} |
|||
scl_bit(0); |
|||
i2c_sleep(3); |
|||
return res; |
|||
} |
|||
|
|||
|
|||
static unsigned char i2c_rec() |
|||
{ |
|||
int i; |
|||
int tmp; |
|||
unsigned char or_char; |
|||
unsigned char value = 0x00; |
|||
sda_dir(G_INPUT); |
|||
for(i=7;i>=0;i--) |
|||
{ |
|||
i2c_sleep(5); |
|||
scl_bit(1); |
|||
i2c_sleep(3); |
|||
#ifdef DEVBD2F_SM502 |
|||
tmp = ((*GPIO_DATA_REG)&(0x1<<GPIO_SDA_DATA_SHIFT)); |
|||
#elif DEVBD2F_FIREWALL |
|||
tmp = ((*GPIO_DATA_REG)&(0x1<<(GPIO_SDA_DATA_SHIFT+16))); |
|||
#endif |
|||
if(tmp) |
|||
or_char=0x1; |
|||
else |
|||
or_char=0x0; |
|||
or_char<<=i; |
|||
value|=or_char; |
|||
i2c_sleep(3); |
|||
scl_bit(0); |
|||
} |
|||
return value; |
|||
} |
|||
|
|||
static unsigned char i2c_send(unsigned char value) |
|||
{//we assume that now scl is 0
|
|||
int i; |
|||
unsigned char and_char; |
|||
sda_dir(G_OUTPUT); |
|||
for(i=7;i>=0;i--) |
|||
{ |
|||
and_char = value; |
|||
and_char>>=i; |
|||
and_char&=0x1; |
|||
if(and_char) |
|||
sda_bit(1); |
|||
else |
|||
sda_bit(0); |
|||
i2c_sleep(1); |
|||
scl_bit(1); |
|||
i2c_sleep(5); |
|||
scl_bit(0); |
|||
i2c_sleep(1); |
|||
} |
|||
sda_bit(1); |
|||
return 1; |
|||
} |
|||
|
|||
unsigned char i2c_rec_s(unsigned char *addr,int addrlen,unsigned char reg,unsigned char* buf ,int count) |
|||
{ |
|||
int i; |
|||
int j; |
|||
|
|||
|
|||
unsigned char value; |
|||
//start signal
|
|||
for(i=0;i<count;i++) |
|||
{ |
|||
i2c_start(); |
|||
for(j=0;j<addrlen;j++) |
|||
{ |
|||
//write slave_addr
|
|||
i2c_send(addr[j]); |
|||
if(!i2c_rec_ack()) |
|||
return 0; |
|||
} |
|||
|
|||
i2c_send(reg); |
|||
if(!i2c_rec_ack()) |
|||
return 0; |
|||
|
|||
//repeat start
|
|||
i2c_start(); |
|||
//write slave_addr+1
|
|||
i2c_send(addr[0]|0x1); |
|||
if(!i2c_rec_ack()) |
|||
return 0; |
|||
//read data
|
|||
buf[i]=i2c_rec(); |
|||
// i2c_send_ack(1);//***add in***//
|
|||
i2c_stop(); |
|||
|
|||
reg++; |
|||
} |
|||
|
|||
return count; |
|||
} |
|||
|
|||
unsigned char i2c_send_s(unsigned char *addr,int addrlen,unsigned char reg,unsigned char * buf ,int count) |
|||
{ |
|||
int i; |
|||
int j; |
|||
for(i=0;i<count;i++) |
|||
{ |
|||
i2c_start(); |
|||
for(j=0;j<addrlen;j++) |
|||
{ |
|||
//write slave_addr
|
|||
i2c_send(addr[j]); |
|||
if(!i2c_rec_ack()) |
|||
return 0; |
|||
} |
|||
|
|||
i2c_send(reg); |
|||
if(!i2c_rec_ack()) |
|||
return 0; |
|||
|
|||
i2c_send(buf[i]); |
|||
if(!i2c_rec_ack()) |
|||
return 0; |
|||
i2c_stop(); |
|||
reg++; |
|||
} |
|||
return 1; |
|||
} |
|||
|
|||
|
|||
unsigned char i2c_rec_b(unsigned char *addr,int addrlen,unsigned char reg,unsigned char* buf ,int count) |
|||
{ |
|||
int i; |
|||
int j; |
|||
|
|||
|
|||
unsigned char value; |
|||
//start signal
|
|||
i2c_start(); |
|||
for(j=0;j<addrlen;j++) |
|||
{ |
|||
//write slave_addr
|
|||
i2c_send(addr[j]); |
|||
if(!i2c_rec_ack()) |
|||
return 0; |
|||
} |
|||
|
|||
i2c_send(reg); |
|||
if(!i2c_rec_ack()) |
|||
return 0; |
|||
|
|||
//repeat start
|
|||
i2c_start(); |
|||
//write slave_addr+1
|
|||
i2c_send(addr[0]|0x1); |
|||
if(!i2c_rec_ack()) |
|||
return 0; |
|||
|
|||
for(i=0;i<count;i++) |
|||
{ |
|||
//read data
|
|||
buf[i]=i2c_rec(); |
|||
// i2c_send_ack(1);//***add in***//
|
|||
|
|||
} |
|||
i2c_stop(); |
|||
|
|||
return count; |
|||
} |
|||
unsigned char i2c_send_b(unsigned char *addr,int addrlen,unsigned char reg,unsigned char * buf ,int count) |
|||
{ |
|||
int i; |
|||
int j; |
|||
i2c_start(); |
|||
for(j=0;j<addrlen;j++) |
|||
{ |
|||
//write slave_addr
|
|||
i2c_send(addr[j]); |
|||
if(!i2c_rec_ack()) |
|||
return 0; |
|||
} |
|||
|
|||
i2c_send(reg); |
|||
if(!i2c_rec_ack()) |
|||
return 0; |
|||
|
|||
for(i=0;i<count;i++) |
|||
{ |
|||
|
|||
i2c_send(buf[i]); |
|||
if(!i2c_rec_ack()) |
|||
return 0; |
|||
} |
|||
i2c_stop(); |
|||
return count; |
|||
} |
|||
//----------------------
|
|||
/*
|
|||
* 0 single: ÿ´Î¶ÁÒ»¸ö |
|||
* 1 smb block |
|||
*/ |
|||
int tgt_i2cread(int type,unsigned char *addr,int addrlen,unsigned char reg,unsigned char *buf,int count) |
|||
{ |
|||
int i; |
|||
tgt_i2cinit(); |
|||
memset(buf,-1,count); |
|||
switch(type) |
|||
{ |
|||
case I2C_SINGLE: |
|||
return i2c_rec_s(addr,addrlen,reg,buf,count); |
|||
break; |
|||
case I2C_BLOCK: |
|||
return i2c_rec_b(addr,addrlen,reg,buf,count); |
|||
break; |
|||
|
|||
default: return 0;break; |
|||
} |
|||
return 0; |
|||
} |
|||
|
|||
int tgt_i2cwrite(int type,unsigned char *addr,int addrlen,unsigned char reg,unsigned char *buf,int count) |
|||
{ |
|||
tgt_i2cinit(); |
|||
switch(type&0xff) |
|||
{ |
|||
case I2C_SINGLE: |
|||
i2c_send_s(addr,addrlen,reg,buf,count); |
|||
break; |
|||
case I2C_BLOCK: |
|||
return i2c_send_b(addr,addrlen,reg,buf,count); |
|||
break; |
|||
case I2C_SMB_BLOCK: |
|||
break; |
|||
default:return -1;break; |
|||
} |
|||
return -1; |
|||
} |
|||
|
|||
|
|||
int tgt_i2cinit() |
|||
{ |
|||
#if defined(DEVBD2F_SM502) |
|||
pcitag_t tag; |
|||
static int inited=0; |
|||
int tmp; |
|||
if(!inited) |
|||
{ |
|||
tag=_pci_make_tag(0,14,0); |
|||
|
|||
mmio = _pci_conf_readn(tag,0x14,4); |
|||
mmio =(int)mmio|(0xb0000000); |
|||
tmp = *(volatile int *)(mmio + 0x40); |
|||
*(volatile int *)(mmio + 0x40) =tmp|0x40; |
|||
|
|||
// tgt_printf("clock enable bit 40 = %x\n", *(volatile int *)(mmio + 0x40));
|
|||
inited=1; |
|||
} |
|||
#endif |
|||
} |
|||
@ -0,0 +1,129 @@ |
|||
/*
|
|||
* 0 single |
|||
* 1 smb block |
|||
*/ |
|||
int tgt_i2cread(int type,unsigned char *addr,int addrlen,unsigned char reg,unsigned char *buf,int count) |
|||
{ |
|||
int i; |
|||
int device,offset; |
|||
char c; |
|||
device=addr[0]; |
|||
offset=reg; |
|||
device |= 1; |
|||
memset(buf,-1,count); |
|||
switch(type&0xff) |
|||
{ |
|||
case I2C_SINGLE: |
|||
for(i=0;i<count;i++) |
|||
{ |
|||
linux_outb(device,SMBUS_HOST_ADDRESS); |
|||
linux_outb(offset+i,SMBUS_HOST_COMMAND); |
|||
linux_outb(0x8,SMBUS_HOST_CONTROL); |
|||
if((c=linux_inb(SMBUS_HOST_STATUS))&0x1f) |
|||
{ |
|||
linux_outb(c,SMBUS_HOST_STATUS); |
|||
} |
|||
|
|||
linux_outb(linux_inb(SMBUS_HOST_CONTROL)|0x40,SMBUS_HOST_CONTROL); |
|||
|
|||
while(linux_inb(SMBUS_HOST_STATUS)&SMBUS_HOST_STATUS_BUSY); |
|||
|
|||
if((c=linux_inb(SMBUS_HOST_STATUS))&0x1f) |
|||
{ |
|||
linux_outb(c,SMBUS_HOST_STATUS); |
|||
} |
|||
|
|||
buf[i]=linux_inb(SMBUS_HOST_DATA0); |
|||
} |
|||
break; |
|||
case I2C_SMB_BLOCK: |
|||
linux_outb(device,SMBUS_HOST_ADDRESS); //0xd3
|
|||
linux_outb(offset,SMBUS_HOST_COMMAND); |
|||
linux_outb(count,SMBUS_HOST_DATA0); |
|||
linux_outb(0x14,SMBUS_HOST_CONTROL); //0x14
|
|||
if((c=linux_inb(SMBUS_HOST_STATUS))&0x1f) |
|||
{ |
|||
linux_outb(c,SMBUS_HOST_STATUS); |
|||
} |
|||
|
|||
linux_outb(linux_inb(SMBUS_HOST_CONTROL)|0x40,SMBUS_HOST_CONTROL); |
|||
|
|||
while(linux_inb(SMBUS_HOST_STATUS)&SMBUS_HOST_STATUS_BUSY); |
|||
|
|||
if((c=linux_inb(SMBUS_HOST_STATUS))&0x1f) |
|||
{ |
|||
linux_outb(c,SMBUS_HOST_STATUS); |
|||
} |
|||
|
|||
for(i=0;i<count;i++) |
|||
{ |
|||
buf[i]=linux_inb(SMBUS_HOST_DATA1+1); |
|||
} |
|||
break; |
|||
|
|||
default: return 0;break; |
|||
} |
|||
return count; |
|||
} |
|||
|
|||
int tgt_i2cwrite(int type,unsigned char *addr,int addrlen,unsigned char reg,unsigned char *buf,int count) |
|||
{ |
|||
int i; |
|||
int device,offset; |
|||
char c; |
|||
device=addr[0]; |
|||
offset=reg; |
|||
device &= ~1; |
|||
switch(type) |
|||
{ |
|||
case I2C_SINGLE: |
|||
for(i=0;i<count;i++) |
|||
{ |
|||
linux_outb(device,SMBUS_HOST_ADDRESS); |
|||
linux_outb(offset+i,SMBUS_HOST_COMMAND); |
|||
linux_outb(0x8,SMBUS_HOST_CONTROL); |
|||
if((c=linux_inb(SMBUS_HOST_STATUS))&0x1f) |
|||
{ |
|||
linux_outb(c,SMBUS_HOST_STATUS); |
|||
} |
|||
|
|||
linux_outb(buf[i],SMBUS_HOST_DATA0); |
|||
|
|||
linux_outb(linux_inb(SMBUS_HOST_CONTROL)|0x40,SMBUS_HOST_CONTROL); |
|||
|
|||
while(linux_inb(SMBUS_HOST_STATUS)&SMBUS_HOST_STATUS_BUSY); |
|||
|
|||
if((c=linux_inb(SMBUS_HOST_STATUS))&0x1f) |
|||
{ |
|||
linux_outb(c,SMBUS_HOST_STATUS); |
|||
} |
|||
|
|||
} |
|||
break; |
|||
case I2C_SMB_BLOCK: |
|||
linux_outb(device,SMBUS_HOST_ADDRESS); //0xd3
|
|||
linux_outb(offset,SMBUS_HOST_COMMAND); |
|||
linux_outb(count,SMBUS_HOST_DATA0); |
|||
linux_outb(0x14,SMBUS_HOST_CONTROL); //0x14
|
|||
if((c=linux_inb(SMBUS_HOST_STATUS))&0x1f) |
|||
{ |
|||
linux_outb(c,SMBUS_HOST_STATUS); |
|||
} |
|||
|
|||
for(i=0;i<count;i++) |
|||
linux_outb(buf[i],SMBUS_HOST_DATA1+1); |
|||
c=linux_inb(SMBUS_HOST_CONTROL); |
|||
linux_outb(c|0x40,SMBUS_HOST_CONTROL); |
|||
|
|||
while(linux_inb(SMBUS_HOST_STATUS)&SMBUS_HOST_STATUS_BUSY); |
|||
|
|||
if((c=linux_inb(SMBUS_HOST_STATUS))&0x1f) |
|||
{ |
|||
linux_outb(c,SMBUS_HOST_STATUS); |
|||
} |
|||
break; |
|||
default:return -1;break; |
|||
} |
|||
return count; |
|||
} |
|||
|
|||
@ -0,0 +1,64 @@ |
|||
LEAF(i2cread) |
|||
addu a0,a0,1 |
|||
/* set device address */ |
|||
li v0, 0xbfd00000 + SMBUS_HOST_ADDRESS |
|||
|
|||
sb a0, 0(v0); |
|||
|
|||
/* store register offset */ |
|||
li v0, 0xbfd00000 + SMBUS_HOST_COMMAND |
|||
sb a1, 0(v0); |
|||
|
|||
/* read byte data protocol */ |
|||
li v0, 0x08 |
|||
li v1, 0xbfd00000 + SMBUS_HOST_CONTROL |
|||
sb v0, 0(v1); |
|||
|
|||
/* make sure SMB host ready to start, important!--zfx */ |
|||
li v1, 0xbfd00000 + SMBUS_HOST_STATUS |
|||
lbu v0, 0(v1) |
|||
andi v0,v0, 0x1f |
|||
beqz v0,1f |
|||
nop |
|||
sb v0, 0(v1) |
|||
lbu v0, 0(v1) #flush the write |
|||
1: |
|||
|
|||
/* start */ |
|||
li v1, 0xbfd00000 + SMBUS_HOST_CONTROL |
|||
lbu v0, 0(v1) |
|||
ori v0, v0, 0x40 |
|||
sb v0, 0(v1); |
|||
|
|||
/* wait */ |
|||
li v1, 0xbfd00000 + SMBUS_HOST_STATUS |
|||
1: |
|||
|
|||
#if 0 |
|||
/* delay */ |
|||
li a0, 0x1000 |
|||
2: |
|||
bnez a0,2b |
|||
addiu a0, -1 |
|||
#endif |
|||
|
|||
lbu v0, 0(v1) |
|||
andi v0, SMBUS_HOST_STATUS_BUSY |
|||
bnez v0, 1b #IDEL ? |
|||
nop |
|||
|
|||
li v1, 0xbfd00000 + SMBUS_HOST_STATUS |
|||
lbu v0, 0(v1) |
|||
andi v0,v0, 0x1f |
|||
beqz v0,1f |
|||
nop |
|||
sb v0, 0(v1) #reset |
|||
lbu v0, 0(v1) #flush the write |
|||
1: |
|||
|
|||
li v1, 0xbfd00000 + SMBUS_HOST_DATA0 |
|||
lbu v0, 0(v1) |
|||
|
|||
jr ra |
|||
nop |
|||
END(i2cread) |
|||
@ -0,0 +1,618 @@ |
|||
#define GPIO_DIR_HIGH (0xbfe00120) |
|||
#define GPIO_DATA_HIGH (0xbfe0011c) |
|||
#define G_OUTPUT 0 |
|||
#define G_INPUT 1 |
|||
|
|||
#define GPIO_SDA_DIR_SHIFT 2 |
|||
#define GPIO_SCL_DIR_SHIFT 3 |
|||
#define GPIO_SDA_DATA_SHIFT 2 |
|||
#define GPIO_SCL_DATA_SHIFT 3 |
|||
|
|||
/* |
|||
can't use t1,t5,t6 |
|||
|
|||
*/ |
|||
|
|||
LEAF(_i2c_sleep) |
|||
// |
|||
// li t0,0x300 |
|||
li t0,0x3 |
|||
sll a0,t0,a0 |
|||
|
|||
1: nop |
|||
subu a0,1 |
|||
bnez a0,1b |
|||
nop |
|||
|
|||
jr ra |
|||
nop |
|||
|
|||
END(_i2c_sleep) |
|||
|
|||
LEAF(_sda_dir) |
|||
li t0,GPIO_DIR_HIGH |
|||
lwu t2,0(t0) |
|||
nop |
|||
|
|||
beqz a0,1f |
|||
nop |
|||
ori t2,t2,0x1<<GPIO_SDA_DIR_SHIFT |
|||
b 2f |
|||
nop |
|||
|
|||
1: li t3,~(0x1<<GPIO_SDA_DIR_SHIFT) |
|||
and t2,t2,t3 |
|||
2: sw t2,0(t0) |
|||
|
|||
nop |
|||
jr ra |
|||
nop |
|||
|
|||
END(_sda_dir) |
|||
|
|||
LEAF(_scl_dir) |
|||
li t0,GPIO_DIR_HIGH |
|||
lwu t2,0(t0) |
|||
nop |
|||
|
|||
beqz a0,1f |
|||
nop |
|||
ori t2,t2,0x1<<GPIO_SCL_DIR_SHIFT |
|||
b 2f |
|||
nop |
|||
|
|||
1: li t3,~(0x1<<GPIO_SCL_DIR_SHIFT) |
|||
and t2,t2,t3 |
|||
2: sw t2,0(t0) |
|||
|
|||
nop |
|||
jr ra |
|||
nop |
|||
|
|||
END(_scl_dir) |
|||
|
|||
LEAF(_sda_bit) |
|||
li t0,GPIO_DATA_HIGH |
|||
lwu t2,0(t0) |
|||
nop |
|||
|
|||
beqz a0,1f |
|||
nop |
|||
ori t2,t2,0x1<<GPIO_SDA_DATA_SHIFT |
|||
b 2f |
|||
nop |
|||
|
|||
1: li t3,~(0x1<<GPIO_SDA_DATA_SHIFT) |
|||
and t2,t2,t3 |
|||
2: sw t2,0(t0) |
|||
|
|||
nop |
|||
jr ra |
|||
nop |
|||
END(_sda_bit) |
|||
|
|||
LEAF(_scl_bit) |
|||
li t0,GPIO_DATA_HIGH |
|||
lwu t2,0(t0) |
|||
nop |
|||
|
|||
beqz a0,1f |
|||
nop |
|||
ori t2,t2,0x1<<GPIO_SCL_DATA_SHIFT |
|||
b 2f |
|||
nop |
|||
|
|||
1: li t3,~(0x1<<GPIO_SCL_DATA_SHIFT) |
|||
and t2,t2,t3 |
|||
2: sw t2,0(t0) |
|||
|
|||
nop |
|||
jr ra |
|||
nop |
|||
END(_sda_bit) |
|||
|
|||
|
|||
LEAF(_i2c_start) |
|||
move t7,ra |
|||
|
|||
|
|||
li a0,G_OUTPUT |
|||
bal _sda_dir |
|||
nop |
|||
li a0,G_OUTPUT |
|||
bal _scl_dir |
|||
nop |
|||
li a0,0 |
|||
bal _scl_bit |
|||
nop |
|||
li a0,1 |
|||
bal _i2c_sleep |
|||
nop |
|||
li a0,1 |
|||
bal _sda_bit |
|||
nop |
|||
|
|||
li a0,1 |
|||
bal _i2c_sleep |
|||
nop |
|||
li a0,1 |
|||
bal _scl_bit |
|||
nop |
|||
li a0,5 |
|||
bal _i2c_sleep |
|||
nop |
|||
li a0,0 |
|||
bal _sda_bit |
|||
nop |
|||
li a0,5 |
|||
bal _i2c_sleep |
|||
nop |
|||
li a0,0 |
|||
bal _scl_bit |
|||
nop |
|||
li a0,2 |
|||
bal _i2c_sleep |
|||
nop |
|||
|
|||
jr t7 |
|||
nop |
|||
|
|||
END(_i2c_start) |
|||
|
|||
LEAF(_i2c_stop) |
|||
move t7,ra |
|||
|
|||
li a0,G_OUTPUT |
|||
bal _sda_dir |
|||
nop |
|||
li a0,G_OUTPUT |
|||
bal _scl_dir |
|||
nop |
|||
li a0,0 |
|||
bal _scl_bit |
|||
nop |
|||
li a0,1 |
|||
bal _i2c_sleep |
|||
nop |
|||
li a0,0 |
|||
bal _sda_bit |
|||
nop |
|||
li a0,1 |
|||
bal _i2c_sleep |
|||
nop |
|||
li a0,1 |
|||
bal _scl_bit |
|||
nop |
|||
li a0,5 |
|||
bal _i2c_sleep |
|||
nop |
|||
li a0,1 |
|||
bal _sda_bit |
|||
nop |
|||
li a0,5 |
|||
bal _i2c_sleep |
|||
nop |
|||
li a0,0 |
|||
bal _scl_bit |
|||
nop |
|||
li a0,2 |
|||
bal _i2c_sleep |
|||
nop |
|||
|
|||
jr t7 |
|||
nop |
|||
END(_i2c_stop) |
|||
LEAF(_i2c_send_ack) |
|||
|
|||
move t7,ra |
|||
move t4,a0 |
|||
|
|||
li a0,G_OUTPUT |
|||
bal _sda_dir |
|||
nop |
|||
move a0,t4 |
|||
bal _sda_bit |
|||
nop |
|||
li a0,3 |
|||
bal _i2c_sleep |
|||
nop |
|||
li a0,1 |
|||
bal _scl_bit |
|||
nop |
|||
li a0,5 |
|||
bal _i2c_sleep |
|||
nop |
|||
li a0,0 |
|||
bal _scl_bit |
|||
nop |
|||
li a0,2 |
|||
bal _i2c_sleep |
|||
nop |
|||
|
|||
jr t7 |
|||
nop |
|||
END(_i2c_send_ack) |
|||
|
|||
LEAF(_i2c_rec_ack) |
|||
move t7,ra |
|||
li v0,1 |
|||
li t4,10 |
|||
|
|||
li a0,G_INPUT |
|||
bal _sda_dir |
|||
nop |
|||
li a0,3 |
|||
bal _i2c_sleep |
|||
nop |
|||
li a0,1 |
|||
bal _scl_bit |
|||
nop |
|||
li a0,5 |
|||
bal _i2c_sleep |
|||
nop |
|||
#ifdef DEVBD2F_SM502 |
|||
li t9,GPIO_DATA_HIGH |
|||
lwu t9,0(t9) |
|||
nop |
|||
andi t9,t9,0x1<<GPIO_SDA_DATA_SHIFT |
|||
#elif DEVBD2F_FIREWALL |
|||
li t9,GPIO_DATA_HIGH |
|||
lwu t9,0(t9) |
|||
nop |
|||
srl t9,t9,16 |
|||
andi t9,t9,0x1<<(GPIO_SDA_DATA_SHIFT) |
|||
|
|||
#endif |
|||
|
|||
2: beqz t9,1f |
|||
nop |
|||
li a0,1 |
|||
bal _i2c_sleep |
|||
nop |
|||
subu t4,t4,1 |
|||
|
|||
bnez t4,3f |
|||
nop |
|||
li v0,0 |
|||
b 1f |
|||
nop |
|||
|
|||
#ifdef DEVBD2F_SM502 |
|||
3: li t9,GPIO_DATA_HIGH |
|||
lwu t9,0(t9) |
|||
nop |
|||
andi t9,t9,0x1<<GPIO_SDA_DATA_SHIFT |
|||
#elif DEVBD2F_FIREWALL |
|||
3: li t9,GPIO_DATA_HIGH |
|||
lwu t9,0(t9) |
|||
nop |
|||
srl t9,t9,16 |
|||
andi t9,t9,0x1<<(GPIO_SDA_DATA_SHIFT) |
|||
#endif |
|||
b 2b |
|||
nop |
|||
|
|||
|
|||
1: li a0,0 |
|||
bal _scl_bit |
|||
nop |
|||
li a0,3 |
|||
bal _i2c_sleep |
|||
nop |
|||
|
|||
jr t7 |
|||
nop |
|||
|
|||
END(_i2c_rec_ack) |
|||
|
|||
|
|||
LEAF(_i2c_rec) |
|||
move t7,ra |
|||
li t9,0x7 |
|||
li v0,0 |
|||
li a0,G_INPUT |
|||
bal _sda_dir |
|||
nop |
|||
|
|||
2: bltz t9,1f |
|||
nop |
|||
|
|||
|
|||
|
|||
li a0,5 |
|||
bal _i2c_sleep |
|||
nop |
|||
li a0,1 |
|||
bal _scl_bit |
|||
nop |
|||
li a0,3 |
|||
bal _i2c_sleep |
|||
nop |
|||
#ifdef DEVBD2F_SM502 |
|||
li t4,GPIO_DATA_HIGH |
|||
lwu t4,0(t4) |
|||
nop |
|||
andi t4,t4,0x1<<GPIO_SDA_DATA_SHIFT |
|||
#elif DEVBD2F_FIREWALL |
|||
li t4,GPIO_DATA_HIGH |
|||
lwu t4,0(t4) |
|||
nop |
|||
srl t4,t4,16 |
|||
andi t4,t4,0x1<<(GPIO_SDA_DATA_SHIFT) |
|||
|
|||
#endif |
|||
beqz t4,3f |
|||
nop |
|||
li t4,1 |
|||
|
|||
3: sll t4,t4,t9 |
|||
or v0,v0,t4 |
|||
li a0,3 |
|||
bal _i2c_sleep |
|||
nop |
|||
li a0,0 |
|||
bal _scl_bit |
|||
nop |
|||
|
|||
sub t9,t9,1 |
|||
b 2b |
|||
nop |
|||
|
|||
1: jr t7 |
|||
nop |
|||
|
|||
END(_i2c_rec) |
|||
|
|||
LEAF(_i2c_send) |
|||
move t7,ra |
|||
move t4,a0 |
|||
li t9,0x7 |
|||
|
|||
li a0,G_OUTPUT |
|||
bal _sda_dir |
|||
nop |
|||
|
|||
2: bltz t9,1f |
|||
nop |
|||
|
|||
move a0,t4 |
|||
srl a0,a0,t9 |
|||
andi a0,a0,1 |
|||
bal _sda_bit |
|||
nop |
|||
|
|||
li a0,1 |
|||
bal _i2c_sleep |
|||
nop |
|||
li a0,1 |
|||
bal _scl_bit |
|||
nop |
|||
li a0,5 |
|||
bal _i2c_sleep |
|||
nop |
|||
li a0,0 |
|||
bal _scl_bit |
|||
nop |
|||
li a0,1 |
|||
bal _i2c_sleep |
|||
nop |
|||
|
|||
sub t9,t9,1 |
|||
b 2b |
|||
nop |
|||
1: li a0,1 |
|||
bal _sda_bit |
|||
nop |
|||
|
|||
jr t7 |
|||
nop |
|||
|
|||
END(_i2c_send) |
|||
|
|||
/* |
|||
a0,a2:slave device addr |
|||
a1,a3:sub addr |
|||
v0:recieve data |
|||
v1:show if sucess,0:sucess,1:failure |
|||
*/ |
|||
LEAF(i2cread) |
|||
move t8,ra |
|||
nop |
|||
move a2,a0 |
|||
move a3,a1 |
|||
li v0,0 |
|||
li v1,0 |
|||
|
|||
|
|||
bal _i2c_start |
|||
nop |
|||
|
|||
move a0,a2 |
|||
bal _i2c_send |
|||
nop |
|||
|
|||
bal _i2c_rec_ack |
|||
nop |
|||
beqz v0,1f |
|||
nop |
|||
#if 0 |
|||
|
|||
li a0,0 |
|||
bal _i2c_send |
|||
nop |
|||
|
|||
|
|||
bal _i2c_rec_ack |
|||
nop |
|||
beqz v0,1f |
|||
nop |
|||
#endif |
|||
|
|||
move a0,a3 |
|||
bal _i2c_send |
|||
nop |
|||
|
|||
|
|||
bal _i2c_rec_ack |
|||
nop |
|||
beqz v0,1f |
|||
nop |
|||
|
|||
|
|||
bal _i2c_start |
|||
nop |
|||
|
|||
move a0,a2 |
|||
addu a0,a0,1 |
|||
bal _i2c_send |
|||
nop |
|||
|
|||
|
|||
bal _i2c_rec_ack |
|||
nop |
|||
beqz v0,1f |
|||
nop |
|||
|
|||
bal _i2c_rec |
|||
nop |
|||
/* |
|||
move k0,v0 |
|||
|
|||
li a0,1 |
|||
bal _i2c_send_ack |
|||
nop |
|||
*/ |
|||
bal _i2c_stop |
|||
nop |
|||
|
|||
li v1,0 |
|||
// move v0,k0 |
|||
b 2f |
|||
nop |
|||
|
|||
1: li v1,1 |
|||
2: jr t8 |
|||
nop |
|||
|
|||
|
|||
END(i2cread) |
|||
|
|||
|
|||
/* |
|||
*a0: slave_addr |
|||
*a1: sub_addr |
|||
*a2: value |
|||
*/ |
|||
LEAF(i2cwrite) |
|||
move t8,ra |
|||
nop |
|||
move a3,a0 |
|||
|
|||
bal _i2c_start |
|||
nop |
|||
|
|||
move a0,a3 |
|||
bal _i2c_send |
|||
nop |
|||
|
|||
bal _i2c_rec_ack |
|||
nop |
|||
beqz v0,1f |
|||
nop |
|||
//for write isl12027 watchdog |
|||
#if 1 |
|||
|
|||
li a0,0 |
|||
bal _i2c_send |
|||
nop |
|||
|
|||
|
|||
bal _i2c_rec_ack |
|||
nop |
|||
beqz v0,1f |
|||
nop |
|||
#endif |
|||
|
|||
|
|||
move a0,a1 |
|||
bal _i2c_send |
|||
nop |
|||
|
|||
|
|||
bal _i2c_rec_ack |
|||
nop |
|||
beqz v0,1f |
|||
nop |
|||
|
|||
move a0,a2 |
|||
bal _i2c_send |
|||
nop |
|||
|
|||
bal _i2c_rec_ack |
|||
nop |
|||
beqz v0,1f |
|||
nop |
|||
|
|||
bal _i2c_stop |
|||
nop |
|||
|
|||
b 2f |
|||
nop |
|||
|
|||
1: li v1,1 |
|||
2: jr t8 |
|||
nop |
|||
|
|||
END(i2cwrite) |
|||
|
|||
LEAF(isl12027_watchdog) |
|||
move t1,ra |
|||
|
|||
li a0,0xde |
|||
li a1,0x3f |
|||
li a2,0x2 |
|||
bal i2cwrite |
|||
nop |
|||
|
|||
//PRINTSTR("setp1\r\n") |
|||
li a0,0xde |
|||
li a1,0x3f |
|||
li a2,0x6 |
|||
bal i2cwrite |
|||
nop |
|||
|
|||
//PRINTSTR("setp2\r\n") |
|||
li a0,0xde |
|||
li a1,0x14 |
|||
li a2,0x84 |
|||
bal i2cwrite |
|||
nop |
|||
|
|||
//PRINTSTR("setp3\r\n") |
|||
|
|||
|
|||
li a0,0xde |
|||
li a1,0x3f |
|||
li a2,0x2 |
|||
bal i2cwrite |
|||
nop |
|||
|
|||
//PRINTSTR("setp1\r\n") |
|||
li a0,0xde |
|||
li a1,0x3f |
|||
li a2,0x6 |
|||
bal i2cwrite |
|||
nop |
|||
|
|||
//PRINTSTR("setp2\r\n") |
|||
li a0,0xde |
|||
li a1,0x10 |
|||
li a2,0x18 |
|||
bal i2cwrite |
|||
nop |
|||
|
|||
//PRINTSTR("setp3\r\n") |
|||
jr t1 |
|||
nop |
|||
|
|||
END(isl12027_watchdog) |
|||
@ -0,0 +1,456 @@ |
|||
#define GPIO_DIR_HIGH (MMIO_BASE+0x0001000c) |
|||
#define GPIO_DATA_HIGH (MMIO_BASE+0x00010004) |
|||
#define G_OUTPUT 1 |
|||
#define G_INPUT 0 |
|||
/* |
|||
can't use t1,t5,t6 |
|||
|
|||
*/ |
|||
|
|||
LEAF(_i2c_sleep) |
|||
// |
|||
// li t0,0x300 |
|||
li t0,0x10 |
|||
sll a0,t0,a0 |
|||
|
|||
1: nop |
|||
subu a0,1 |
|||
bnez a0,1b |
|||
nop |
|||
|
|||
jr ra |
|||
nop |
|||
|
|||
END(_i2c_sleep) |
|||
|
|||
LEAF(_sda_dir) |
|||
li t0,GPIO_DIR_HIGH |
|||
lwu t2,0(t0) |
|||
nop |
|||
|
|||
beqz a0,1f |
|||
nop |
|||
ori t2,t2,0x8000 |
|||
b 2f |
|||
nop |
|||
|
|||
1: li t3,~(0x8000) |
|||
and t2,t2,t3 |
|||
2: sw t2,0(t0) |
|||
|
|||
nop |
|||
jr ra |
|||
nop |
|||
|
|||
END(_sda_dir) |
|||
|
|||
LEAF(_scl_dir) |
|||
li t0,GPIO_DIR_HIGH; |
|||
lwu t2,0(t0) |
|||
nop |
|||
|
|||
beqz a0,1f |
|||
nop |
|||
ori t2,t2,0x4000 |
|||
b 2f |
|||
nop |
|||
|
|||
1: li t3,~(0x4000) |
|||
and t2,t2,t3 |
|||
2: sw t2,0(t0) |
|||
|
|||
nop |
|||
jr ra |
|||
nop |
|||
|
|||
END(_scl_dir) |
|||
|
|||
LEAF(_sda_bit) |
|||
li t0,GPIO_DATA_HIGH; |
|||
lwu t2,0(t0) |
|||
nop |
|||
|
|||
beqz a0,1f |
|||
nop |
|||
ori t2,t2,0x8000 |
|||
b 2f |
|||
nop |
|||
|
|||
1: li t3,~(0x8000) |
|||
and t2,t2,t3 |
|||
2: sw t2,0(t0) |
|||
|
|||
nop |
|||
jr ra |
|||
nop |
|||
END(_sda_bit) |
|||
|
|||
LEAF(_scl_bit) |
|||
li t0,GPIO_DATA_HIGH; |
|||
lwu t2,0(t0) |
|||
nop |
|||
|
|||
beqz a0,1f |
|||
nop |
|||
ori t2,t2,0x4000 |
|||
b 2f |
|||
nop |
|||
|
|||
1: li t3,~(0x4000) |
|||
and t2,t2,t3 |
|||
2: sw t2,0(t0) |
|||
|
|||
nop |
|||
jr ra |
|||
nop |
|||
END(_sda_bit) |
|||
|
|||
|
|||
LEAF(_i2c_start) |
|||
move t7,ra |
|||
|
|||
|
|||
li a0,G_OUTPUT |
|||
bal _sda_dir |
|||
nop |
|||
li a0,G_OUTPUT |
|||
bal _scl_dir |
|||
nop |
|||
li a0,0 |
|||
bal _scl_bit |
|||
nop |
|||
li a0,1 |
|||
bal _i2c_sleep |
|||
nop |
|||
li a0,1 |
|||
bal _sda_bit |
|||
nop |
|||
|
|||
li a0,1 |
|||
bal _i2c_sleep |
|||
nop |
|||
li a0,1 |
|||
bal _scl_bit |
|||
nop |
|||
li a0,5 |
|||
bal _i2c_sleep |
|||
nop |
|||
li a0,0 |
|||
bal _sda_bit |
|||
nop |
|||
li a0,5 |
|||
bal _i2c_sleep |
|||
nop |
|||
li a0,0 |
|||
bal _scl_bit |
|||
nop |
|||
li a0,2 |
|||
bal _i2c_sleep |
|||
nop |
|||
|
|||
jr t7 |
|||
nop |
|||
|
|||
END(_i2c_start) |
|||
|
|||
LEAF(_i2c_stop) |
|||
move t7,ra |
|||
|
|||
li a0,G_OUTPUT |
|||
bal _sda_dir |
|||
nop |
|||
li a0,G_OUTPUT |
|||
bal _scl_dir |
|||
nop |
|||
li a0,0 |
|||
bal _scl_bit |
|||
nop |
|||
li a0,1 |
|||
bal _i2c_sleep |
|||
nop |
|||
li a0,0 |
|||
bal _sda_bit |
|||
nop |
|||
li a0,1 |
|||
bal _i2c_sleep |
|||
nop |
|||
li a0,1 |
|||
bal _scl_bit |
|||
nop |
|||
li a0,5 |
|||
bal _i2c_sleep |
|||
nop |
|||
li a0,1 |
|||
bal _sda_bit |
|||
nop |
|||
li a0,5 |
|||
bal _i2c_sleep |
|||
nop |
|||
li a0,0 |
|||
bal _scl_bit |
|||
nop |
|||
li a0,2 |
|||
bal _i2c_sleep |
|||
nop |
|||
|
|||
jr t7 |
|||
nop |
|||
END(_i2c_stop) |
|||
LEAF(_i2c_send_ack) |
|||
|
|||
move t7,ra |
|||
move t4,a0 |
|||
|
|||
li a0,G_OUTPUT |
|||
bal _sda_dir |
|||
nop |
|||
move a0,t4 |
|||
bal _sda_bit |
|||
nop |
|||
li a0,3 |
|||
bal _i2c_sleep |
|||
nop |
|||
li a0,1 |
|||
bal _scl_bit |
|||
nop |
|||
li a0,5 |
|||
bal _i2c_sleep |
|||
nop |
|||
li a0,0 |
|||
bal _scl_bit |
|||
nop |
|||
li a0,2 |
|||
bal _i2c_sleep |
|||
nop |
|||
|
|||
jr t7 |
|||
nop |
|||
END(_i2c_send_ack) |
|||
|
|||
LEAF(_i2c_rec_ack) |
|||
move t7,ra |
|||
li v0,1 |
|||
li t4,10 |
|||
|
|||
li a0,G_INPUT |
|||
bal _sda_dir |
|||
nop |
|||
li a0,3 |
|||
bal _i2c_sleep |
|||
nop |
|||
li a0,1 |
|||
bal _scl_bit |
|||
nop |
|||
li a0,5 |
|||
bal _i2c_sleep |
|||
nop |
|||
li t9,GPIO_DATA_HIGH |
|||
lwu t9,0(t9) |
|||
nop |
|||
andi t9,t9,0x8000 |
|||
|
|||
2: beqz t9,1f |
|||
nop |
|||
li a0,1 |
|||
bal _i2c_sleep |
|||
nop |
|||
subu t4,t4,1 |
|||
|
|||
bnez t4,3f |
|||
nop |
|||
li v0,0 |
|||
b 1f |
|||
nop |
|||
|
|||
3: li t9,GPIO_DATA_HIGH |
|||
lwu t9,0(t9) |
|||
nop |
|||
andi t9,t9,0x8000 |
|||
b 2b |
|||
nop |
|||
|
|||
|
|||
1: li a0,0 |
|||
bal _scl_bit |
|||
nop |
|||
li a0,3 |
|||
bal _i2c_sleep |
|||
nop |
|||
|
|||
jr t7 |
|||
nop |
|||
|
|||
END(_i2c_rec_ack) |
|||
|
|||
|
|||
LEAF(_i2c_rec) |
|||
move t7,ra |
|||
li t9,0x7 |
|||
li v0,0 |
|||
li a0,G_INPUT |
|||
bal _sda_dir |
|||
nop |
|||
|
|||
2: bltz t9,1f |
|||
nop |
|||
|
|||
|
|||
|
|||
li a0,5 |
|||
bal _i2c_sleep |
|||
nop |
|||
li a0,1 |
|||
bal _scl_bit |
|||
nop |
|||
li a0,3 |
|||
bal _i2c_sleep |
|||
nop |
|||
li t4,GPIO_DATA_HIGH |
|||
lwu t4,0(t4) |
|||
nop |
|||
andi t4,t4,0x8000 |
|||
|
|||
beqz t4,3f |
|||
nop |
|||
li t4,1 |
|||
|
|||
3: sll t4,t4,t9 |
|||
or v0,v0,t4 |
|||
li a0,3 |
|||
bal _i2c_sleep |
|||
nop |
|||
li a0,0 |
|||
bal _scl_bit |
|||
nop |
|||
|
|||
sub t9,t9,1 |
|||
b 2b |
|||
nop |
|||
|
|||
1: jr t7 |
|||
nop |
|||
|
|||
END(_i2c_rec) |
|||
|
|||
LEAF(_i2c_send) |
|||
move t7,ra |
|||
move t4,a0 |
|||
li t9,0x7 |
|||
|
|||
li a0,G_OUTPUT |
|||
bal _sda_dir |
|||
nop |
|||
|
|||
2: bltz t9,1f |
|||
nop |
|||
|
|||
move a0,t4 |
|||
srl a0,a0,t9 |
|||
andi a0,a0,1 |
|||
bal _sda_bit |
|||
nop |
|||
|
|||
li a0,1 |
|||
bal _i2c_sleep |
|||
nop |
|||
li a0,1 |
|||
bal _scl_bit |
|||
nop |
|||
li a0,5 |
|||
bal _i2c_sleep |
|||
nop |
|||
li a0,0 |
|||
bal _scl_bit |
|||
nop |
|||
li a0,1 |
|||
bal _i2c_sleep |
|||
nop |
|||
|
|||
sub t9,t9,1 |
|||
b 2b |
|||
nop |
|||
1: li a0,1 |
|||
bal _sda_bit |
|||
nop |
|||
|
|||
jr t7 |
|||
nop |
|||
|
|||
END(_i2c_send) |
|||
|
|||
/* |
|||
a0,a2:slave device addr |
|||
a1,a3:sub addr |
|||
v0:recieve data |
|||
v1:show if sucess,0:sucess,1:failure |
|||
*/ |
|||
LEAF(i2cread) |
|||
move t8,ra |
|||
nop |
|||
move a2,a0 |
|||
move a3,a1 |
|||
li v0,0 |
|||
li v1,0 |
|||
|
|||
|
|||
bal _i2c_start |
|||
nop |
|||
|
|||
move a0,a2 |
|||
bal _i2c_send |
|||
nop |
|||
|
|||
bal _i2c_rec_ack |
|||
nop |
|||
beqz v0,1f |
|||
nop |
|||
|
|||
move a0,a3 |
|||
bal _i2c_send |
|||
nop |
|||
beqz v0,1f |
|||
nop |
|||
|
|||
bal _i2c_rec_ack |
|||
nop |
|||
beqz v0,1f |
|||
nop |
|||
|
|||
|
|||
bal _i2c_start |
|||
nop |
|||
|
|||
move a0,a2 |
|||
addu a0,a0,1 |
|||
bal _i2c_send |
|||
nop |
|||
beqz v0,1f |
|||
nop |
|||
|
|||
bal _i2c_rec_ack |
|||
nop |
|||
beqz v0,1f |
|||
nop |
|||
|
|||
bal _i2c_rec |
|||
nop |
|||
move k0,v0 |
|||
|
|||
li a0,1 |
|||
bal _i2c_send_ack |
|||
nop |
|||
bal _i2c_stop |
|||
nop |
|||
|
|||
li v1,0 |
|||
move v0,k0 |
|||
b 2f |
|||
nop |
|||
|
|||
1: li v1,1 |
|||
2: jr t8 |
|||
nop |
|||
|
|||
|
|||
END(i2cread) |
|||
|
|||
@ -0,0 +1,407 @@ |
|||
li k0,0 |
|||
li k1,0 |
|||
li msize,0 |
|||
PRINTSTR("DIMM read\r\n") |
|||
|
|||
li a1, 0x0 |
|||
li a0,0xa0 |
|||
bal i2cread |
|||
nop |
|||
beq v0,0xff,1f |
|||
nop |
|||
beq v0,0x80,1f |
|||
nop |
|||
move a0,v0 |
|||
// bal hexserial |
|||
nop |
|||
PRINTSTR ("\r\nNo DIMM in slot 0 \r\n"); |
|||
b 2f |
|||
nop |
|||
1: |
|||
li a0,0xa0 |
|||
bal ii2c_cfg |
|||
nop |
|||
2: |
|||
li a1, 0x0 |
|||
li a0,0xa2 |
|||
bal i2cread |
|||
nop |
|||
li a1,0x0 |
|||
beq v0,0xff,1f |
|||
nop |
|||
beq v0,0x80,1f |
|||
nop |
|||
move a0,v0 |
|||
// bal hexserial |
|||
nop |
|||
PRINTSTR ("\r\nNo DIMM in slot 1 \r\n"); |
|||
b 2f |
|||
nop |
|||
1: |
|||
li a0,0xa2 |
|||
bal ii2c_cfg |
|||
nop |
|||
|
|||
b 2f |
|||
nop |
|||
|
|||
2: |
|||
b 211f |
|||
nop |
|||
/*ic2 cfg |
|||
* a0=0xa0 for slot 0,a0=0xa2 for slot 1 |
|||
* t5 used for save i2c addr a0,t6 save ra. |
|||
* use t1 |
|||
*/ |
|||
LEAF(ii2c_cfg) |
|||
move t6,ra |
|||
move t5,a0 |
|||
|
|||
#ifdef I2C_DEBUG |
|||
li t1,0 |
|||
1: |
|||
move a1,t1 |
|||
move a0,t5 |
|||
bal i2cread |
|||
nop |
|||
|
|||
#print |
|||
move a0, v0 |
|||
bal hexserial |
|||
nop |
|||
PRINTSTR("\r\n") |
|||
addiu t1,t1,1 |
|||
li v0, 0x20 |
|||
bleu t1, v0, 1b |
|||
nop |
|||
#endif |
|||
|
|||
# set some parameters for DDR333 |
|||
# rank number and DDR type field will be filled later |
|||
# to check: fix TCAS? |
|||
|
|||
|
|||
PRINTSTR("read memory type\r\n") |
|||
|
|||
/* read DIMM number of rows */ |
|||
move a0,t5 /* #zgj-11-17 */ |
|||
li a1,3 |
|||
bal i2cread |
|||
nop |
|||
move s6,v0 |
|||
move a0, v0 |
|||
subu v0, 12 |
|||
bgtu v0, 2,.nodimm1 |
|||
nop |
|||
move t1, v0 |
|||
PRINTSTR("read number of rows :"); |
|||
move a0,s6 |
|||
bal hexserial |
|||
nop |
|||
|
|||
2: /* read DIMM number of cols */ |
|||
|
|||
move a0,t5 /* #zgj-11-17 */ |
|||
li a1,4 |
|||
bal i2cread |
|||
nop |
|||
////////////////////// |
|||
move a0,v0 |
|||
dsll a0,a0,32 |
|||
daddu s6,a0 |
|||
///////////////////// |
|||
subu v0, 8 |
|||
bgtu v0, 4,.nodimm1 |
|||
nop |
|||
|
|||
bne t1, 0, 10f |
|||
nop |
|||
bne v0, 2, 20f |
|||
nop |
|||
li v0, 0 |
|||
b .ddrtype1 |
|||
nop |
|||
|
|||
20: bne v0, 1, 21f |
|||
nop |
|||
li v0, 1 |
|||
b .ddrtype1 |
|||
nop |
|||
21: bne v0, 0, 22f |
|||
nop |
|||
|
|||
li v0, 2 |
|||
b .ddrtype1 |
|||
nop |
|||
22: bne v0, 3, 33f |
|||
nop |
|||
li v0, 3 |
|||
b .ddrtype1 |
|||
nop |
|||
10: bne t1, 1, 11f |
|||
nop |
|||
bne v0, 3, 20f |
|||
nop |
|||
li v0, 4 |
|||
b .ddrtype1 |
|||
nop |
|||
20: bne v0, 2, 21f |
|||
nop |
|||
li v0, 5 |
|||
b .ddrtype1 |
|||
nop |
|||
21: bne v0, 1, 22f |
|||
nop |
|||
li v0, 6 |
|||
b .ddrtype1 |
|||
nop |
|||
22: bne v0, 4, 33f |
|||
nop |
|||
li v0, 7 |
|||
b .ddrtype1 |
|||
nop |
|||
11: bne t1, 2, 33f |
|||
nop |
|||
bne v0, 4, 20f |
|||
nop |
|||
li v0, 8 |
|||
b .ddrtype1 |
|||
nop |
|||
20: bne v0, 3, 21f |
|||
nop |
|||
li v0, 9 |
|||
b .ddrtype1 |
|||
nop |
|||
21: bne v0, 2, 33f |
|||
nop |
|||
li v0, 10 |
|||
b .ddrtype1 |
|||
nop |
|||
33: PRINTSTR("DDR type not supported!\r\n"); |
|||
34: b 34b |
|||
nop |
|||
|
|||
.ddrtype1: |
|||
|
|||
move a0,t5 |
|||
li a1,17 |
|||
bal i2cread |
|||
nop |
|||
beq v0,4,2f |
|||
nop |
|||
bne v0,8,.nodimm1 |
|||
li k0,1 |
|||
nop |
|||
2: |
|||
|
|||
PRINTSTR("\r\nnumber of ranks ,package and height\r\n") ; |
|||
PRINTSTR("k1 to save cs_map filed valule\r\n") ; |
|||
move a0,t5 |
|||
li a1,5 |
|||
bal i2cread |
|||
nop |
|||
//*********** |
|||
andi v0,v0,0x7 |
|||
//*********** |
|||
beq v0,0,2f |
|||
nop |
|||
bne v0,1,.nodimm1 |
|||
nop |
|||
|
|||
//************ |
|||
bne t5,0xa0,123f |
|||
nop |
|||
ori k1,k1,0x3 |
|||
b 124f |
|||
nop |
|||
|
|||
123: ori k1,k1,0xc |
|||
|
|||
124: b 124f |
|||
nop |
|||
|
|||
|
|||
|
|||
2: bne t5,0xa0,123f |
|||
nop |
|||
ori k1,k1,0x1 |
|||
b 124f |
|||
nop |
|||
|
|||
123: ori k1,k1,0x4 |
|||
124: nop |
|||
|
|||
//************ |
|||
|
|||
|
|||
|
|||
/* read DIMM width */ |
|||
move a0,t5 |
|||
li a1,6 |
|||
|
|||
bal i2cread |
|||
nop |
|||
bleu v0,36,2f |
|||
nop |
|||
bgtu v0,72,.nodimm1 |
|||
nop |
|||
PRINTSTR("read width\r\n") ; |
|||
2: |
|||
PRINTSTR("module rank density\r\n") ; |
|||
move a0,t5 |
|||
li a1,31 |
|||
bal i2cread |
|||
nop |
|||
beqz v0,.nodimm1 |
|||
nop |
|||
//////////////////// |
|||
beq v0,0x80,1f |
|||
nop |
|||
beq v0,0x40,2f |
|||
nop |
|||
beq v0,0x20,3f |
|||
nop |
|||
beq v0,0x10,4f |
|||
nop |
|||
beq v0,0x08,5f |
|||
nop |
|||
beq v0,0x04,6f |
|||
nop |
|||
beq v0,0x02,7f |
|||
nop |
|||
li tmpsize,1<<10 |
|||
b 100f |
|||
nop |
|||
|
|||
7: li tmpsize,2<<10 |
|||
b 100f |
|||
nop |
|||
6: li tmpsize,4<<10 |
|||
b 100f |
|||
nop |
|||
5: li tmpsize,8<<10 |
|||
b 100f |
|||
nop |
|||
4: li tmpsize,16<<10 |
|||
b 100f |
|||
nop |
|||
3: li tmpsize,128 |
|||
b 100f |
|||
nop |
|||
2: li tmpsize,256 |
|||
b 100f |
|||
nop |
|||
1: li tmpsize,512 |
|||
|
|||
//////////////// |
|||
100: addu msize,tmpsize |
|||
|
|||
|
|||
PRINTSTR("sizing slot memory size\r\n") ; |
|||
move a0,t5 |
|||
li a1,5 |
|||
bal i2cread |
|||
nop |
|||
andi v0,0x7 |
|||
2: beq v0,0,1f |
|||
nop |
|||
addu msize,tmpsize |
|||
subu v0,v0,1 |
|||
|
|||
b 2b |
|||
nop |
|||
|
|||
.nodimm1: |
|||
PRINTSTR ("\r\nNo DIMM in this slot "); |
|||
1: |
|||
jr t6 |
|||
nop |
|||
END(ii2c_cfg) |
|||
|
|||
211: |
|||
beqz msize,212f |
|||
nop |
|||
move a0,k1 |
|||
|
|||
li v0,0xaffffe70 |
|||
lw v1,0(v0) |
|||
nop |
|||
sll a0,a0,16 |
|||
li t0,0xfff0ffff |
|||
and v1,v1,t0 |
|||
or v1,v1,a0 |
|||
sw v1,0(v0) |
|||
nop |
|||
|
|||
|
|||
PRINTSTR ("cs map : "); |
|||
move a0,k1 |
|||
bal hexserial |
|||
nop |
|||
|
|||
|
|||
PRINTSTR("\r\nconfig bank if bank 8: ") |
|||
li v0,0xaffffe10 |
|||
ld v1,0(v0) |
|||
nop |
|||
move a0,v1 |
|||
dsrl a0,a0,32 |
|||
or a0,a0,k0 |
|||
dsll a0,a0,32 |
|||
or v1,a0,v1 |
|||
sd v1,0(v0) |
|||
nop |
|||
move a0,v1 |
|||
dsrl a0,a0,32 |
|||
bal hexserial |
|||
nop |
|||
|
|||
PRINTSTR("\r\ncols rows: ") |
|||
|
|||
//row addr numbers |
|||
li v0,0xffffffff |
|||
and a0,s6,v0 |
|||
li v0,15 |
|||
subu a0,v0,a0 |
|||
|
|||
//col addr numbers |
|||
dsrl s6,s6,20 |
|||
dsrl s6,s6,12 |
|||
li v0,14 |
|||
|
|||
move a1,s6 |
|||
subu a1,v0,a1 |
|||
|
|||
sll a1,a1,24 |
|||
sll a0,a0,8 |
|||
|
|||
li v0,0xaffffe50 |
|||
lw v1,0(v0) |
|||
nop |
|||
li t0,0xf8fff8ff |
|||
and v1,v1,t0 |
|||
or v1,v1,a0 |
|||
or v1,v1,a1 |
|||
sw v1,0(v0) |
|||
nop |
|||
move a0,v1 |
|||
bal hexserial |
|||
nop |
|||
|
|||
PRINTSTR("\r\n") |
|||
b 213f |
|||
nop |
|||
212: |
|||
.nodimm: |
|||
li msize,0x100 |
|||
PRINTSTR ("\r\nNo DIMM in all slots,use default configure\r\n") |
|||
213: |
|||
|
|||
PRINTSTR ("\r\nDIMM size :") |
|||
move a0,msize |
|||
bal hexserial |
|||
nop |
|||
|
|||
PRINTSTR ("\r\n") |
|||
|
|||
sll msize,20 |
|||
@ -0,0 +1,72 @@ |
|||
#define EJTAG_TLB_INDEX EJTAG_INDEX |
|||
#define EJTAG_TLB_HIGH EJTAG_ENTRYHI |
|||
#define EJTAG_TLB_LO0 EJTAG_ENTRYLO0 |
|||
#define EJTAG_TLB_LO1 EJTAG_ENTRYLO1 |
|||
|
|||
li t0, 0x20000000 |
|||
.set mips64 |
|||
dmfc0 t1, COP_0_TLB_PG_MASK, 1 |
|||
or t1, t1, t0 |
|||
dmtc0 t1, COP_0_TLB_PG_MASK, 1 |
|||
|
|||
dmfc0 t0, COP_0_CONFIG, 3 |
|||
ori t0, t0, 0x80 |
|||
dmtc0 t0, COP_0_CONFIG, 3 |
|||
.set mips3 |
|||
|
|||
li t0, 0xfff000 |
|||
li t0, -1 |
|||
mtc0 t0, COP_0_TLB_PG_MASK # 16MB page |
|||
|
|||
li t0, 63 |
|||
1: |
|||
mtc0 t0, COP_0_TLB_INDEX |
|||
|
|||
#PRINTSTR("index:") |
|||
#move a0, t0 |
|||
# bal hexserial64 |
|||
#nop |
|||
# PRINTSTR("\r\n") |
|||
li a0,EJTAG_TLB_INDEX |
|||
sd t0, 0x0(a0) |
|||
|
|||
tlbr |
|||
nop |
|||
nop |
|||
nop |
|||
nop |
|||
|
|||
.set mips64 |
|||
dmfc0 t1, COP_0_TLB_HI |
|||
#PRINTSTR("tlb hi:") |
|||
#move a0, t3 |
|||
# bal hexserial64 |
|||
#nop |
|||
# PRINTSTR("\r\n") |
|||
li a0,EJTAG_TLB_HIGH |
|||
sd t1, 0x0(a0) |
|||
|
|||
|
|||
dmfc0 t1, COP_0_TLB_LO0 |
|||
#PRINTSTR("tlb lo0:") |
|||
#move a0, t4 |
|||
# bal hexserial64 |
|||
#nop |
|||
# PRINTSTR("\r\n") |
|||
li a0,EJTAG_TLB_LO0 |
|||
sd t1, 0x0(a0) |
|||
|
|||
|
|||
dmfc0 t1, COP_0_TLB_LO1 |
|||
#PRINTSTR("tlb lo1:") |
|||
#move a0, t5 |
|||
# bal hexserial64 |
|||
#nop |
|||
# PRINTSTR("\r\n") |
|||
li a0,EJTAG_TLB_LO1 |
|||
sd t1, 0x0(a0) |
|||
|
|||
.set mips3 |
|||
|
|||
bnez t0, 1b |
|||
addiu t0, -1 |
|||
@ -0,0 +1,72 @@ |
|||
/*whd : loongson3_fixup.S |
|||
used to fix up the potential addressing miss |
|||
caused by speculated execution |
|||
*/ |
|||
|
|||
|
|||
#if 1 |
|||
#set XBAR to route all the DMA request to Scache0 |
|||
#define SINGLE_SCACHE |
|||
#ifdef SINGLE_SCACHE |
|||
dli a0,0xf #using 37:36 |
|||
#else |
|||
//dli a0,0x2 #using 11:10 |
|||
dli a0,0xb #using 29:28 |
|||
#endif |
|||
dli t0,0x900000003ff00400 |
|||
sd a0,0x0(t0) |
|||
|
|||
#if 0//config L1 xbar cpu port |
|||
dli t2, 0x900000003ff02000 |
|||
dli t1, 0x900000003ff02400 |
|||
TTYDBG("Using Scache 3 \r\n") |
|||
1: |
|||
dli t0, 0x0000000000000000 |
|||
sd t0, 0x00(t2) |
|||
dli t0, 0x0000000000000000 |
|||
sd t0, 0x40(t2) |
|||
dli t0, 0x00000000000000f3 |
|||
sd t0, 0x80(t2) |
|||
#endif |
|||
|
|||
PRINTSTR("Scache index setup done\r\n") |
|||
#endif |
|||
|
|||
|
|||
#if 1//config L1 xbar cpu port |
|||
dli t2, 0x900000003ff02000 |
|||
dli t1, 0x900000003ff02400 |
|||
TTYDBG("Fix L1xbar illegal access \r\n") |
|||
1: |
|||
|
|||
|
|||
#ifndef MULTI_CHIP |
|||
####### address space to other nodes ############ |
|||
// dli t0, 0x0000200000000000 |
|||
// sd t0, 0x30(t2) |
|||
// dli t0, 0x0000200000000000 |
|||
// sd t0, 0x70(t2) |
|||
// dli t0, 0x00002000000000f7 |
|||
// sd t0, 0xb0(t2) |
|||
// |
|||
// dli t0, 0x0000100000000000 |
|||
// sd t0, 0x38(t2) |
|||
// dli t0, 0x0000300000000000 |
|||
// sd t0, 0x78(t2) |
|||
// dli t0, 0x00001000000000f7 |
|||
// sd t0, 0xb8(t2) |
|||
|
|||
dli t0, 0x0000000000000000 |
|||
sd t0, 0x38(t2) |
|||
dli t0, 0x0000000000000000 |
|||
sd t0, 0x78(t2) |
|||
dli t0, 0x00000000000000f0 |
|||
sd t0, 0xb8(t2) |
|||
daddiu t2, t2, 0x100 |
|||
bne t2, t1, 1b |
|||
nop |
|||
#endif |
|||
|
|||
#endif |
|||
|
|||
|
|||
@ -0,0 +1,434 @@ |
|||
#include "time.h" |
|||
#define nr_printf printf |
|||
#define nr_gets gets |
|||
#define nr_strtol strtoul |
|||
//-------------------------------------------PNP------------------------------------------
|
|||
// MB PnP configuration register
|
|||
|
|||
#define PNP_KEY_ADDR (0xbfd00000+0x3f0) |
|||
#define PNP_DATA_ADDR (0xbfd00000+0x3f1) |
|||
|
|||
|
|||
|
|||
static unsigned char slave_addr; |
|||
|
|||
void PNPSetConfig(char Index, char data); |
|||
char PNPGetConfig(char Index); |
|||
|
|||
#define SUPERIO_CFG_REG 0x85 |
|||
|
|||
void EnterMBPnP(void) |
|||
{ |
|||
pcitag_t tag; |
|||
char confval; |
|||
tag=_pci_make_tag(VTSB_BUS,VTSB_DEV, VTSB_ISA_FUNC); |
|||
confval=_pci_conf_readn(tag,SUPERIO_CFG_REG,1); |
|||
_pci_conf_writen(tag,SUPERIO_CFG_REG,confval|2,1); |
|||
} |
|||
|
|||
void ExitMBPnP(void) |
|||
{ |
|||
pcitag_t tag; |
|||
char confval,val; |
|||
tag=_pci_make_tag(VTSB_BUS,VTSB_DEV, VTSB_ISA_FUNC); |
|||
confval=_pci_conf_readn(tag,SUPERIO_CFG_REG,1); |
|||
_pci_conf_writen(tag,SUPERIO_CFG_REG,confval&~2,1); |
|||
} |
|||
|
|||
void PNPSetConfig(char Index, char data) |
|||
{ |
|||
EnterMBPnP(); // Enter IT8712 MB PnP mode
|
|||
outb(PNP_KEY_ADDR,Index); |
|||
outb(PNP_DATA_ADDR,data); |
|||
ExitMBPnP(); |
|||
} |
|||
|
|||
char PNPGetConfig(char Index) |
|||
{ |
|||
char rtn; |
|||
|
|||
EnterMBPnP(); // Enter IT8712 MB PnP mode
|
|||
outb(PNP_KEY_ADDR,Index); |
|||
rtn = inb(PNP_DATA_ADDR); |
|||
ExitMBPnP(); |
|||
return rtn; |
|||
} |
|||
|
|||
|
|||
|
|||
int dumpsis(int argc,char **argv) |
|||
{ |
|||
int i; |
|||
volatile unsigned char *p=0xbfd003c4; |
|||
unsigned char c; |
|||
for(i=0;i<0x15;i++) |
|||
{ |
|||
p[0]=i; |
|||
c=p[1]; |
|||
printf("sr%x=0x%02x\n",i,c); |
|||
} |
|||
p[0]=5; |
|||
p[1]=0x86; |
|||
printf("after set 0x86 to sr5\n"); |
|||
for(i=0;i<0x15;i++) |
|||
{ |
|||
p[0]=i; |
|||
c=p[1]; |
|||
printf("sr%x=0x%02x\n",i,c); |
|||
} |
|||
return 0; |
|||
} |
|||
|
|||
unsigned char i2cread(char slot,char offset); |
|||
|
|||
|
|||
union commondata{ |
|||
unsigned char data1; |
|||
unsigned short data2; |
|||
unsigned int data4; |
|||
unsigned int data8[2]; |
|||
unsigned char c[8]; |
|||
}; |
|||
extern unsigned int syscall_addrtype; |
|||
extern int (*syscall1)(int type,long long addr,union commondata *mydata); |
|||
extern int (*syscall2)(int type,long long addr,union commondata *mydata); |
|||
|
|||
|
|||
|
|||
|
|||
#include "target/via686b.h" |
|||
static int i2cslot=0; |
|||
|
|||
|
|||
static int DimmRead(int type,long long addr,union commondata *mydata) |
|||
{ |
|||
char i2caddr[]={(i2cslot<<1)+0xa0}; |
|||
switch(type) |
|||
{ |
|||
case 1: |
|||
tgt_i2cread(I2C_SINGLE,i2caddr,1,addr,&mydata->data1,1); |
|||
break; |
|||
|
|||
default: return -1;break; |
|||
} |
|||
return 0; |
|||
} |
|||
|
|||
static int DimmWrite(int type,long long addr,union commondata *mydata) |
|||
{ |
|||
return -1; |
|||
} |
|||
|
|||
|
|||
static int Ics950220Read(int type,long long addr,union commondata *mydata) |
|||
{ |
|||
char c; |
|||
char i2caddr[]={0xd2}; |
|||
switch(type) |
|||
{ |
|||
case 1: |
|||
tgt_i2cread(I2C_SMB_BLOCK,i2caddr,1,addr,&mydata->data1,1); |
|||
|
|||
break; |
|||
|
|||
default: return -1;break; |
|||
} |
|||
return 0; |
|||
} |
|||
|
|||
static int Ics950220Write(int type,long long addr,union commondata *mydata) |
|||
{ |
|||
char c; |
|||
char i2caddr[]={0xd2}; |
|||
switch(type) |
|||
{ |
|||
case 1: |
|||
tgt_i2cwrite(I2C_SMB_BLOCK,i2caddr,1,addr,&mydata->data1,1); |
|||
|
|||
break; |
|||
|
|||
default: return -1;break; |
|||
} |
|||
return 0; |
|||
return -1; |
|||
} |
|||
|
|||
static int rom_ddr_reg_read(int type,long long addr,union commondata *mydata) |
|||
{ |
|||
char *nvrambuf; |
|||
extern char ddr2_reg_data,_start; |
|||
nvrambuf = 0xbfc00000+((int)&ddr2_reg_data -(int)&_start)+addr; |
|||
// printf("ddr2_reg_data=%x\nbuf=%x,ddr=%x\n",&ddr2_reg_data,nvrambuf,addr);
|
|||
switch(type) |
|||
{ |
|||
case 1:memcpy(&mydata->data1,nvrambuf,1);break; |
|||
case 2:memcpy(&mydata->data2,nvrambuf,2);break; |
|||
case 4:memcpy(&mydata->data4,nvrambuf,4);break; |
|||
case 8:memcpy(&mydata->data8,nvrambuf,8);break; |
|||
} |
|||
return 0; |
|||
} |
|||
|
|||
static int rom_ddr_reg_write(int type,long long addr,union commondata *mydata) |
|||
{ |
|||
char *nvrambuf; |
|||
char *nvramsecbuf; |
|||
char *nvram; |
|||
int offs; |
|||
extern char ddr2_reg_data,_start; |
|||
struct fl_device *dev=fl_devident(0xbfc00000,0); |
|||
int nvram_size=dev->fl_secsize; |
|||
|
|||
nvram = 0xbfc00000+((int)&ddr2_reg_data -(int)&_start); |
|||
offs=(int)nvram &(nvram_size - 1); |
|||
nvram =(int)nvram & ~(nvram_size - 1); |
|||
|
|||
/* Deal with an entire sector even if we only use part of it */ |
|||
|
|||
/* If NVRAM is found to be uninitialized, reinit it. */ |
|||
|
|||
/* Find end of evironment strings */ |
|||
nvramsecbuf = (char *)malloc(nvram_size); |
|||
|
|||
if(nvramsecbuf == 0) { |
|||
printf("Warning! Unable to malloc nvrambuffer!\n"); |
|||
return(-1); |
|||
} |
|||
|
|||
memcpy(nvramsecbuf, nvram, nvram_size); |
|||
if(fl_erase_device(nvram, nvram_size, FALSE)) { |
|||
printf("Error! Nvram erase failed!\n"); |
|||
free(nvramsecbuf); |
|||
return(0); |
|||
} |
|||
|
|||
nvrambuf = nvramsecbuf + offs; |
|||
switch(type) |
|||
{ |
|||
case 1:memcpy(nvrambuf+addr,&mydata->data1,1);break; |
|||
case 2:memcpy(nvrambuf+addr,&mydata->data2,2);break; |
|||
case 4:memcpy(nvrambuf+addr,&mydata->data4,4);break; |
|||
case 8:memcpy(nvrambuf+addr,&mydata->data8,8);break; |
|||
} |
|||
|
|||
if(fl_program_device(nvram, nvramsecbuf, nvram_size, FALSE)) { |
|||
printf("Error! Nvram program failed!\n"); |
|||
free(nvramsecbuf); |
|||
return(0); |
|||
} |
|||
free(nvramsecbuf); |
|||
return 0; |
|||
} |
|||
|
|||
|
|||
#if defined(DEVBD2F_SM502)||defined(DEVBD2F_FIREWALL) |
|||
|
|||
|
|||
#ifndef BCD_TO_BIN |
|||
#define BCD_TO_BIN(val) ((val)=((val)&15) + ((val)>>4)*10) |
|||
#endif |
|||
|
|||
#ifndef BIN_TO_BCD |
|||
#define BIN_TO_BCD(val) ((val)=(((val)/10)<<4) + (val)%10) |
|||
#endif |
|||
|
|||
void tm_binary_to_bcd(struct tm *tm) |
|||
{ |
|||
BIN_TO_BCD(tm->tm_sec); |
|||
BIN_TO_BCD(tm->tm_min); |
|||
BIN_TO_BCD(tm->tm_hour); |
|||
tm->tm_hour = tm->tm_hour|0x80; |
|||
BIN_TO_BCD(tm->tm_mday); |
|||
BIN_TO_BCD(tm->tm_mon); |
|||
BIN_TO_BCD(tm->tm_year); |
|||
BIN_TO_BCD(tm->tm_wday); |
|||
|
|||
} |
|||
|
|||
/*
|
|||
*isl 12027 |
|||
* */ |
|||
char gpio_i2c_settime(struct tm *tm) |
|||
{ |
|||
struct |
|||
{ |
|||
char tm_sec; |
|||
char tm_min; |
|||
char tm_hour; |
|||
char tm_mday; |
|||
char tm_mon; |
|||
char tm_year; |
|||
char tm_wday; |
|||
char tm_year_hi; |
|||
} rtcvar; |
|||
char i2caddr[]={0xde,0}; |
|||
|
|||
char a ; |
|||
word_addr = 1; |
|||
tm->tm_mon = tm->tm_mon + 1; |
|||
tm_binary_to_bcd(tm); |
|||
|
|||
//when rtc stop,can't set it ,follow 5 lines to resolve it
|
|||
a = 2; |
|||
tgt_i2cwrite(I2C_SINGLE,i2caddr,2,0x3f,&a,1); |
|||
a = 6; |
|||
tgt_i2cwrite(I2C_SINGLE,i2caddr,2,0x3f,&a,1); |
|||
tgt_i2cwrite(I2C_SINGLE,i2caddr,2,0x30,&a,1); |
|||
|
|||
a = 2; |
|||
tgt_i2cwrite(I2C_SINGLE,i2caddr,2,0x3f,&a,1); |
|||
a = 6; |
|||
tgt_i2cwrite(I2C_SINGLE,i2caddr,2,0x3f,&a,1); |
|||
|
|||
//begin set
|
|||
|
|||
rtcvar.tm_sec=tm->tm_sec; |
|||
rtcvar.tm_min=tm->tm_min; |
|||
rtcvar.tm_hour=tm->tm_hour; |
|||
rtcvar.tm_mday=tm->tm_mday; |
|||
rtcvar.tm_mon=tm->tm_mon; |
|||
rtcvar.tm_wday=tm->tm_wday; |
|||
if(tm->tm_year>=0xa0) |
|||
{ |
|||
rtcvar.tm_year = tm->tm_year - 0xa0; |
|||
rtcvar.tm_year_hi=20; |
|||
|
|||
} |
|||
else |
|||
{ |
|||
rtcvar.tm_year = tm->tm_year; |
|||
rtcvar.tm_year_hi=19; |
|||
} |
|||
tgt_i2cwrite(I2C_BLOCK,i2caddr,2,0x30,&rtcvar,sizeof(rtcvar)); |
|||
|
|||
return 1; |
|||
|
|||
} |
|||
|
|||
/*
|
|||
* sm502: rx8025 |
|||
* fire:isl12027 |
|||
*/ |
|||
|
|||
|
|||
|
|||
|
|||
#endif |
|||
|
|||
//----------------------------------------
|
|||
|
|||
static int syscall_i2c_type,syscall_i2c_addrlen; |
|||
static char syscall_i2c_addr[2]; |
|||
|
|||
static int i2c_read_syscall(int type,long long addr,union commondata *mydata) |
|||
{ |
|||
char c; |
|||
switch(type) |
|||
{ |
|||
case 1: |
|||
tgt_i2cread(syscall_i2c_type,syscall_i2c_addr,syscall_i2c_addrlen,addr,&mydata->data1,1); |
|||
|
|||
break; |
|||
|
|||
default: return -1;break; |
|||
} |
|||
return 0; |
|||
} |
|||
|
|||
static int i2c_write_syscall(int type,long long addr,union commondata *mydata) |
|||
{ |
|||
char c; |
|||
switch(type) |
|||
{ |
|||
case 1: |
|||
tgt_i2cwrite(syscall_i2c_type,syscall_i2c_addr,syscall_i2c_addrlen,addr,&mydata->data1,1); |
|||
|
|||
break; |
|||
|
|||
default: return -1;break; |
|||
} |
|||
return 0; |
|||
return -1; |
|||
} |
|||
//----------------------------------------
|
|||
|
|||
static int i2cs(int argc,char **argv) |
|||
{ |
|||
pcitag_t tag; |
|||
volatile int i; |
|||
if(argc<2) |
|||
return -1; |
|||
|
|||
i2cslot=strtoul(argv[1],0,0); |
|||
|
|||
switch(i2cslot) |
|||
{ |
|||
case 0: |
|||
case 1: |
|||
syscall1=(void*)DimmRead; |
|||
syscall2=(void*)DimmWrite; |
|||
break; |
|||
case 2: |
|||
syscall1=(void*)Ics950220Read; |
|||
syscall2=(void*)Ics950220Write; |
|||
break; |
|||
case 3: |
|||
syscall1=(void *)rom_ddr_reg_read; |
|||
syscall2=(void *)rom_ddr_reg_write; |
|||
if(argc==3 && !strcmp(argv[2][2],"revert")) |
|||
{ |
|||
extern char ddr2_reg_data,_start; |
|||
extern char ddr2_reg_data1; |
|||
printf("revert to default ddr setting\n"); |
|||
// tgt_flashprogram(0xbfc00000+((int)&ddr2_reg_data -(int)&_start),30*8,&ddr2_reg_data1,TRUE);
|
|||
} |
|||
break; |
|||
case -1: |
|||
if(argc<4)return -1; |
|||
syscall_i2c_type=strtoul(argv[2],0,0); |
|||
syscall_i2c_addrlen=argc-3; |
|||
for(i=3;i<argc;i++)syscall_i2c_addr[i-3]=strtoul(argv[i],0,0); |
|||
syscall1=(void*)i2c_read_syscall; |
|||
syscall2=(void*)i2c_write_syscall; |
|||
break; |
|||
default: |
|||
return -1; |
|||
} |
|||
|
|||
syscall_addrtype=0; |
|||
|
|||
return 0; |
|||
} |
|||
|
|||
|
|||
|
|||
static const Cmd Cmds[] = |
|||
{ |
|||
{"MyCmds"}, |
|||
{"dumpsis", "", 0, "dump sis registers", dumpsis, 0, 99, CMD_REPEAT}, |
|||
{"i2cs","slotno #slot 0-1 for dimm,slot 2 for ics95220,3 for ddrcfg,3 revert for revert to default ddr setting", 0, "select i2c ops for d1,m1", i2cs, 0, 99, CMD_REPEAT}, |
|||
{0, 0} |
|||
}; |
|||
|
|||
#ifdef DEVBD2F_SM502 |
|||
int power_button_poll(void *unused) |
|||
{ |
|||
int cause; |
|||
volatile int *p=0xbfe0011c; |
|||
asm("mfc0 %0,$13":"=r"(cause)); |
|||
if(cause&(1<<10))tgt_poweroff(); |
|||
return 0; |
|||
} |
|||
#endif |
|||
|
|||
static void init_cmd __P((void)) __attribute__ ((constructor)); |
|||
|
|||
static void |
|||
init_cmd() |
|||
{ |
|||
#ifdef DEVBD2F_SM502 |
|||
tgt_poll_register(1, power_button_poll, 0); |
|||
#endif |
|||
cmdlist_expand(Cmds, 1); |
|||
} |
|||
|
|||
@ -0,0 +1,768 @@ |
|||
|
|||
//extern onintr(int a,int *b);
|
|||
//#include "mips/cpu.h"
|
|||
#include "mips/prid.h" |
|||
|
|||
#include "mips.h" |
|||
#include "pmon.h" |
|||
#ifdef R3081 |
|||
#include "r3081.h" |
|||
#endif |
|||
#ifdef R3041 |
|||
#include "r3041.h" |
|||
#endif |
|||
|
|||
#include "ri.h" |
|||
|
|||
static unsigned long |
|||
mips_get_word_l(struct pt_regs *xcp, void *va, int *perr) |
|||
{ |
|||
*perr = 0; |
|||
return(*(unsigned long *)va); |
|||
} |
|||
|
|||
static int |
|||
mips_put_word_l(struct pt_regs *xcp, void *va, unsigned long val) |
|||
{ |
|||
*(unsigned long *)va = val; |
|||
return 0; |
|||
} |
|||
|
|||
static int emu_lwl(struct pt_regs * regs,mips_instruction ir,vaddr_t_l emulpc) |
|||
{ int err = 0; |
|||
/*the "ir" is the instruction causing the exception*/ |
|||
/*get the real address,perhaps the address is not word aligned*/ |
|||
void *va = REG_TO_VA_l (regs->regs[MIPSInst_RS(ir)])+ MIPSInst_SIMM(ir); |
|||
|
|||
unsigned long addr = 0; |
|||
unsigned long emul_pc = (unsigned long)emulpc; |
|||
|
|||
unsigned long little_three_bits; |
|||
unsigned long value,value_tmp; |
|||
|
|||
// printf("emu_lwl\r\n");
|
|||
|
|||
/*compute the correct position in the RT*/ |
|||
/*note !!!!: we have supposed the CPU is little_Endianness and status regiester's RE bit =0 */ |
|||
/*little Endianness*/ |
|||
little_three_bits = (unsigned long)va&(0x7); |
|||
value_tmp = regs->regs[MIPSInst_RT(ir)]; |
|||
switch(little_three_bits) { |
|||
case 0: |
|||
case 4: |
|||
/*must check lwl valid*/ |
|||
addr = (unsigned long) va; |
|||
check_axs(emul_pc,addr,4); |
|||
value = mips_get_word_l(regs,va,&err); |
|||
if(err){ |
|||
return SIGBUS; |
|||
} |
|||
value<<=24; |
|||
value_tmp &= 0xffffff; |
|||
regs->regs[MIPSInst_RT(ir)] =value_tmp|value; |
|||
break; |
|||
|
|||
case 1: |
|||
case 5: |
|||
addr = (unsigned long)va -1; |
|||
check_axs(emul_pc,addr,4); |
|||
value = mips_get_word_l(regs,(void *)((unsigned long) va-1),&err); |
|||
if(err){ |
|||
return SIGBUS; |
|||
} |
|||
value<<=16; |
|||
value_tmp&=0xffff; |
|||
regs->regs[MIPSInst_RT(ir)] =value_tmp|value; |
|||
break; |
|||
|
|||
case 2: |
|||
case 6: |
|||
addr = (unsigned long)va - 2; |
|||
check_axs(emul_pc,addr,4); |
|||
value = mips_get_word_l(regs,(void *)((unsigned long)va-2),&err); |
|||
if(err){ |
|||
return SIGBUS; |
|||
|
|||
} |
|||
value<<=8; |
|||
value_tmp &= 0xff; |
|||
regs->regs[MIPSInst_RT(ir)] =value_tmp|value; |
|||
break; |
|||
|
|||
case 3: |
|||
case 7: |
|||
addr = (unsigned long)va - 3; |
|||
check_axs(emul_pc,addr,4); |
|||
value = mips_get_word_l(regs,(void *)((unsigned long)va-3),&err); |
|||
if(err){ |
|||
return SIGBUS; |
|||
}; |
|||
regs->regs[MIPSInst_RT(ir)] = value; |
|||
break; |
|||
} /*swith ended*/ |
|||
return 0; |
|||
|
|||
} |
|||
|
|||
static int emu_lwr(struct pt_regs *regs,mips_instruction ir,vaddr_t_l emulpc) |
|||
{ int err = 0; |
|||
/*the "ir" is the instruction causing the exception*/ |
|||
/*get the real address,perhaps the address is not word aligned*/ |
|||
void *va = REG_TO_VA_l (regs->regs[MIPSInst_RS(ir)]) |
|||
+ MIPSInst_SIMM(ir); |
|||
unsigned long addr; |
|||
unsigned long emul_pc = (unsigned long)emulpc; |
|||
unsigned long little_three_bits; |
|||
unsigned long value,value_tmp; |
|||
|
|||
// printf("emu_lwr\r\n");
|
|||
|
|||
/*compute the correct position in the RT*/ |
|||
/*note !!!!: we have supposed the CPU is little_Endianness and status regiester's RE bit =0 */ |
|||
little_three_bits = (unsigned long)va&(0x7); |
|||
value_tmp = regs->regs[MIPSInst_RT(ir)]; |
|||
switch(little_three_bits) { |
|||
case 0: |
|||
case 4: |
|||
/*must check lwl valid*/ |
|||
addr = (unsigned long)va ; |
|||
check_axs(emul_pc,addr,4); |
|||
value = mips_get_word_l(regs,va,&err); |
|||
if(err){ |
|||
return SIGBUS; |
|||
} |
|||
regs->regs[MIPSInst_RT(ir)] =value; |
|||
break; |
|||
|
|||
case 1: |
|||
case 5: |
|||
addr = (unsigned long)va -1; |
|||
check_axs(emul_pc,addr,4); |
|||
value = mips_get_word_l(regs,(void *)((unsigned long)va-1),&err); |
|||
if(err){ |
|||
return SIGBUS; |
|||
} |
|||
value>>=8; |
|||
value_tmp&=0xff000000; |
|||
regs->regs[MIPSInst_RT(ir)] =value_tmp|value; |
|||
break; |
|||
|
|||
case 2: |
|||
case 6: |
|||
addr = (unsigned long)va-2; |
|||
check_axs(emul_pc,addr,4); |
|||
value = mips_get_word_l(regs,(void *)((unsigned long)va-2),&err); |
|||
if(err){ |
|||
return SIGBUS; |
|||
|
|||
} |
|||
value>>=16; |
|||
value_tmp &= 0xffff0000; |
|||
regs->regs[MIPSInst_RT(ir)] =value_tmp|value; |
|||
break; |
|||
|
|||
case 3: |
|||
case 7: |
|||
addr = (unsigned long)va -3; |
|||
check_axs(emul_pc,addr,4); |
|||
value = mips_get_word_l(regs,(void *)((unsigned long)va-3),&err); |
|||
if(err){ |
|||
return SIGBUS; |
|||
}; |
|||
value>>=24; |
|||
value_tmp &= 0xffffff00; |
|||
regs->regs[MIPSInst_RT(ir)] = value_tmp|value; |
|||
break; |
|||
} /*swith ended*/ |
|||
return 0; |
|||
} |
|||
|
|||
static int emu_swl(struct pt_regs *regs,mips_instruction ir, vaddr_t_l emulpc) |
|||
{ |
|||
int err = 0; |
|||
/*the "ir" is the instruction causing the exception*/ |
|||
/*get the real address,perhaps the address is not word aligned*/ |
|||
void *va = REG_TO_VA_l (regs->regs[MIPSInst_RS(ir)]) |
|||
+ MIPSInst_SIMM(ir); |
|||
unsigned long addr; |
|||
unsigned long emul_pc = (unsigned long)emulpc; |
|||
unsigned long little_three_bits; |
|||
unsigned long value,value_tmp; |
|||
|
|||
// printf("emu_swl\r\n");
|
|||
|
|||
/*compute the correct position in the RT*/ |
|||
/*note !!!!: we have supposed the CPU is little_Endianness and status re
|
|||
* giester's RE bit =0 */ |
|||
little_three_bits = (unsigned long)va&(0x7); |
|||
value_tmp = regs->regs[MIPSInst_RT(ir)]; |
|||
switch(little_three_bits) { |
|||
case 0: |
|||
case 4: |
|||
addr = (unsigned long)va; |
|||
check_axs(emul_pc,addr,4); |
|||
value_tmp >>= 24; |
|||
value = mips_get_word_l(regs,va,&err); |
|||
if(err){ |
|||
return SIGBUS; |
|||
} |
|||
value &=0xffffff00; |
|||
value |= value_tmp; |
|||
if(mips_put_word_l(regs,va,value)){ |
|||
return SIGBUS; |
|||
} |
|||
break; |
|||
case 1: |
|||
case 5: |
|||
addr = (unsigned long)va -1; |
|||
check_axs(emul_pc,addr,4); |
|||
value_tmp >>= 16; |
|||
value = mips_get_word_l(regs,(void *)((unsigned long)va-1),&err); |
|||
if(err){ |
|||
return SIGBUS; |
|||
} |
|||
value &=0xffff0000; |
|||
value |= value_tmp; |
|||
if(mips_put_word_l(regs,(void *)((unsigned long)va-1),value)){ |
|||
return SIGBUS; |
|||
} |
|||
break; |
|||
case 2: |
|||
case 6: |
|||
addr = (unsigned long)va - 2; |
|||
check_axs(emul_pc,addr,4); |
|||
value_tmp >>= 8; |
|||
value = mips_get_word_l(regs,(void *)((unsigned long)va-2),&err); |
|||
if(err){ |
|||
return SIGBUS; |
|||
} |
|||
value &=0xff000000; |
|||
value |= value_tmp; |
|||
if(mips_put_word_l(regs,(void *)((unsigned long)va-2),value)){ |
|||
return SIGBUS; |
|||
} |
|||
break; |
|||
case 3: |
|||
case 7: |
|||
addr = (unsigned long)va - 3; |
|||
check_axs(emul_pc,addr,4); |
|||
value = value_tmp; |
|||
|
|||
if(mips_put_word_l(regs,(void *)((unsigned long)va-3),value)){ |
|||
return SIGBUS; |
|||
} |
|||
break; |
|||
} |
|||
return 0; |
|||
|
|||
} |
|||
|
|||
static int emu_swr(struct pt_regs *regs,mips_instruction ir, vaddr_t_l emulpc) |
|||
{ |
|||
int err = 0; |
|||
/*the "ir" is the instruction causing the exception*/ |
|||
/*get the real address,perhaps the address is not word aligned*/ |
|||
void *va = REG_TO_VA_l (regs->regs[MIPSInst_RS(ir)]) |
|||
+ MIPSInst_SIMM(ir); |
|||
unsigned long addr; |
|||
unsigned long emul_pc = (unsigned long)emulpc; |
|||
|
|||
|
|||
unsigned long little_three_bits; |
|||
unsigned long value,value_tmp; |
|||
|
|||
// printf("emu_swr\r\n");
|
|||
|
|||
/*compute the correct position in the RT*/ |
|||
/*note !!!!: we have supposed the CPU is little_Endianness and status re
|
|||
* giester's RE bit =0 */ |
|||
little_three_bits = (unsigned long)va&(0x7); |
|||
value_tmp = regs->regs[MIPSInst_RT(ir)]; |
|||
switch(little_three_bits) { |
|||
case 0: |
|||
case 4: |
|||
addr = (unsigned long) va; |
|||
check_axs(emul_pc,addr,4); |
|||
value = value_tmp; |
|||
if(mips_put_word_l(regs,va,value)){ |
|||
return SIGBUS; |
|||
} |
|||
break; |
|||
case 1: |
|||
case 5: |
|||
addr = (unsigned long)va -1; |
|||
check_axs(emul_pc,addr,4); |
|||
value_tmp <<= 8; |
|||
value = mips_get_word_l(regs,(void *)((unsigned long)va-1),&err); |
|||
if(err){ |
|||
return SIGBUS; |
|||
} |
|||
value &=0xff; |
|||
value |= value_tmp; |
|||
if(mips_put_word_l(regs,(void *)((unsigned long)va-1),value)){ |
|||
return SIGBUS; |
|||
} |
|||
break; |
|||
case 2: |
|||
case 6: |
|||
addr = (unsigned long)va - 2; |
|||
check_axs(emul_pc,addr,4); |
|||
value_tmp <<= 16; |
|||
value = mips_get_word_l(regs,(void *)((unsigned long)va-2),&err); |
|||
if(err){ |
|||
return SIGBUS; |
|||
} |
|||
value &=0xffff; |
|||
value |= value_tmp; |
|||
if(mips_put_word_l(regs,(void *)((unsigned long)va-2),value)){ |
|||
return SIGBUS; |
|||
} |
|||
break; |
|||
case 3: |
|||
case 7: |
|||
addr = (unsigned long)va -3; |
|||
check_axs(emul_pc,addr,4); |
|||
value_tmp <<= 24; |
|||
value = mips_get_word_l(regs,(void *)((unsigned long)va-3),&err); |
|||
if(err){ |
|||
return SIGBUS; |
|||
} |
|||
|
|||
value &= 0xffffff; |
|||
value |= value_tmp; |
|||
if(mips_put_word_l(regs,(void *)((unsigned long)va-3),value)){ |
|||
return SIGBUS; |
|||
} |
|||
break; |
|||
} |
|||
return 0; |
|||
|
|||
} |
|||
|
|||
|
|||
|
|||
static int emu_div(struct pt_regs *regs,mips_instruction ir) |
|||
{ |
|||
int x,y; |
|||
int flag = 0; |
|||
int quotient = 0,remainder = 0; |
|||
unsigned int absx,absy,absquotient = 0,absremainder = 0,bm = 1; |
|||
/*the "ir" is the instruction causing the exception*/ |
|||
x = regs->regs[MIPSInst_RS(ir)]; |
|||
y = regs->regs[MIPSInst_RT(ir)]; |
|||
|
|||
#ifdef __test_ri__ |
|||
//printf("now in function:emu_div().\r\n");
|
|||
#endif |
|||
|
|||
if( y == 0 ) {/*overflow*/ |
|||
return SIGABRT; |
|||
} |
|||
/*x and y ·ûºÅÊÇ·ñ²»Í¬*/ |
|||
flag = (x&0x80000000)^(y&0x80000000); |
|||
|
|||
/*get the abs(x)*/ |
|||
if(x<0){ |
|||
absx = (unsigned int)-x; |
|||
}else { |
|||
absx = (unsigned int)x; |
|||
} |
|||
|
|||
/*get the abs(y)*/ |
|||
if(y<0){ |
|||
absy = (unsigned int) -y; |
|||
}else { |
|||
absy = (unsigned int)y; |
|||
} |
|||
|
|||
/*caculate the absx/absy*/ |
|||
if(absx<absy) {/*don't need to calculate*/ |
|||
absquotient = 0; |
|||
absremainder = absx; |
|||
goto end; |
|||
} |
|||
|
|||
while(!(absy&0x80000000)) |
|||
{ absy<<=1; |
|||
if(absx<absy){ |
|||
absy>>= 1; |
|||
break; |
|||
} |
|||
bm<<=1; |
|||
} |
|||
|
|||
for(;bm;bm>>=1){ |
|||
if(absx>=absy){ |
|||
absx -= absy; |
|||
absquotient |= bm; |
|||
if(absx == 0) |
|||
break; |
|||
} |
|||
absy >>= 1; |
|||
} |
|||
absremainder = absx; |
|||
|
|||
end: |
|||
if( flag ){/*·ûºÅÏàÒì*/ |
|||
quotient = -absquotient; |
|||
remainder = x-quotient*y; |
|||
}else { |
|||
quotient = absquotient; |
|||
remainder = x - quotient*y; |
|||
} |
|||
|
|||
regs->lo =(unsigned long)quotient; |
|||
regs->hi = (unsigned long)remainder; |
|||
|
|||
#ifdef __test_ri__ |
|||
// printf("x is: %d\r\n",x);
|
|||
// printf("y is: %d\r\n",y);
|
|||
// printf("result is: %d (:\r\n",quotient);
|
|||
#endif |
|||
|
|||
return 0; |
|||
} |
|||
|
|||
static int emu_divu(struct pt_regs *regs,mips_instruction ir) |
|||
{ |
|||
unsigned int x,y,bm=1; |
|||
unsigned int quotient = 0,remainder = 0; |
|||
|
|||
/*the "ir" is the instruction causing the exception*/ |
|||
x = regs->regs[MIPSInst_RS(ir)]; |
|||
y = regs->regs[MIPSInst_RT(ir)]; |
|||
|
|||
if( y == 0 ) {/*overflow*/ |
|||
return SIGABRT; |
|||
} |
|||
|
|||
if(x<y) {/*don't need to calculate*/ |
|||
quotient = 0; |
|||
remainder = x; |
|||
goto end; |
|||
} |
|||
|
|||
while(!(y&0x80000000)) |
|||
{ y<<=1; |
|||
if(x<y){ |
|||
y>>= 1; |
|||
break; |
|||
} |
|||
bm<<=1; |
|||
} |
|||
|
|||
for(;bm;bm>>=1){ |
|||
if(x>=y){ |
|||
x -= y; |
|||
quotient |= bm; |
|||
if(x == 0) |
|||
break; |
|||
} |
|||
y >>= 1; |
|||
|
|||
} |
|||
remainder = x; |
|||
end: |
|||
regs->lo = quotient; |
|||
regs->hi = remainder; |
|||
return 0; |
|||
|
|||
} |
|||
|
|||
/*
|
|||
* Compute the return address and do emulate branch simulation, if required. |
|||
*/ |
|||
#define EFAULT 1 |
|||
int __compute_return_epc(struct pt_regs *regs) |
|||
{ |
|||
unsigned int *addr, bit, fcr31; |
|||
long epc; |
|||
mips_instruction insn; |
|||
|
|||
epc = regs->cp0_epc; |
|||
if (epc & 3) { |
|||
printf("%s: unaligned epc - sending SIGBUS.\n"); |
|||
// force_sig(SIGBUS, current);
|
|||
return -EFAULT; |
|||
} |
|||
|
|||
/*
|
|||
* Read the instruction |
|||
*/ |
|||
addr = (unsigned int *) (unsigned long) epc; |
|||
#if 0 |
|||
if (__get_user(insn, addr)) { |
|||
printf("%s: bad epc value - sending SIGSEGV.\n"); |
|||
// force_sig(SIGSEGV, current);
|
|||
return -EFAULT; |
|||
} |
|||
#endif |
|||
//bjzheng add __get_user is prevent page_fault exception,if this occurs,load from disk,but now my whole code is in ram.
|
|||
insn=*addr; |
|||
// printf("instruction is %x",insn);
|
|||
regs->regs[0] = 0; |
|||
switch (MIPSInst_OPCODE(insn)) { |
|||
/*
|
|||
* jr and jalr are in r_format format. |
|||
*/ |
|||
case spec_op: |
|||
switch (MIPSInst_FUNC(insn)) { |
|||
case jalr_op: |
|||
regs->regs[MIPSInst_RD(insn)] = epc + 8; |
|||
/* Fall through */ |
|||
case jr_op: |
|||
regs->cp0_epc = regs->regs[MIPSInst_RS(insn)]; |
|||
break; |
|||
} |
|||
break; |
|||
|
|||
/*
|
|||
* This group contains: |
|||
* bltz_op, bgez_op, bltzl_op, bgezl_op, |
|||
* bltzal_op, bgezal_op, bltzall_op, bgezall_op. |
|||
*/ |
|||
case bcond_op: |
|||
switch (MIPSInst_RT(insn)) { |
|||
case bltz_op: |
|||
case bltzl_op: |
|||
if ((long)regs->regs[MIPSInst_RS(insn)] < 0) |
|||
epc = epc + 4 + (MIPSInst_SIMM(insn) << 2); |
|||
else |
|||
epc += 8; |
|||
regs->cp0_epc = epc; |
|||
break; |
|||
|
|||
case bgez_op: |
|||
case bgezl_op: |
|||
if ((long)regs->regs[MIPSInst_RS(insn)] >= 0) |
|||
epc = epc + 4 + (MIPSInst_SIMM(insn) << 2); |
|||
else |
|||
epc += 8; |
|||
regs->cp0_epc = epc; |
|||
break; |
|||
|
|||
case bltzal_op: |
|||
case bltzall_op: |
|||
regs->regs[31] = epc + 8; |
|||
if ((long)regs->regs[MIPSInst_RS(insn)] < 0) |
|||
epc = epc + 4 + (MIPSInst_SIMM(insn) << 2); |
|||
else |
|||
epc += 8; |
|||
regs->cp0_epc = epc; |
|||
break; |
|||
|
|||
case bgezal_op: |
|||
case bgezall_op: |
|||
regs->regs[31] = epc + 8; |
|||
if ((long)regs->regs[MIPSInst_RS(insn)] >= 0) |
|||
epc = epc + 4 + (MIPSInst_SIMM(insn) << 2); |
|||
else |
|||
epc += 8; |
|||
regs->cp0_epc = epc; |
|||
break; |
|||
} |
|||
break; |
|||
|
|||
/*
|
|||
* These are unconditional and in j_format. |
|||
*/ |
|||
case jal_op: |
|||
regs->regs[31] = regs->cp0_epc + 8; |
|||
case j_op: |
|||
epc += 4; |
|||
epc >>= 28; |
|||
epc <<= 28; |
|||
epc |= (MIPSInst_JTARGET(insn) << 2); |
|||
regs->cp0_epc = epc; |
|||
break; |
|||
|
|||
/*
|
|||
* These are conditional and in i_format. |
|||
*/ |
|||
case beq_op: |
|||
case beql_op: |
|||
if (regs->regs[MIPSInst_RS(insn)] == |
|||
regs->regs[MIPSInst_RT(insn)]) |
|||
epc = epc + 4 + (MIPSInst_SIMM(insn) << 2); |
|||
else |
|||
epc += 8; |
|||
regs->cp0_epc = epc; |
|||
break; |
|||
|
|||
case bne_op: |
|||
case bnel_op: |
|||
if (regs->regs[MIPSInst_RS(insn)] != |
|||
regs->regs[MIPSInst_RT(insn)]) |
|||
epc = epc + 4 + (MIPSInst_SIMM(insn) << 2); |
|||
else |
|||
epc += 8; |
|||
regs->cp0_epc = epc; |
|||
break; |
|||
|
|||
case blez_op: /* not really i_format */ |
|||
case blezl_op: |
|||
/* rt field assumed to be zero */ |
|||
if ((long)regs->regs[MIPSInst_RS(insn)] <= 0) |
|||
epc = epc + 4 + (MIPSInst_SIMM(insn) << 2); |
|||
else |
|||
epc += 8; |
|||
regs->cp0_epc = epc; |
|||
break; |
|||
|
|||
case bgtz_op: |
|||
case bgtzl_op: |
|||
/* rt field assumed to be zero */ |
|||
if ((long)regs->regs[MIPSInst_RS(insn)] > 0) |
|||
epc = epc + 4 + (MIPSInst_SIMM(insn) << 2); |
|||
else |
|||
epc += 8; |
|||
regs->cp0_epc = epc; |
|||
break; |
|||
|
|||
/*
|
|||
* And now the FPA/cp1 branch instructions. |
|||
*/ |
|||
case cop1_op: |
|||
#ifdef CONFIG_MIPS_FPU_EMULATOR |
|||
if(!(mips_cpu.options & MIPS_CPU_FPU)) |
|||
fcr31 = current->tss.fpu.soft.sr; |
|||
else |
|||
#endif |
|||
asm ("cfc1\t%0,$31":"=r" (fcr31)); |
|||
bit = (MIPSInst_RT(insn) >> 2); |
|||
bit += (bit != 0); |
|||
bit += 23; |
|||
switch (MIPSInst_RT(insn)) { |
|||
case 0: /* bc1f */ |
|||
case 2: /* bc1fl */ |
|||
if (~fcr31 & (1 << bit)) |
|||
epc = epc + 4 + (MIPSInst_SIMM(insn) << 2); |
|||
else |
|||
epc += 8; |
|||
regs->cp0_epc = epc; |
|||
break; |
|||
|
|||
case 1: /* bc1t */ |
|||
case 3: /* bc1tl */ |
|||
if (fcr31 & (1 << bit)) |
|||
epc = epc + 4 + (MIPSInst_SIMM(insn) << 2); |
|||
else |
|||
epc += 8; |
|||
regs->cp0_epc = epc; |
|||
break; |
|||
} |
|||
break; |
|||
} |
|||
|
|||
return 0; |
|||
} |
|||
|
|||
int do_ri (struct pt_regs *xcp) |
|||
{ |
|||
mips_instruction ir; |
|||
vaddr_t_l emulpc; |
|||
vaddr_t_l contpc; |
|||
int err = 0; |
|||
int sig; |
|||
|
|||
|
|||
ir = mips_get_word_l(xcp, REG_TO_VA_l xcp->cp0_epc, &err); |
|||
if (err) { |
|||
return SIGBUS; |
|||
} |
|||
|
|||
/* XXX NEC Vr54xx bug workaround */ |
|||
/* if ((xcp->cp0_cause & CAUSEF_BD) && !isBranchInstr (&ir))
|
|||
xcp->cp0_cause &= ~CAUSEF_BD;*/ |
|||
|
|||
if (xcp->cp0_cause & CAUSEF_BD) { |
|||
|
|||
/* The instruction to be emulated is in a branch delay slot
|
|||
* which means that we have to emulate the branch instruction |
|||
* BEFORE we do the emulating instruction. |
|||
* This branch could be a COP1 branch |
|||
*/ |
|||
|
|||
emulpc = REG_TO_VA_l(xcp->cp0_epc + 4); /* Snapshot emulation target */ |
|||
|
|||
#ifndef __bjzheng__ |
|||
if( __compute_return_epc(xcp)) {/*compute the return address*/ |
|||
#ifdef DBG |
|||
_mon_printf ("failed to emulate branch at %p\n", |
|||
REG_TO_VA_l (xcp->cp0_epc)); |
|||
#endif |
|||
return -1;; |
|||
} |
|||
#endif |
|||
|
|||
ir = mips_get_word_l(xcp, emulpc, &err); |
|||
if (err) { |
|||
return SIGBUS; |
|||
} |
|||
contpc = REG_TO_VA_l xcp->cp0_epc; |
|||
|
|||
} else { /* not in the Branch delay slot*/ |
|||
emulpc = REG_TO_VA_l xcp->cp0_epc; |
|||
contpc = REG_TO_VA_l xcp->cp0_epc + 4; |
|||
} |
|||
|
|||
switch(MIPSInst_OPCODE(ir)) { |
|||
case lwl_op: /*lwl instruction*/ |
|||
sig = emu_lwl(xcp,ir,emulpc); |
|||
if( sig!=0) { /*emul has failed*/ |
|||
return sig; |
|||
} |
|||
break; |
|||
|
|||
case lwr_op:/*lwr instruction*/ |
|||
sig = emu_lwr(xcp,ir,emulpc); |
|||
if ( sig != 0){ |
|||
/*emulate has failed!\n");*/ |
|||
return sig; |
|||
} |
|||
break; |
|||
|
|||
case swl_op: |
|||
sig = emu_swl(xcp,ir,emulpc); |
|||
if( sig!=0 ) { /*emul has failed!*/ |
|||
printf("emu_swl error\r\n"); |
|||
return sig; |
|||
} |
|||
break; |
|||
|
|||
case swr_op: |
|||
sig = emu_swr(xcp,ir,emulpc); |
|||
if( sig!=0 ) { /*emul has failed!*/ |
|||
printf("emu_swr error\r\n"); |
|||
return sig; |
|||
} |
|||
break; |
|||
case spec_op: |
|||
switch (MIPSInst_FUNC(ir)){ |
|||
case div_op:/*div_op*/ |
|||
sig = emu_div(xcp,ir); |
|||
if(sig) { |
|||
return sig; |
|||
} |
|||
break; |
|||
case divu_op:/* divu_op:*/ |
|||
sig = emu_divu(xcp,ir); |
|||
if(sig) { |
|||
return sig; |
|||
} |
|||
break; |
|||
default:; |
|||
|
|||
} |
|||
|
|||
default:; |
|||
} |
|||
|
|||
|
|||
/*we do it*/ |
|||
xcp->cp0_epc = VA_TO_REG_l(contpc); |
|||
xcp->cp0_cause &= ~CAUSEF_BD; |
|||
return sig; |
|||
|
|||
} |
|||
|
|||
File diff suppressed because it is too large
File diff suppressed because it is too large
File diff suppressed because it is too large
File diff suppressed because it is too large
File diff suppressed because it is too large
File diff suppressed because it is too large
File diff suppressed because it is too large
File diff suppressed because it is too large
@ -0,0 +1 @@ |
|||
#define NAHCI_CDROM 0 |
|||
@ -0,0 +1 @@ |
|||
#define NAHCI_SD 0 |
|||
@ -0,0 +1 @@ |
|||
#define NATP 0 |
|||
@ -0,0 +1 @@ |
|||
#define NBPFILTER 0 |
|||
@ -0,0 +1 @@ |
|||
#define NBRIDGE 0 |
|||
@ -0,0 +1 @@ |
|||
#define NCD 0 |
|||
@ -0,0 +1,2 @@ |
|||
#define NCMD_ENV 1 |
|||
#define NCMD_SET 1 |
|||
@ -0,0 +1 @@ |
|||
#define NCMD_HIST 1 |
|||
@ -0,0 +1 @@ |
|||
#define NCMD_LWDHCP 0 |
|||
@ -0,0 +1 @@ |
|||
#define NCMD_MORE 1 |
|||
@ -0,0 +1,4 @@ |
|||
#define NCMD_SHELL 1 |
|||
#define NCMD_VERS 0 |
|||
#define NCMD_HELP 0 |
|||
#define NCMD_EVAL 0 |
|||
@ -0,0 +1,107 @@ |
|||
/* $OpenBSD: crtbegin.c,v 1.2 1999/01/28 05:01:15 rahnds Exp $ */ |
|||
/* $NetBSD: crtbegin.c,v 1.1 1996/09/12 16:59:03 cgd Exp $ */ |
|||
|
|||
/*
|
|||
* Copyright (c) 1993 Paul Kranenburg |
|||
* All rights reserved. |
|||
* |
|||
* Redistribution and use in source and binary forms, with or without |
|||
* modification, are permitted provided that the following conditions |
|||
* are met: |
|||
* 1. Redistributions of source code must retain the above copyright |
|||
* notice, this list of conditions and the following disclaimer. |
|||
* 2. Redistributions in binary form must reproduce the above copyright |
|||
* notice, this list of conditions and the following disclaimer in the |
|||
* documentation and/or other materials provided with the distribution. |
|||
* 3. All advertising materials mentioning features or use of this software |
|||
* must display the following acknowledgement: |
|||
* This product includes software developed by Paul Kranenburg. |
|||
* 4. The name of the author may not be used to endorse or promote products |
|||
* derived from this software without specific prior written permission |
|||
* |
|||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
|||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
|||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
|||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
|||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
|||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
|||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
|||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
|||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
|||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
|||
*/ |
|||
|
|||
/*
|
|||
* Run-time module for GNU C++ compiled shared libraries. |
|||
* |
|||
* The linker constructs the following arrays of pointers to global |
|||
* constructors and destructors. The first element contains the |
|||
* number of pointers in each. |
|||
* The tables are also null-terminated. |
|||
|
|||
*/ |
|||
#include <stdlib.h> |
|||
|
|||
static void __dtors __P((void)); |
|||
static void __ctors __P((void)); |
|||
|
|||
typedef void (*func_ptr) (void); |
|||
|
|||
void __init __P((void)); |
|||
void __fini __P((void)); |
|||
|
|||
extern func_ptr __CTOR_LIST__[]; |
|||
extern func_ptr __DTOR_LIST__[]; |
|||
|
|||
static void __dtors __P((void)); |
|||
static void __ctors __P((void)); |
|||
|
|||
static void |
|||
__dtors() |
|||
{ |
|||
unsigned long i = (unsigned long) __DTOR_LIST__[0]; |
|||
void (**p)(void); |
|||
|
|||
if (i == -1) { |
|||
for (i = 1; __DTOR_LIST__[i] != NULL; i++) |
|||
; |
|||
i--; |
|||
} |
|||
p = __DTOR_LIST__ + i; |
|||
while (i--) |
|||
(**p--)(); |
|||
} |
|||
|
|||
static void |
|||
__ctors() |
|||
{ |
|||
void (**p)(void) = __CTOR_LIST__ + 1; |
|||
|
|||
while (*p) |
|||
(**p++)(); |
|||
} |
|||
|
|||
void |
|||
__init() |
|||
{ |
|||
static int initialized = 0; |
|||
|
|||
/*
|
|||
* Call global constructors. |
|||
* Arrange to call global destructors at exit. |
|||
*/ |
|||
if (!initialized) { |
|||
initialized = 1; |
|||
__ctors(); |
|||
} |
|||
} |
|||
|
|||
void |
|||
__fini() |
|||
{ |
|||
/*
|
|||
* Call global destructors. |
|||
*/ |
|||
__dtors(); |
|||
} |
|||
|
|||
@ -0,0 +1,50 @@ |
|||
/* $Id: crtend.c,v 1.1.1.1 2006/09/14 01:59:08 root Exp $ */ |
|||
|
|||
/*
|
|||
* Copyright (c) 2001-2002 Opsycon AB (www.opsycon.se / www.opsycon.com) |
|||
* |
|||
* Redistribution and use in source and binary forms, with or without |
|||
* modification, are permitted provided that the following conditions |
|||
* are met: |
|||
* 1. Redistributions of source code must retain the above copyright |
|||
* notice, this list of conditions and the following disclaimer. |
|||
* 2. Redistributions in binary form must reproduce the above copyright |
|||
* notice, this list of conditions and the following disclaimer in the |
|||
* documentation and/or other materials provided with the distribution. |
|||
* 3. All advertising materials mentioning features or use of this software |
|||
* must display the following acknowledgement: |
|||
* This product includes software developed by Opsycon AB, Sweden. |
|||
* 4. The name of the author may not be used to endorse or promote products |
|||
* derived from this software without specific prior written permission. |
|||
* |
|||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS |
|||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
|||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
|||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY |
|||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
|||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
|||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
|||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
|||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
|||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
|||
* SUCH DAMAGE. |
|||
* |
|||
*/ |
|||
#include <sys/cdefs.h> |
|||
|
|||
typedef void (*func_ptr) (void); |
|||
|
|||
#define NULL 0 |
|||
|
|||
static func_ptr __CTOR_END__[1] __attribute__ ((section (".ctors"))) = { |
|||
(func_ptr)(NULL) |
|||
}; |
|||
static func_ptr __DTOR_END__[1] __attribute__ ((section (".ctors"))) = { |
|||
(func_ptr)(NULL) |
|||
}; |
|||
|
|||
int __cl__ __P((void)); |
|||
int __cl__() |
|||
{ |
|||
return((int)&__CTOR_END__ + (int)&__DTOR_END__); |
|||
} |
|||
@ -0,0 +1,3 @@ |
|||
#define NCS5536 1 |
|||
#define NPCI 1 |
|||
#define NKB3310 0 |
|||
@ -0,0 +1 @@ |
|||
#define NELF32ONLY 0 |
|||
@ -0,0 +1 @@ |
|||
#define NETHER 1 |
|||
@ -0,0 +1 @@ |
|||
#define NFD 0 |
|||
@ -0,0 +1,6 @@ |
|||
#define NFLASH 0 |
|||
#define NMOD_FLASH_AMD 1 |
|||
#define NMOD_FLASH_INTEL 1 |
|||
#define NMOD_FLASH_SST 1 |
|||
#define NMOD_FLASH_WINBOND 0 |
|||
#define NMOD_FLASH_ST 0 |
|||
@ -0,0 +1 @@ |
|||
#define NGZIP 1 |
|||
@ -0,0 +1 @@ |
|||
#define NIDE_CD 1 |
|||
@ -0,0 +1,142 @@ |
|||
/*
|
|||
* MACHINE GENERATED: DO NOT EDIT |
|||
* |
|||
* ioconf.c, from "Bonito.2g1a" |
|||
*/ |
|||
|
|||
#include "mainbus.h" |
|||
#if NMAINBUS > 0 |
|||
#include <sys/param.h> |
|||
#include <sys/device.h> |
|||
|
|||
extern struct cfdriver mainbus_cd; |
|||
extern struct cfdriver pcibr_cd; |
|||
extern struct cfdriver usb_cd; |
|||
extern struct cfdriver localbus_cd; |
|||
extern struct cfdriver syn_cd; |
|||
extern struct cfdriver pci_cd; |
|||
extern struct cfdriver rtl_cd; |
|||
extern struct cfdriver pciide_cd; |
|||
extern struct cfdriver ppb_cd; |
|||
extern struct cfdriver uhci_cd; |
|||
extern struct cfdriver ohci_cd; |
|||
extern struct cfdriver wd_cd; |
|||
extern struct cfdriver ide_cd_cd; |
|||
|
|||
extern struct cfattach mainbus_ca; |
|||
extern struct cfattach pcibr_ca; |
|||
extern struct cfattach usb_ca; |
|||
extern struct cfattach localbus_ca; |
|||
extern struct cfattach syn_ca; |
|||
extern struct cfattach pci_ca; |
|||
extern struct cfattach rtl_ca; |
|||
extern struct cfattach pciide_ca; |
|||
extern struct cfattach ppb_ca; |
|||
extern struct cfattach uhci_ca; |
|||
extern struct cfattach ohci_ca; |
|||
extern struct cfattach wd_ca; |
|||
extern struct cfattach ide_cd_ca; |
|||
|
|||
|
|||
/* locators */ |
|||
static int loc[2] = { |
|||
-1, -1, |
|||
}; |
|||
|
|||
#ifndef MAXEXTRALOC |
|||
#define MAXEXTRALOC 32 |
|||
#endif |
|||
int extraloc[MAXEXTRALOC]; |
|||
int nextraloc = MAXEXTRALOC; |
|||
int uextraloc = 0; |
|||
|
|||
char *locnames[] = { |
|||
"base", |
|||
"bus", |
|||
"dev", |
|||
"function", |
|||
"channel", |
|||
"drive", |
|||
}; |
|||
|
|||
/* each entry is an index into locnames[]; -1 terminates */ |
|||
short locnamp[] = { |
|||
-1, 0, -1, 1, -1, 1, -1, 2, |
|||
3, -1, 4, 5, -1, |
|||
}; |
|||
|
|||
/* size of parent vectors */ |
|||
int pv_size = 14; |
|||
|
|||
/* parent vectors */ |
|||
short pv[14] = { |
|||
1, 9, -1, 11, 10, -1, 6, -1, 8, -1, 3, -1, 0, -1, |
|||
}; |
|||
|
|||
#define NORM FSTATE_NOTFOUND |
|||
#define STAR FSTATE_STAR |
|||
#define DNRM FSTATE_DNOTFOUND |
|||
#define DSTR FSTATE_DSTAR |
|||
|
|||
struct cfdata cfdata[] = { |
|||
/* attachment driver unit state loc flags parents nm ivstubs starunit1 */ |
|||
/* 0: mainbus0 at root */ |
|||
{&mainbus_ca, &mainbus_cd, 0, NORM, loc, 0, pv+ 2, 0, 0, 0}, |
|||
/* 1: pcibr0 at mainbus0 */ |
|||
{&pcibr_ca, &pcibr_cd, 0, NORM, loc, 0, pv+12, 0, 0, 0}, |
|||
/* 2: usb* at ohci*|uhci* */ |
|||
{&usb_ca, &usb_cd, 0, STAR, loc, 0, pv+ 3, 0, 0, 0}, |
|||
/* 3: localbus0 at mainbus0 */ |
|||
{&localbus_ca, &localbus_cd, 0, NORM, loc, 0, pv+12, 0, 0, 0}, |
|||
/* 4: syn0 at localbus0 base -1 */ |
|||
{&syn_ca, &syn_cd, 0, NORM, loc+ 1, 0, pv+10, 1, 0, 0}, |
|||
/* 5: syn1 at localbus0 base -1 */ |
|||
{&syn_ca, &syn_cd, 1, NORM, loc+ 1, 0, pv+10, 1, 0, 1}, |
|||
/* 6: pci* at pcibr0|ppb* bus -1 */ |
|||
{&pci_ca, &pci_cd, 0, STAR, loc+ 1, 0, pv+ 0, 3, 0, 0}, |
|||
/* 7: rtl* at pci* dev -1 function -1 */ |
|||
{&rtl_ca, &rtl_cd, 0, STAR, loc+ 0, 0, pv+ 6, 7, 0, 0}, |
|||
/* 8: pciide* at pci* dev -1 function -1 */ |
|||
{&pciide_ca, &pciide_cd, 0, STAR, loc+ 0, 0, pv+ 6, 7, 0, 0}, |
|||
/* 9: ppb* at pci* dev -1 function -1 */ |
|||
{&ppb_ca, &ppb_cd, 0, STAR, loc+ 0, 0, pv+ 6, 7, 0, 0}, |
|||
/* 10: uhci* at pci* dev -1 function -1 */ |
|||
{&uhci_ca, &uhci_cd, 0, STAR, loc+ 0, 0, pv+ 6, 7, 0, 0}, |
|||
/* 11: ohci* at pci* dev -1 function -1 */ |
|||
{&ohci_ca, &ohci_cd, 0, STAR, loc+ 0, 0, pv+ 6, 7, 0, 0}, |
|||
/* 12: wd0 at pciide* channel -1 drive -1 */ |
|||
{&wd_ca, &wd_cd, 0, NORM, loc+ 0, 0, pv+ 8, 10, 0, 0}, |
|||
/* 13: ide_cd* at pciide* channel -1 drive -1 */ |
|||
{&ide_cd_ca, &ide_cd_cd, 0, STAR, loc+ 0, 0x1, pv+ 8, 10, 0, 0}, |
|||
{0}, |
|||
{0}, |
|||
{0}, |
|||
{0}, |
|||
{0}, |
|||
{0}, |
|||
{0}, |
|||
{0}, |
|||
{(struct cfattach *)-1} |
|||
}; |
|||
|
|||
short cfroots[] = { |
|||
0 /* mainbus0 */, |
|||
-1 |
|||
}; |
|||
|
|||
int cfroots_size = 2; |
|||
|
|||
/* pseudo-devices */ |
|||
extern void loopattach (int); |
|||
|
|||
char *pdevnames[] = { |
|||
"loop", |
|||
}; |
|||
|
|||
int pdevnames_size = 1; |
|||
|
|||
struct pdevinit pdevinit[] = { |
|||
{ loopattach, 1 }, |
|||
{ 0, 0 } |
|||
}; |
|||
#endif /* NMAINBUS */ |
|||
@ -0,0 +1 @@ |
|||
#define NISO9660 1 |
|||
@ -0,0 +1,2 @@ |
|||
#define NLOGFILE 0 |
|||
#define NRAMFILES 1 |
|||
@ -0,0 +1 @@ |
|||
#define NLOOPDEV 0 |
|||
@ -0,0 +1 @@ |
|||
../../../../sys/arch/mips/include |
|||
@ -0,0 +1 @@ |
|||
#define NMAINBUS 1 |
|||
@ -0,0 +1,2 @@ |
|||
#define NMOD_DEBUGGER 1 |
|||
#define NCMD_L 1 |
|||
@ -0,0 +1 @@ |
|||
#define NMOD_DISPLAY 1 |
|||
@ -0,0 +1 @@ |
|||
#define NMOD_FRAMEBUFFER 0 |
|||
@ -0,0 +1,4 @@ |
|||
#define NMOD_LOAD 0 |
|||
#define NMOD_FASTLOAD 0 |
|||
#define NMOD_ELFLOAD 1 |
|||
#define NMOD_S3LOAD 1 |
|||
@ -0,0 +1 @@ |
|||
#define NMOD_S3LOAD 1 |
|||
@ -0,0 +1 @@ |
|||
#define NMOD_SISFB 0 |
|||
@ -0,0 +1 @@ |
|||
#define NMOD_SMI502 0 |
|||
@ -0,0 +1 @@ |
|||
#define NMOD_SMI712 0 |
|||
@ -0,0 +1,2 @@ |
|||
#define NMOD_SYMBOLS 1 |
|||
#define NCMD_SYM 0 |
|||
@ -0,0 +1,3 @@ |
|||
#define NMOD_TOD 0 |
|||
#define NHAVE_TOD 1 |
|||
#define NCMD_DATE 1 |
|||
@ -0,0 +1,2 @@ |
|||
#define NMOD_USB_KBD 1 |
|||
#define NMOD_USB 1 |
|||
@ -0,0 +1 @@ |
|||
#define NMOD_USB_OHCI 1 |
|||
@ -0,0 +1 @@ |
|||
#define NMOD_USB_STORAGE 1 |
|||
@ -0,0 +1 @@ |
|||
#define NMOD_USB_UHCI 1 |
|||
@ -0,0 +1,2 @@ |
|||
#define NMOD_VESA 0 |
|||
#define NMOD_FRAMEBUFFER 0 |
|||
@ -0,0 +1 @@ |
|||
#define NMOD_VGACON 1 |
|||
@ -0,0 +1 @@ |
|||
#define NMOD_X86EMU 1 |
|||
@ -0,0 +1 @@ |
|||
#define NMOD_X86EMU_INT10 0 |
|||
@ -0,0 +1,38 @@ |
|||
AUTOLOAD |
|||
BONITOEL |
|||
BOOT_PARAM |
|||
CONFIG_CACHE_64K_4WAY |
|||
CONFIG_SLOW_PCI_FOR_BROKENDEV |
|||
CONS_BAUD=B115200 |
|||
DEVBD2E |
|||
DEVBD2F_CS5536 |
|||
DEVBD2F_CS5536_WY810 |
|||
FLOATINGPT |
|||
FOR_GXEMUL |
|||
HAVE_NVENV |
|||
HAVE_TOD |
|||
IDECD |
|||
INET |
|||
INPUT_FROM_BOTH |
|||
INTERFACE_3A780E |
|||
KBD_CHECK_FAST |
|||
LOONGSON_2G1A |
|||
LS2GPLUS_KBD |
|||
MIPS |
|||
MY40IO |
|||
MY61IO |
|||
NOPCINAMES |
|||
NOSNOOP |
|||
NVRAM_IN_FLASH |
|||
OUTPUT_TO_BOTH |
|||
PCI_IDSEL_CS5536=0xe |
|||
SST008A |
|||
SYSTYPE=\"Bonito\" |
|||
TARGETNAME=\"Bonito\" |
|||
TEST_CS5536_USE_OTG |
|||
USE_SUPERIO_UART |
|||
VESAFB |
|||
VGAROM_IN_BIOS |
|||
VGA_BASE=0xb0000000 |
|||
VGA_NO_ROM |
|||
spi_mod |
|||
@ -0,0 +1,96 @@ |
|||
/* $Id: param.c,v 1.1.1.1 2006/09/14 01:59:08 root Exp $ */ |
|||
/*
|
|||
* Copyright (c) 1980, 1986, 1989 Regents of the University of California. |
|||
* All rights reserved. |
|||
* |
|||
* Redistribution and use in source and binary forms, with or without |
|||
* modification, are permitted provided that the following conditions |
|||
* are met: |
|||
* 1. Redistributions of source code must retain the above copyright |
|||
* notice, this list of conditions and the following disclaimer. |
|||
* 2. Redistributions in binary form must reproduce the above copyright |
|||
* notice, this list of conditions and the following disclaimer in the |
|||
* documentation and/or other materials provided with the distribution. |
|||
* 3. All advertising materials mentioning features or use of this software |
|||
* must display the following acknowledgement: |
|||
* This product includes software developed by the University of |
|||
* California, Berkeley and its contributors. |
|||
* 4. Neither the name of the University nor the names of its contributors |
|||
* may be used to endorse or promote products derived from this software |
|||
* without specific prior written permission. |
|||
* |
|||
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND |
|||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
|||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
|||
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE |
|||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
|||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
|||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
|||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
|||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
|||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
|||
* SUCH DAMAGE. |
|||
* |
|||
* @(#)param.c 7.20 (Berkeley) 6/27/91 |
|||
*/ |
|||
|
|||
#include "sys/param.h" |
|||
#include "sys/systm.h" |
|||
#include "sys/callout.h" |
|||
#include "sys/filedesc.h" |
|||
#include "sys/mbuf.h" |
|||
|
|||
/*
|
|||
* System parameter formulae. |
|||
* |
|||
* This file is copied into each directory where we compile |
|||
* the kernel; it should be modified there to suit local taste |
|||
* if necessary. |
|||
* |
|||
* Compiled with -DHZ=xx -DTIMEZONE=x -DDST=x |
|||
*/ |
|||
|
|||
#ifndef HZ |
|||
#define HZ 100 |
|||
#endif |
|||
|
|||
int hz; |
|||
int tick; |
|||
|
|||
#ifndef TIMEZONE |
|||
#define TIMEZONE 0 |
|||
#endif |
|||
#ifndef DST |
|||
#define DST 0 |
|||
#endif |
|||
struct timezone tz; |
|||
|
|||
#ifndef NPROC |
|||
#define NPROC 3 |
|||
#endif |
|||
|
|||
int ncallout; |
|||
int nmbclusters; |
|||
int maxfiles; |
|||
|
|||
/*
|
|||
* These have to be allocated somewhere; allocating |
|||
* them here forces loader errors if this file is omitted |
|||
* (if they've been externed everywhere else; hah!). |
|||
*/ |
|||
struct callout *callout; |
|||
|
|||
|
|||
void |
|||
paraminit () |
|||
{ |
|||
hz = HZ; |
|||
tick = 1000000 / HZ; |
|||
|
|||
tz.tz_minuteswest = TIMEZONE; |
|||
tz.tz_dsttime = DST; |
|||
|
|||
ncallout = 16 + NPROC; |
|||
nmbclusters = NMBCLUSTERS; |
|||
maxfiles = NDFILE * NPROC; |
|||
} |
|||
@ -0,0 +1,2 @@ |
|||
#define NPCI 1 |
|||
#define NCS5536 1 |
|||
@ -0,0 +1 @@ |
|||
#define NPCIBR 1 |
|||
Binary file not shown.
Binary file not shown.
@ -0,0 +1 @@ |
|||
#define NRAMFILES 1 |
|||
@ -0,0 +1 @@ |
|||
#define NRAW_ETHER 0 |
|||
@ -0,0 +1,778 @@ |
|||
|
|||
//extern onintr(int a,int *b);
|
|||
//#include "mips/cpu.h"
|
|||
#include <prid.h> |
|||
#include <stdio.h> |
|||
#include <sys/sys/signal.h> |
|||
#ifdef R3081 |
|||
#include "r3081.h" |
|||
#endif |
|||
#ifdef R3041 |
|||
#include "r3041.h" |
|||
#endif |
|||
|
|||
#include "ri.h" |
|||
|
|||
#ifdef GODSONEV1 |
|||
int global_div_num=0; |
|||
#endif |
|||
|
|||
extern int do_ri (struct pt_regs *xcp); |
|||
int __compute_return_epc(struct pt_regs *regs); |
|||
static unsigned long |
|||
mips_get_word_l(struct pt_regs *xcp, void *va, int *perr) |
|||
{ |
|||
*perr = 0; |
|||
return(*(unsigned long *)va); |
|||
} |
|||
|
|||
static int |
|||
mips_put_word_l(struct pt_regs *xcp, void *va, unsigned long val) |
|||
{ |
|||
*(unsigned long *)va = val; |
|||
return 0; |
|||
} |
|||
|
|||
static int emu_lwl(struct pt_regs * regs,mips_instruction ir,vaddr_t_l emulpc) |
|||
{ int err = 0; |
|||
/*the "ir" is the instruction causing the exception*/ |
|||
/*get the real address,perhaps the address is not word aligned*/ |
|||
void *va = REG_TO_VA_l (regs->regs[MIPSInst_RS(ir)])+ MIPSInst_SIMM(ir); |
|||
|
|||
unsigned long addr = 0; |
|||
unsigned long emul_pc = (unsigned long)emulpc; |
|||
|
|||
unsigned long little_three_bits; |
|||
unsigned long value,value_tmp; |
|||
|
|||
// printf("emu_lwl\r\n");
|
|||
|
|||
/*compute the correct position in the RT*/ |
|||
/*note !!!!: we have supposed the CPU is little_Endianness and status regiester's RE bit =0 */ |
|||
/*little Endianness*/ |
|||
little_three_bits = (unsigned long)va&(0x7); |
|||
value_tmp = regs->regs[MIPSInst_RT(ir)]; |
|||
switch(little_three_bits) { |
|||
case 0: |
|||
case 4: |
|||
/*must check lwl valid*/ |
|||
addr = (unsigned long) va; |
|||
check_axs(emul_pc,addr,4); |
|||
value = mips_get_word_l(regs,va,&err); |
|||
if(err){ |
|||
return SIGBUS; |
|||
} |
|||
value<<=24; |
|||
value_tmp &= 0xffffff; |
|||
regs->regs[MIPSInst_RT(ir)] =value_tmp|value; |
|||
break; |
|||
|
|||
case 1: |
|||
case 5: |
|||
addr = (unsigned long)va -1; |
|||
check_axs(emul_pc,addr,4); |
|||
value = mips_get_word_l(regs,(void *)((unsigned long) va-1),&err); |
|||
if(err){ |
|||
return SIGBUS; |
|||
} |
|||
value<<=16; |
|||
value_tmp&=0xffff; |
|||
regs->regs[MIPSInst_RT(ir)] =value_tmp|value; |
|||
break; |
|||
|
|||
case 2: |
|||
case 6: |
|||
addr = (unsigned long)va - 2; |
|||
check_axs(emul_pc,addr,4); |
|||
value = mips_get_word_l(regs,(void *)((unsigned long)va-2),&err); |
|||
if(err){ |
|||
return SIGBUS; |
|||
|
|||
} |
|||
value<<=8; |
|||
value_tmp &= 0xff; |
|||
regs->regs[MIPSInst_RT(ir)] =value_tmp|value; |
|||
break; |
|||
|
|||
case 3: |
|||
case 7: |
|||
addr = (unsigned long)va - 3; |
|||
check_axs(emul_pc,addr,4); |
|||
value = mips_get_word_l(regs,(void *)((unsigned long)va-3),&err); |
|||
if(err){ |
|||
return SIGBUS; |
|||
}; |
|||
regs->regs[MIPSInst_RT(ir)] = value; |
|||
break; |
|||
} /*swith ended*/ |
|||
return 0; |
|||
|
|||
} |
|||
|
|||
static int emu_lwr(struct pt_regs *regs,mips_instruction ir,vaddr_t_l emulpc) |
|||
{ int err = 0; |
|||
/*the "ir" is the instruction causing the exception*/ |
|||
/*get the real address,perhaps the address is not word aligned*/ |
|||
void *va = REG_TO_VA_l (regs->regs[MIPSInst_RS(ir)]) |
|||
+ MIPSInst_SIMM(ir); |
|||
unsigned long addr; |
|||
unsigned long emul_pc = (unsigned long)emulpc; |
|||
unsigned long little_three_bits; |
|||
unsigned long value,value_tmp; |
|||
|
|||
// printf("emu_lwr\r\n");
|
|||
|
|||
/*compute the correct position in the RT*/ |
|||
/*note !!!!: we have supposed the CPU is little_Endianness and status regiester's RE bit =0 */ |
|||
little_three_bits = (unsigned long)va&(0x7); |
|||
value_tmp = regs->regs[MIPSInst_RT(ir)]; |
|||
switch(little_three_bits) { |
|||
case 0: |
|||
case 4: |
|||
/*must check lwl valid*/ |
|||
addr = (unsigned long)va ; |
|||
check_axs(emul_pc,addr,4); |
|||
value = mips_get_word_l(regs,va,&err); |
|||
if(err){ |
|||
return SIGBUS; |
|||
} |
|||
regs->regs[MIPSInst_RT(ir)] =value; |
|||
break; |
|||
|
|||
case 1: |
|||
case 5: |
|||
addr = (unsigned long)va -1; |
|||
check_axs(emul_pc,addr,4); |
|||
value = mips_get_word_l(regs,(void *)((unsigned long)va-1),&err); |
|||
if(err){ |
|||
return SIGBUS; |
|||
} |
|||
value>>=8; |
|||
value_tmp&=0xff000000; |
|||
regs->regs[MIPSInst_RT(ir)] =value_tmp|value; |
|||
break; |
|||
|
|||
case 2: |
|||
case 6: |
|||
addr = (unsigned long)va-2; |
|||
check_axs(emul_pc,addr,4); |
|||
value = mips_get_word_l(regs,(void *)((unsigned long)va-2),&err); |
|||
if(err){ |
|||
return SIGBUS; |
|||
|
|||
} |
|||
value>>=16; |
|||
value_tmp &= 0xffff0000; |
|||
regs->regs[MIPSInst_RT(ir)] =value_tmp|value; |
|||
break; |
|||
|
|||
case 3: |
|||
case 7: |
|||
addr = (unsigned long)va -3; |
|||
check_axs(emul_pc,addr,4); |
|||
value = mips_get_word_l(regs,(void *)((unsigned long)va-3),&err); |
|||
if(err){ |
|||
return SIGBUS; |
|||
}; |
|||
value>>=24; |
|||
value_tmp &= 0xffffff00; |
|||
regs->regs[MIPSInst_RT(ir)] = value_tmp|value; |
|||
break; |
|||
} /*swith ended*/ |
|||
return 0; |
|||
} |
|||
|
|||
static int emu_swl(struct pt_regs *regs,mips_instruction ir, vaddr_t_l emulpc) |
|||
{ |
|||
int err = 0; |
|||
/*the "ir" is the instruction causing the exception*/ |
|||
/*get the real address,perhaps the address is not word aligned*/ |
|||
void *va = REG_TO_VA_l (regs->regs[MIPSInst_RS(ir)]) |
|||
+ MIPSInst_SIMM(ir); |
|||
unsigned long addr; |
|||
unsigned long emul_pc = (unsigned long)emulpc; |
|||
unsigned long little_three_bits; |
|||
unsigned long value,value_tmp; |
|||
|
|||
// printf("emu_swl\r\n");
|
|||
|
|||
/*compute the correct position in the RT*/ |
|||
/*note !!!!: we have supposed the CPU is little_Endianness and status re
|
|||
* giester's RE bit =0 */ |
|||
little_three_bits = (unsigned long)va&(0x7); |
|||
value_tmp = regs->regs[MIPSInst_RT(ir)]; |
|||
switch(little_three_bits) { |
|||
case 0: |
|||
case 4: |
|||
addr = (unsigned long)va; |
|||
check_axs(emul_pc,addr,4); |
|||
value_tmp >>= 24; |
|||
value = mips_get_word_l(regs,va,&err); |
|||
if(err){ |
|||
return SIGBUS; |
|||
} |
|||
value &=0xffffff00; |
|||
value |= value_tmp; |
|||
if(mips_put_word_l(regs,va,value)){ |
|||
return SIGBUS; |
|||
} |
|||
break; |
|||
case 1: |
|||
case 5: |
|||
addr = (unsigned long)va -1; |
|||
check_axs(emul_pc,addr,4); |
|||
value_tmp >>= 16; |
|||
value = mips_get_word_l(regs,(void *)((unsigned long)va-1),&err); |
|||
if(err){ |
|||
return SIGBUS; |
|||
} |
|||
value &=0xffff0000; |
|||
value |= value_tmp; |
|||
if(mips_put_word_l(regs,(void *)((unsigned long)va-1),value)){ |
|||
return SIGBUS; |
|||
} |
|||
break; |
|||
case 2: |
|||
case 6: |
|||
addr = (unsigned long)va - 2; |
|||
check_axs(emul_pc,addr,4); |
|||
value_tmp >>= 8; |
|||
value = mips_get_word_l(regs,(void *)((unsigned long)va-2),&err); |
|||
if(err){ |
|||
return SIGBUS; |
|||
} |
|||
value &=0xff000000; |
|||
value |= value_tmp; |
|||
if(mips_put_word_l(regs,(void *)((unsigned long)va-2),value)){ |
|||
return SIGBUS; |
|||
} |
|||
break; |
|||
case 3: |
|||
case 7: |
|||
addr = (unsigned long)va - 3; |
|||
check_axs(emul_pc,addr,4); |
|||
value = value_tmp; |
|||
|
|||
if(mips_put_word_l(regs,(void *)((unsigned long)va-3),value)){ |
|||
return SIGBUS; |
|||
} |
|||
break; |
|||
} |
|||
return 0; |
|||
|
|||
} |
|||
|
|||
static int emu_swr(struct pt_regs *regs,mips_instruction ir, vaddr_t_l emulpc) |
|||
{ |
|||
int err = 0; |
|||
/*the "ir" is the instruction causing the exception*/ |
|||
/*get the real address,perhaps the address is not word aligned*/ |
|||
void *va = REG_TO_VA_l (regs->regs[MIPSInst_RS(ir)]) |
|||
+ MIPSInst_SIMM(ir); |
|||
unsigned long addr; |
|||
unsigned long emul_pc = (unsigned long)emulpc; |
|||
|
|||
|
|||
unsigned long little_three_bits; |
|||
unsigned long value,value_tmp; |
|||
|
|||
// printf("emu_swr\r\n");
|
|||
|
|||
/*compute the correct position in the RT*/ |
|||
/*note !!!!: we have supposed the CPU is little_Endianness and status re
|
|||
* giester's RE bit =0 */ |
|||
little_three_bits = (unsigned long)va&(0x7); |
|||
value_tmp = regs->regs[MIPSInst_RT(ir)]; |
|||
switch(little_three_bits) { |
|||
case 0: |
|||
case 4: |
|||
addr = (unsigned long) va; |
|||
check_axs(emul_pc,addr,4); |
|||
value = value_tmp; |
|||
if(mips_put_word_l(regs,va,value)){ |
|||
return SIGBUS; |
|||
} |
|||
break; |
|||
case 1: |
|||
case 5: |
|||
addr = (unsigned long)va -1; |
|||
check_axs(emul_pc,addr,4); |
|||
value_tmp <<= 8; |
|||
value = mips_get_word_l(regs,(void *)((unsigned long)va-1),&err); |
|||
if(err){ |
|||
return SIGBUS; |
|||
} |
|||
value &=0xff; |
|||
value |= value_tmp; |
|||
if(mips_put_word_l(regs,(void *)((unsigned long)va-1),value)){ |
|||
return SIGBUS; |
|||
} |
|||
break; |
|||
case 2: |
|||
case 6: |
|||
addr = (unsigned long)va - 2; |
|||
check_axs(emul_pc,addr,4); |
|||
value_tmp <<= 16; |
|||
value = mips_get_word_l(regs,(void *)((unsigned long)va-2),&err); |
|||
if(err){ |
|||
return SIGBUS; |
|||
} |
|||
value &=0xffff; |
|||
value |= value_tmp; |
|||
if(mips_put_word_l(regs,(void *)((unsigned long)va-2),value)){ |
|||
return SIGBUS; |
|||
} |
|||
break; |
|||
case 3: |
|||
case 7: |
|||
addr = (unsigned long)va -3; |
|||
check_axs(emul_pc,addr,4); |
|||
value_tmp <<= 24; |
|||
value = mips_get_word_l(regs,(void *)((unsigned long)va-3),&err); |
|||
if(err){ |
|||
return SIGBUS; |
|||
} |
|||
|
|||
value &= 0xffffff; |
|||
value |= value_tmp; |
|||
if(mips_put_word_l(regs,(void *)((unsigned long)va-3),value)){ |
|||
return SIGBUS; |
|||
} |
|||
break; |
|||
} |
|||
return 0; |
|||
|
|||
} |
|||
|
|||
|
|||
|
|||
static int emu_div(struct pt_regs *regs,mips_instruction ir) |
|||
{ |
|||
int x,y; |
|||
int flag = 0; |
|||
int quotient = 0,remainder = 0; |
|||
unsigned int absx,absy,absquotient = 0,absremainder = 0,bm = 1; |
|||
/*the "ir" is the instruction causing the exception*/ |
|||
x = regs->regs[MIPSInst_RS(ir)]; |
|||
y = regs->regs[MIPSInst_RT(ir)]; |
|||
|
|||
#ifdef __test_ri__ |
|||
//printf("now in function:emu_div().\r\n");
|
|||
#endif |
|||
|
|||
if( y == 0 ) {/*overflow*/ |
|||
return SIGABRT; |
|||
} |
|||
/*x and y ·ûºÅÊÇ·ñ²»Í¬*/ |
|||
flag = (x&0x80000000)^(y&0x80000000); |
|||
|
|||
/*get the abs(x)*/ |
|||
if(x<0){ |
|||
absx = (unsigned int)-x; |
|||
}else { |
|||
absx = (unsigned int)x; |
|||
} |
|||
|
|||
/*get the abs(y)*/ |
|||
if(y<0){ |
|||
absy = (unsigned int) -y; |
|||
}else { |
|||
absy = (unsigned int)y; |
|||
} |
|||
|
|||
/*caculate the absx/absy*/ |
|||
if(absx<absy) {/*don't need to calculate*/ |
|||
absquotient = 0; |
|||
absremainder = absx; |
|||
goto end; |
|||
} |
|||
|
|||
while(!(absy&0x80000000)) |
|||
{ absy<<=1; |
|||
if(absx<absy){ |
|||
absy>>= 1; |
|||
break; |
|||
} |
|||
bm<<=1; |
|||
} |
|||
|
|||
for(;bm;bm>>=1){ |
|||
if(absx>=absy){ |
|||
absx -= absy; |
|||
absquotient |= bm; |
|||
if(absx == 0) |
|||
break; |
|||
} |
|||
absy >>= 1; |
|||
} |
|||
absremainder = absx; |
|||
|
|||
end: |
|||
if( flag ){/*·ûºÅÏàÒì*/ |
|||
quotient = -absquotient; |
|||
remainder = x-quotient*y; |
|||
}else { |
|||
quotient = absquotient; |
|||
remainder = x - quotient*y; |
|||
} |
|||
|
|||
regs->lo =(unsigned long)quotient; |
|||
regs->hi = (unsigned long)remainder; |
|||
|
|||
#ifdef __test_ri__ |
|||
// printf("x is: %d\r\n",x);
|
|||
// printf("y is: %d\r\n",y);
|
|||
// printf("result is: %d (:\r\n",quotient);
|
|||
#endif |
|||
|
|||
return 0; |
|||
} |
|||
|
|||
static int emu_divu(struct pt_regs *regs,mips_instruction ir) |
|||
{ |
|||
unsigned int x,y,bm=1; |
|||
unsigned int quotient = 0,remainder = 0; |
|||
|
|||
/*the "ir" is the instruction causing the exception*/ |
|||
x = regs->regs[MIPSInst_RS(ir)]; |
|||
y = regs->regs[MIPSInst_RT(ir)]; |
|||
|
|||
if( y == 0 ) {/*overflow*/ |
|||
return SIGABRT; |
|||
} |
|||
|
|||
if(x<y) {/*don't need to calculate*/ |
|||
quotient = 0; |
|||
remainder = x; |
|||
goto end; |
|||
} |
|||
|
|||
while(!(y&0x80000000)) |
|||
{ y<<=1; |
|||
if(x<y){ |
|||
y>>= 1; |
|||
break; |
|||
} |
|||
bm<<=1; |
|||
} |
|||
|
|||
for(;bm;bm>>=1){ |
|||
if(x>=y){ |
|||
x -= y; |
|||
quotient |= bm; |
|||
if(x == 0) |
|||
break; |
|||
} |
|||
y >>= 1; |
|||
|
|||
} |
|||
remainder = x; |
|||
end: |
|||
regs->lo = quotient; |
|||
regs->hi = remainder; |
|||
return 0; |
|||
|
|||
} |
|||
|
|||
/*
|
|||
* Compute the return address and do emulate branch simulation, if required. |
|||
*/ |
|||
#define EFAULT 1 |
|||
int __compute_return_epc(struct pt_regs *regs) |
|||
{ |
|||
unsigned int *addr, bit, fcr31; |
|||
long epc; |
|||
mips_instruction insn; |
|||
|
|||
epc = regs->cp0_epc; |
|||
if (epc & 3) { |
|||
printf("%s: unaligned epc - sending SIGBUS.\n"); |
|||
// force_sig(SIGBUS, current);
|
|||
return -EFAULT; |
|||
} |
|||
|
|||
/*
|
|||
* Read the instruction |
|||
*/ |
|||
addr = (unsigned int *) (unsigned long) epc; |
|||
#if 0 |
|||
if (__get_user(insn, addr)) { |
|||
printf("%s: bad epc value - sending SIGSEGV.\n"); |
|||
// force_sig(SIGSEGV, current);
|
|||
return -EFAULT; |
|||
} |
|||
#endif |
|||
//bjzheng add __get_user is prevent page_fault exception,if this occurs,load from disk,but now my whole code is in ram.
|
|||
insn=*addr; |
|||
// printf("instruction is %x",insn);
|
|||
regs->regs[0] = 0; |
|||
switch (MIPSInst_OPCODE(insn)) { |
|||
/*
|
|||
* jr and jalr are in r_format format. |
|||
*/ |
|||
case spec_op: |
|||
switch (MIPSInst_FUNC(insn)) { |
|||
case jalr_op: |
|||
regs->regs[MIPSInst_RD(insn)] = epc + 8; |
|||
/* Fall through */ |
|||
case jr_op: |
|||
regs->cp0_epc = regs->regs[MIPSInst_RS(insn)]; |
|||
break; |
|||
} |
|||
break; |
|||
|
|||
/*
|
|||
* This group contains: |
|||
* bltz_op, bgez_op, bltzl_op, bgezl_op, |
|||
* bltzal_op, bgezal_op, bltzall_op, bgezall_op. |
|||
*/ |
|||
case bcond_op: |
|||
switch (MIPSInst_RT(insn)) { |
|||
case bltz_op: |
|||
case bltzl_op: |
|||
if ((long)regs->regs[MIPSInst_RS(insn)] < 0) |
|||
epc = epc + 4 + (MIPSInst_SIMM(insn) << 2); |
|||
else |
|||
epc += 8; |
|||
regs->cp0_epc = epc; |
|||
break; |
|||
|
|||
case bgez_op: |
|||
case bgezl_op: |
|||
if ((long)regs->regs[MIPSInst_RS(insn)] >= 0) |
|||
epc = epc + 4 + (MIPSInst_SIMM(insn) << 2); |
|||
else |
|||
epc += 8; |
|||
regs->cp0_epc = epc; |
|||
break; |
|||
|
|||
case bltzal_op: |
|||
case bltzall_op: |
|||
regs->regs[31] = epc + 8; |
|||
if ((long)regs->regs[MIPSInst_RS(insn)] < 0) |
|||
epc = epc + 4 + (MIPSInst_SIMM(insn) << 2); |
|||
else |
|||
epc += 8; |
|||
regs->cp0_epc = epc; |
|||
break; |
|||
|
|||
case bgezal_op: |
|||
case bgezall_op: |
|||
regs->regs[31] = epc + 8; |
|||
if ((long)regs->regs[MIPSInst_RS(insn)] >= 0) |
|||
epc = epc + 4 + (MIPSInst_SIMM(insn) << 2); |
|||
else |
|||
epc += 8; |
|||
regs->cp0_epc = epc; |
|||
break; |
|||
} |
|||
break; |
|||
|
|||
/*
|
|||
* These are unconditional and in j_format. |
|||
*/ |
|||
case jal_op: |
|||
regs->regs[31] = regs->cp0_epc + 8; |
|||
case j_op: |
|||
epc += 4; |
|||
epc >>= 28; |
|||
epc <<= 28; |
|||
epc |= (MIPSInst_JTARGET(insn) << 2); |
|||
regs->cp0_epc = epc; |
|||
break; |
|||
|
|||
/*
|
|||
* These are conditional and in i_format. |
|||
*/ |
|||
case beq_op: |
|||
case beql_op: |
|||
if (regs->regs[MIPSInst_RS(insn)] == |
|||
regs->regs[MIPSInst_RT(insn)]) |
|||
epc = epc + 4 + (MIPSInst_SIMM(insn) << 2); |
|||
else |
|||
epc += 8; |
|||
regs->cp0_epc = epc; |
|||
break; |
|||
|
|||
case bne_op: |
|||
case bnel_op: |
|||
if (regs->regs[MIPSInst_RS(insn)] != |
|||
regs->regs[MIPSInst_RT(insn)]) |
|||
epc = epc + 4 + (MIPSInst_SIMM(insn) << 2); |
|||
else |
|||
epc += 8; |
|||
regs->cp0_epc = epc; |
|||
break; |
|||
|
|||
case blez_op: /* not really i_format */ |
|||
case blezl_op: |
|||
/* rt field assumed to be zero */ |
|||
if ((long)regs->regs[MIPSInst_RS(insn)] <= 0) |
|||
epc = epc + 4 + (MIPSInst_SIMM(insn) << 2); |
|||
else |
|||
epc += 8; |
|||
regs->cp0_epc = epc; |
|||
break; |
|||
|
|||
case bgtz_op: |
|||
case bgtzl_op: |
|||
/* rt field assumed to be zero */ |
|||
if ((long)regs->regs[MIPSInst_RS(insn)] > 0) |
|||
epc = epc + 4 + (MIPSInst_SIMM(insn) << 2); |
|||
else |
|||
epc += 8; |
|||
regs->cp0_epc = epc; |
|||
break; |
|||
|
|||
/*
|
|||
* And now the FPA/cp1 branch instructions. |
|||
*/ |
|||
case cop1_op: |
|||
#ifdef CONFIG_MIPS_FPU_EMULATOR |
|||
if(!(mips_cpu.options & MIPS_CPU_FPU)) |
|||
fcr31 = current->tss.fpu.soft.sr; |
|||
else |
|||
#endif |
|||
asm ("cfc1\t%0,$31":"=r" (fcr31)); |
|||
bit = (MIPSInst_RT(insn) >> 2); |
|||
bit += (bit != 0); |
|||
bit += 23; |
|||
switch (MIPSInst_RT(insn)) { |
|||
case 0: /* bc1f */ |
|||
case 2: /* bc1fl */ |
|||
if (~fcr31 & (1 << bit)) |
|||
epc = epc + 4 + (MIPSInst_SIMM(insn) << 2); |
|||
else |
|||
epc += 8; |
|||
regs->cp0_epc = epc; |
|||
break; |
|||
|
|||
case 1: /* bc1t */ |
|||
case 3: /* bc1tl */ |
|||
if (fcr31 & (1 << bit)) |
|||
epc = epc + 4 + (MIPSInst_SIMM(insn) << 2); |
|||
else |
|||
epc += 8; |
|||
regs->cp0_epc = epc; |
|||
break; |
|||
} |
|||
break; |
|||
} |
|||
|
|||
return 0; |
|||
} |
|||
|
|||
int do_ri (struct pt_regs *xcp) |
|||
{ |
|||
mips_instruction ir; |
|||
vaddr_t_l emulpc; |
|||
vaddr_t_l contpc; |
|||
int err = 0; |
|||
int sig; |
|||
|
|||
ir = mips_get_word_l(xcp, REG_TO_VA_l xcp->cp0_epc, &err); |
|||
if (err) { |
|||
return SIGBUS; |
|||
} |
|||
|
|||
/* XXX NEC Vr54xx bug workaround */ |
|||
/* if ((xcp->cp0_cause & CAUSEF_BD) && !isBranchInstr (&ir))
|
|||
xcp->cp0_cause &= ~CAUSEF_BD;*/ |
|||
|
|||
if (xcp->cp0_cause & CAUSEF_BD) { |
|||
|
|||
/* The instruction to be emulated is in a branch delay slot
|
|||
* which means that we have to emulate the branch instruction |
|||
* BEFORE we do the emulating instruction. |
|||
* This branch could be a COP1 branch |
|||
*/ |
|||
|
|||
emulpc = REG_TO_VA_l(xcp->cp0_epc + 4); /* Snapshot emulation target */ |
|||
|
|||
#ifndef __bjzheng__ |
|||
if( __compute_return_epc(xcp)) {/*compute the return address*/ |
|||
#ifdef DBG |
|||
_mon_printf ("failed to emulate branch at %p\n", |
|||
REG_TO_VA_l (xcp->cp0_epc)); |
|||
#endif |
|||
return -1;; |
|||
} |
|||
#endif |
|||
|
|||
ir = mips_get_word_l(xcp, emulpc, &err); |
|||
if (err) { |
|||
return SIGBUS; |
|||
} |
|||
contpc = REG_TO_VA_l xcp->cp0_epc; |
|||
|
|||
} else { /* not in the Branch delay slot*/ |
|||
emulpc = REG_TO_VA_l xcp->cp0_epc; |
|||
contpc = REG_TO_VA_l xcp->cp0_epc + 4; |
|||
} |
|||
|
|||
switch(MIPSInst_OPCODE(ir)) { |
|||
case lwl_op: /*lwl instruction*/ |
|||
sig = emu_lwl(xcp,ir,emulpc); |
|||
if( sig!=0) { /*emul has failed*/ |
|||
return sig; |
|||
} |
|||
break; |
|||
|
|||
case lwr_op:/*lwr instruction*/ |
|||
sig = emu_lwr(xcp,ir,emulpc); |
|||
if ( sig != 0){ |
|||
/*emulate has failed!\n");*/ |
|||
return sig; |
|||
} |
|||
break; |
|||
|
|||
case swl_op: |
|||
sig = emu_swl(xcp,ir,emulpc); |
|||
if( sig!=0 ) { /*emul has failed!*/ |
|||
printf("emu_swl error\r\n"); |
|||
return sig; |
|||
} |
|||
break; |
|||
|
|||
case swr_op: |
|||
sig = emu_swr(xcp,ir,emulpc); |
|||
if( sig!=0 ) { /*emul has failed!*/ |
|||
printf("emu_swr error\r\n"); |
|||
return sig; |
|||
} |
|||
break; |
|||
case spec_op: |
|||
switch (MIPSInst_FUNC(ir)){ |
|||
case div_op:/*div_op*/ |
|||
#ifdef GODSONEV1 |
|||
global_div_num++; |
|||
#endif |
|||
sig = emu_div(xcp,ir); |
|||
if(sig) { |
|||
return sig; |
|||
} |
|||
break; |
|||
case divu_op:/* divu_op:*/ |
|||
#ifdef GODSONEV1 |
|||
global_div_num++; |
|||
#endif |
|||
sig = emu_divu(xcp,ir); |
|||
if(sig) { |
|||
return sig; |
|||
} |
|||
break; |
|||
default:; |
|||
|
|||
} |
|||
|
|||
default:; |
|||
} |
|||
|
|||
|
|||
/*we do it*/ |
|||
xcp->cp0_epc = VA_TO_REG_l(contpc); |
|||
xcp->cp0_cause &= ~CAUSEF_BD; |
|||
return sig; |
|||
|
|||
} |
|||
|
|||
@ -0,0 +1 @@ |
|||
#define NSD 0 |
|||
@ -0,0 +1 @@ |
|||
../../../../Targets/Bonito2g1a/include |
|||
@ -0,0 +1 @@ |
|||
#define NTCP 1 |
|||
@ -0,0 +1,6 @@ |
|||
char ostype[] = "PMON2000"; |
|||
char osrelease[] = "3.2"; |
|||
char osversion[] = "Bonito.2g1a#56"; |
|||
char sccs[8] = { ' ', ' ', ' ', ' ', '@', '(', '#', ')' }; |
|||
char vers[] = |
|||
"PMON2000 3.2 (Bonito.2g1a) #56: Wed Sep 17 17:32:16 CST 2014 commit 8d4a76530ed774ffbf0bdd1c69d842a2d26b7f16 Author: lixuefeng <lixuefeng@loongson.cn> Date: Tue Sep 9 17:22:20 2014 +0800 "; |
|||
@ -0,0 +1 @@ |
|||
#define VERS "PMON2000 3.2 (Bonito.2g1a) #56: Wed Sep 17 17:32:16 CST 2014\r\n" |
|||
@ -0,0 +1 @@ |
|||
57 |
|||
@ -0,0 +1 @@ |
|||
#define NWD 1 |
|||
@ -0,0 +1,4 @@ |
|||
include "Targets/Bonito3u/conf/Bonito.3uv2" |
|||
#include "Targets/Bonito2fdev/conf/Bonito.2fdev.via" |
|||
#include "Targets/Bonito2fdev/conf/Bonito.2fdev.sm502" |
|||
#include "Targets/Bonito2fdev/conf/Bonito.2feva" |
|||
@ -0,0 +1,209 @@ |
|||
# $Id: Bonito,v 1.1.1.1 2006/09/14 01:59:09 root Exp $ # # GENERIC configuration for Galileo EV64240 # # This file is supposed to be included by target file after # endian has been defined. |
|||
# |
|||
machine Bonito3u mips # CPU Architecture, Platform |
|||
config pmon |
|||
option VGAROM_IN_BIOS |
|||
|
|||
# |
|||
# Define target endian |
|||
# |
|||
makeoptions ENDIAN=EL # Little endian version. |
|||
|
|||
|
|||
#include "conf/GENERIC_ALL" |
|||
|
|||
# |
|||
# System Name and Target Name |
|||
# |
|||
option SYSTYPE="\"Bonito\"" |
|||
option TARGETNAME="\"Bonito\"" |
|||
|
|||
# |
|||
# Platform options |
|||
# |
|||
option BONITOEL |
|||
option DEVBD2E |
|||
option MIPS |
|||
option INET |
|||
|
|||
select mod_flash_amd # AMD flash device programming |
|||
select mod_flash_intel # intel flash device programming |
|||
select mod_flash_sst # intel flash device programming |
|||
select mod_debugger # Debugging module |
|||
select mod_symbols # Symbol table handling |
|||
select mod_s3load # Srecord loading |
|||
#select mod_fastload # LSI Fastload |
|||
select mod_elfload # ELF loading |
|||
|
|||
# |
|||
# Command selection. Selects pmon commands |
|||
# |
|||
select cmd_newmt |
|||
select cmd_setup |
|||
select cmd_about # Display info about PMON |
|||
select cmd_boot # Boot wrapper |
|||
select cmd_mycmd |
|||
#select cmd_mycmd_debug |
|||
select cmd_newmt |
|||
select cmd_cache # Cache enabling |
|||
#select cmd_call # Call a function command |
|||
select cmd_date # Time of day command |
|||
select cmd_env # Full blown environment command set |
|||
select cmd_flash # Flash programming cmds |
|||
select cmd_hist # Command history |
|||
select cmd_ifaddr # Interface address command |
|||
select cmd_l # Disassemble |
|||
select cmd_mem # Memory manipulation commands |
|||
select cmd_more # More paginator |
|||
select cmd_mt # Simple memory test command |
|||
select cmd_misc # Reboot & Flush etc. |
|||
#select cmd_stty # TTY setings command |
|||
select cmd_tr # Host port-through command |
|||
select cmd_devls # Device list |
|||
select cmd_set # As cmd_env but not req. cmd_hist |
|||
select cmd_testdisk |
|||
# |
|||
select cmd_shell # Shell commands, vers, help, eval |
|||
# |
|||
# |
|||
# Platform options |
|||
# |
|||
select mod_uart_ns16550 # Standard UART driver |
|||
select mod_display |
|||
#option CONS_BAUD=B9600 |
|||
option CONS_BAUD=B115200 |
|||
select ext2 |
|||
select fatfs |
|||
select ramfiles |
|||
select mod_x86emu # X86 emulation for VGA |
|||
option MY40IO |
|||
#select mod_x86emu_int10 |
|||
option MY61IO |
|||
option VGA_BASE=0xb0000000 |
|||
select mod_vgacon |
|||
#select sis315e |
|||
#option SIS315E |
|||
option VGA_NO_ROM # display card has no rom |
|||
#select mod_sisfb |
|||
option NOPCINAMES # Save some space for x86emu |
|||
#option FASTBOOT |
|||
#select vt82c686 #via686a/b code |
|||
|
|||
#select mod_framebuffer |
|||
#select mod_smi712 # X86 emulation for VGA |
|||
#option SMI712 |
|||
#option X800x600 |
|||
#option CONFIG_VIDEO_16BPP |
|||
#option CONFIG_VIDEO_8BPP_INDEX |
|||
|
|||
# |
|||
# Functional options. |
|||
# |
|||
option NOSNOOP # Caches are no-snooping |
|||
|
|||
# |
|||
# HAVE options. What tgt level provide |
|||
# |
|||
#option HAVE_TOD # Time-Of-Day clock |
|||
option HAVE_NVENV # Platform has non-volatile env mem |
|||
option HAVE_LOGO # Output splash logo |
|||
option USE_SUPERIO_UART |
|||
#option VESAFB |
|||
#option USE_LEGACY_RTC |
|||
#option GODSONEV2A |
|||
#option LINUX_PC |
|||
#option LONGMENG |
|||
#option RADEON7000 |
|||
#option DEBUG_EMU_VGA |
|||
option AUTOLOAD |
|||
#option CONFIG_PCI0_LARGE_MEM |
|||
#option CONFIG_PCI0_HUGE_MEM |
|||
#option CONFIG_PCI0_GAINT_MEM |
|||
option CONFIG_CACHE_64K_4WAY |
|||
option NVRAM_IN_FLASH |
|||
|
|||
# |
|||
# Now the Machine specification |
|||
# |
|||
mainbus0 at root |
|||
localbus0 at mainbus0 |
|||
#fd0 at mainbus0 |
|||
pcibr0 at mainbus0 |
|||
#pcibr1 at mainbus0 |
|||
pci* at pcibr? |
|||
ppb* at pci? dev ? function ? # PCI-PCI bridges |
|||
pci* at ppb? bus ? |
|||
|
|||
#### USB |
|||
#uhci* at pci? dev ? function ? |
|||
|
|||
#### SCSI support |
|||
#siop* at pci? dev ? function ? # Symbios/NCR 53c... |
|||
#scsibus* at siop? |
|||
#sd* at scsibus? target ? lun ? |
|||
#cd* at scsibus? target ? lun ? |
|||
|
|||
#### Networking Devices |
|||
#gt0 at localbus? base 4 |
|||
#gt1 at localbus? base 5 |
|||
#gt2 at localbus? base 6 |
|||
# fxp normally only used for debugging (enable/disable both) |
|||
#fxp* at pci? dev ? function ? # Intel 82559 Device |
|||
#inphy* at mii? phy ? # Intel 82555 PHYs |
|||
rtl* at pci? dev ? function ? |
|||
rtk* at pci? dev ? function ? |
|||
#em* at pci? dev ? function ? |
|||
#uhci* at pci? dev ? function ? |
|||
#ohci0 at pci? dev ? function ? |
|||
#usb* at usbbus ? |
|||
#ohci1 at pci? dev ? function ? |
|||
|
|||
#select mod_usb |
|||
#select mod_usb_storage |
|||
#select mod_usb_uhci |
|||
#select mod_usb_ohci |
|||
#select mod_usb_kbd |
|||
|
|||
|
|||
#### IDE controllers |
|||
pciide* at pci ? dev ? function ? flags 0x0000 |
|||
#atp* at pci? dev ? function ? #sata atp8620 |
|||
#wd* at atp? channel ? drive ? flags 0x0000 |
|||
#sata* at atp? |
|||
|
|||
#### IDE hard drives |
|||
wd0 at pciide? channel ? drive ? flags 0x0000 |
|||
|
|||
cmdide* at pci ? dev ? function ? flags 0x0000 |
|||
wd* at cmdide? channel ? drive ? flags 0x0000 |
|||
|
|||
#### Pseudo devices |
|||
pseudo-device loop 1 # network loopback |
|||
|
|||
syn0 at localbus0 |
|||
syn1 at localbus0 |
|||
select gmac |
|||
|
|||
ide_cd* at pciide? channel ? drive ? flags 0x0001 |
|||
select iso9660 |
|||
option IDECD |
|||
select cmd_testfire |
|||
#option HAVE_NB_SERIAL |
|||
#option USE_ENVMAC |
|||
#option LOOKLIKE_PC |
|||
#select cmd_lwdhcp |
|||
#select cmd_bootp |
|||
option FOR_GXEMUL |
|||
select fatfs |
|||
option FLOATINGPT |
|||
option COM3_BASE_ADDR=0xbfe001e0 |
|||
#option WDC_NORESET |
|||
select gzip |
|||
option INPUT_FROM_BOTH |
|||
option OUTPUT_TO_BOTH |
|||
option KBD_CHECK_FAST |
|||
option LS2GPLUS_KBD |
|||
option TEST_CS5536_USE_OTG |
|||
option TEST_USB_HOST |
|||
option CONFIG_SLOW_PCI_FOR_BROKENDEV |
|||
|
|||
@ -0,0 +1,231 @@ |
|||
# $Id: Bonito,v 1.1.1.1 2006/09/14 01:59:09 root Exp $ # # GENERIC configuration for Galileo EV64240 # # This file is supposed to be included by target file after # endian has been defined. |
|||
# |
|||
machine Bonito2g1a mips # CPU Architecture, Platform |
|||
config pmon |
|||
option VGAROM_IN_BIOS |
|||
|
|||
# |
|||
# Define target endian |
|||
# |
|||
makeoptions ENDIAN=EL # Little endian version. |
|||
|
|||
|
|||
#include "conf/GENERIC_ALL" |
|||
|
|||
# |
|||
# System Name and Target Name |
|||
# |
|||
option SYSTYPE="\"Bonito\"" |
|||
option TARGETNAME="\"Bonito\"" |
|||
|
|||
# |
|||
# Platform options |
|||
# |
|||
option BONITOEL |
|||
option DEVBD2E |
|||
option MIPS |
|||
option INET |
|||
option LOONGSON_2G1A |
|||
option BOOT_PARAM |
|||
|
|||
select mod_flash_amd # AMD flash device programming |
|||
select mod_flash_intel # intel flash device programming |
|||
select mod_flash_sst # intel flash device programming |
|||
select mod_debugger # Debugging module |
|||
select mod_symbols # Symbol table handling |
|||
select mod_s3load # Srecord loading |
|||
#select mod_fastload # LSI Fastload |
|||
select mod_elfload # ELF loading |
|||
|
|||
option SST008A |
|||
# |
|||
# Command selection. Selects pmon commands |
|||
# |
|||
select cmd_newmt |
|||
select cmd_setup |
|||
select cmd_about # Display info about PMON |
|||
select cmd_boot # Boot wrapper |
|||
select cmd_mycmd |
|||
#select cmd_mycmd_debug |
|||
select cmd_newmt |
|||
select cmd_cache # Cache enabling |
|||
#select cmd_call # Call a function command |
|||
select cmd_date # Time of day command |
|||
select cmd_env # Full blown environment command set |
|||
select cmd_flash # Flash programming cmds |
|||
select cmd_hist # Command history |
|||
select cmd_ifaddr # Interface address command |
|||
select cmd_l # Disassemble |
|||
select cmd_mem # Memory manipulation commands |
|||
select cmd_more # More paginator |
|||
select cmd_mt # Simple memory test command |
|||
select cmd_misc # Reboot & Flush etc. |
|||
#select cmd_stty # TTY setings command |
|||
select cmd_tr # Host port-through command |
|||
select cmd_devls # Device list |
|||
select cmd_set # As cmd_env but not req. cmd_hist |
|||
#select cmd_testdisk |
|||
# |
|||
select cmd_shell # Shell commands, vers, help, eval |
|||
# |
|||
# |
|||
# Platform options |
|||
# |
|||
select mod_uart_ns16550 # Standard UART driver |
|||
select mod_display |
|||
#option CONS_BAUD=B9600 |
|||
option CONS_BAUD=B115200 |
|||
select ext2 |
|||
select fatfs |
|||
select ramfiles |
|||
select mod_x86emu # X86 emulation for VGA |
|||
option MY40IO |
|||
#select mod_x86emu_int10 |
|||
option MY61IO |
|||
option VGA_BASE=0xb0000000 |
|||
select mod_vgacon |
|||
#select sis315e |
|||
#option SIS315E |
|||
option VGA_NO_ROM # display card has no rom |
|||
#select mod_sisfb |
|||
option NOPCINAMES # Save some space for x86emu |
|||
#option FASTBOOT |
|||
#select vt82c686 #via686a/b code |
|||
|
|||
#select mod_framebuffer |
|||
#select mod_smi712 # X86 emulation for VGA |
|||
#option SMI712 |
|||
#option X800x600 |
|||
#option X1024x768 |
|||
#option CONFIG_VIDEO_16BPP |
|||
#option CONFIG_VIDEO_8BPP_INDEX |
|||
|
|||
# |
|||
# Functional options. |
|||
# |
|||
option NOSNOOP # Caches are no-snooping |
|||
|
|||
# |
|||
# HAVE options. What tgt level provide |
|||
# |
|||
option HAVE_TOD # Time-Of-Day clock |
|||
option HAVE_NVENV # Platform has non-volatile env mem |
|||
#option HAVE_LOGO # Output splash logo |
|||
option USE_SUPERIO_UART |
|||
option VESAFB |
|||
#option USE_LEGACY_RTC |
|||
#option GODSONEV2A |
|||
#option LINUX_PC |
|||
#option LONGMENG |
|||
#option RADEON7000 |
|||
#option DEBUG_EMU_VGA |
|||
option AUTOLOAD |
|||
#option CONFIG_PCI0_LARGE_MEM |
|||
#option CONFIG_PCI0_HUGE_MEM |
|||
#option CONFIG_PCI0_GAINT_MEM |
|||
option CONFIG_CACHE_64K_4WAY |
|||
option NVRAM_IN_FLASH |
|||
option spi_mod |
|||
|
|||
# |
|||
# Now the Machine specification |
|||
# |
|||
mainbus0 at root |
|||
localbus0 at mainbus0 |
|||
#fd0 at mainbus0 |
|||
pcibr0 at mainbus0 |
|||
#pcibr1 at mainbus0 |
|||
pci* at pcibr? |
|||
ppb* at pci? dev ? function ? # PCI-PCI bridges |
|||
pci* at ppb? bus ? |
|||
|
|||
#### USB |
|||
uhci* at pci? dev ? function ? |
|||
ohci* at pci? dev ? function ? |
|||
usb* at usbbus ? |
|||
|
|||
select mod_usb |
|||
select mod_usb_storage |
|||
select mod_usb_uhci |
|||
select mod_usb_ohci |
|||
select mod_usb_kbd |
|||
|
|||
#### SCSI support |
|||
#siop* at pci? dev ? function ? # Symbios/NCR 53c... |
|||
#scsibus* at siop? |
|||
#sd* at scsibus? target ? lun ? |
|||
#cd* at scsibus? target ? lun ? |
|||
|
|||
#### Networking Devices |
|||
#gt0 at localbus? base 4 |
|||
#gt1 at localbus? base 5 |
|||
#gt2 at localbus? base 6 |
|||
# fxp normally only used for debugging (enable/disable both) |
|||
#fxp* at pci? dev ? function ? # Intel 82559 Device |
|||
#inphy* at mii? phy ? # Intel 82555 PHYs |
|||
rtl* at pci? dev ? function ? |
|||
#rtk* at pci? dev ? function ? |
|||
#em* at pci? dev ? function ? |
|||
#uhci* at pci? dev ? function ? |
|||
#ohci0 at pci? dev ? function ? |
|||
#usb* at usbbus ? |
|||
#ohci1 at pci? dev ? function ? |
|||
|
|||
#select mod_usb |
|||
#select mod_usb_storage |
|||
#select mod_usb_uhci |
|||
#select mod_usb_ohci |
|||
#select mod_usb_kbd |
|||
|
|||
|
|||
#### IDE controllers |
|||
pciide* at pci ? dev ? function ? flags 0x0000 |
|||
#atp* at pci? dev ? function ? #sata atp8620 |
|||
#wd* at atp? channel ? drive ? flags 0x0000 |
|||
#sata* at atp? |
|||
|
|||
#### IDE hard drives |
|||
wd0 at pciide? channel ? drive ? flags 0x0000 |
|||
|
|||
#cmdide* at pci ? dev ? function ? flags 0x0000 |
|||
#wd* at cmdide? channel ? drive ? flags 0x0000 |
|||
|
|||
#### Pseudo devices |
|||
pseudo-device loop 1 # network loopback |
|||
|
|||
syn0 at localbus0 |
|||
syn1 at localbus0 |
|||
select gmac |
|||
|
|||
ide_cd* at pciide? channel ? drive ? flags 0x0001 |
|||
select iso9660 |
|||
option IDECD |
|||
#select cmd_testfire |
|||
#option HAVE_NB_SERIAL |
|||
#option USE_ENVMAC |
|||
#option LOOKLIKE_PC |
|||
#select cmd_lwdhcp |
|||
#select cmd_bootp |
|||
option FOR_GXEMUL |
|||
select fatfs |
|||
option FLOATINGPT |
|||
option PCI_IDSEL_CS5536=14 |
|||
#option COM3_BASE_ADDR=0xbfe001e0 ????? |
|||
#option WDC_NORESET |
|||
select cs5536 |
|||
option DEVBD2F_CS5536 |
|||
option DEVBD2F_CS5536_WY810 |
|||
select gzip |
|||
option INPUT_FROM_BOTH |
|||
option OUTPUT_TO_BOTH |
|||
option KBD_CHECK_FAST |
|||
option LS2GPLUS_KBD |
|||
option TEST_CS5536_USE_OTG |
|||
#option TEST_USB_HOST |
|||
option CONFIG_SLOW_PCI_FOR_BROKENDEV |
|||
|
|||
select http |
|||
select tcp |
|||
|
|||
select cmd_main |
|||
option INTERFACE_3A780E |
|||
@ -0,0 +1,19 @@ |
|||
ifndef S |
|||
S:=$(shell cd ../../../..; pwd) |
|||
endif |
|||
TARGET= ${S}/Targets/Bonito2g1a |
|||
SUBTARGET?=Bonito |
|||
CPPFLAGS=-mips3 |
|||
|
|||
%OBJS |
|||
|
|||
%CFILES |
|||
|
|||
%SFILES |
|||
|
|||
%LOAD |
|||
|
|||
export CFILES OBJS SFILES |
|||
include ${S}/Makefile.inc |
|||
|
|||
%RULES |
|||
@ -0,0 +1,57 @@ |
|||
# $Id: files.Bonito |
|||
# |
|||
# Bonito Target specific files |
|||
# |
|||
|
|||
file Targets/Bonito2g1a/pci/pci_machdep.c |
|||
file Targets/Bonito2g1a/Bonito/tgt_machdep.c |
|||
file Targets/Bonito2g1a/pci/cs5536_io.c cs5536 |
|||
file Targets/Bonito2g1a/pci/cs5536_vsm.c cs5536 |
|||
|
|||
|
|||
define localbus { [base = -1 ] } |
|||
device localbus |
|||
attach localbus at mainbus |
|||
file Targets/Bonito2g1a/dev/localbus.c localbus |
|||
|
|||
#GMAC |
|||
file sys/dev/gmac/synopGMAC_Host.c |
|||
file sys/dev/gmac/synopGMAC_Dev.c |
|||
file sys/dev/gmac/synopGMAC_network_interface.c |
|||
file sys/dev/gmac/synopGMAC_pci_bus_interface.c |
|||
file sys/dev/gmac/synopGMAC_plat.c |
|||
|
|||
|
|||
device syn: ether, ifnet |
|||
attach syn at localbus |
|||
file sys/dev/gmac/if_gmac.c gmac |
|||
|
|||
# Ethernet driver for Discovery ethernet |
|||
device gt: ether, ifnet, ifmedia |
|||
attach gt at localbus |
|||
file sys/dev/ic/if_gt.c gt |
|||
|
|||
# |
|||
# Media Indepedent Interface (mii) |
|||
# |
|||
include "sys/dev/mii/files.mii" |
|||
|
|||
# Various PCI bridges |
|||
|
|||
include "sys/dev/pci/files.pci" |
|||
|
|||
# |
|||
# Machine-independent ATAPI drivers |
|||
# |
|||
|
|||
include "sys/dev/ata/files.ata" |
|||
|
|||
# |
|||
# SCSI framework |
|||
# |
|||
include "sys/scsi/files.scsi" |
|||
|
|||
# |
|||
# Custom application files |
|||
# |
|||
include "pmon/custom/files.custom" |
|||
@ -0,0 +1,105 @@ |
|||
|
|||
OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradbigmips", |
|||
"elf32-tradlittlemips") |
|||
OUTPUT_ARCH(mips) |
|||
ENTRY(_start) |
|||
SECTIONS |
|||
{ |
|||
|
|||
. = 0xffffffff8f010000; |
|||
.text : |
|||
{ |
|||
_ftext = . ; |
|||
*(.text) |
|||
*(.rodata) |
|||
*(.rodata1) |
|||
*(.reginfo) |
|||
*(.init) |
|||
*(.stub) |
|||
|
|||
*(.gnu.warning) |
|||
} =0 |
|||
_etext = .; |
|||
PROVIDE (etext = .); |
|||
.fini : { *(.fini) } =0 |
|||
.data : |
|||
{ |
|||
_fdata = . ; |
|||
*(.data) |
|||
. = ALIGN(32); |
|||
*(.data.align32) |
|||
. = ALIGN(64); |
|||
*(.data.align64) |
|||
. = ALIGN(128); |
|||
*(.data.align128) |
|||
. = ALIGN(4096); |
|||
*(.data.align4096) |
|||
CONSTRUCTORS |
|||
} |
|||
.data1 : { *(.data1) } |
|||
.ctors : |
|||
{ |
|||
__CTOR_LIST__ = .; |
|||
LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2) |
|||
*(.ctors) |
|||
LONG(0) |
|||
__CTOR_END__ = .; |
|||
} |
|||
.dtors : |
|||
{ |
|||
__DTOR_LIST__ = .; |
|||
LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2) |
|||
*(.dtors) |
|||
LONG(0) |
|||
__DTOR_END__ = .; |
|||
} |
|||
_gp = ALIGN(16) + 0x7ff0; |
|||
.got : |
|||
{ |
|||
*(.got.plt) *(.got) |
|||
} |
|||
|
|||
|
|||
|
|||
.sdata : { *(.sdata) } |
|||
.lit8 : { *(.lit8) } |
|||
.lit4 : { *(.lit4) } |
|||
_edata = .; |
|||
PROVIDE (edata = .); |
|||
__bss_start = .; |
|||
_fbss = .; |
|||
.sbss : { *(.sbss) *(.scommon) } |
|||
.bss : |
|||
{ |
|||
*(.dynbss) |
|||
*(.bss) |
|||
. = ALIGN(32); |
|||
*(.bss.align32) |
|||
. = ALIGN(64); |
|||
*(.bss.align64) |
|||
. = ALIGN(128); |
|||
*(.bss.align128) |
|||
. = ALIGN(4096); |
|||
*(.bss.align4096) |
|||
*(COMMON) |
|||
} |
|||
_end = . ; |
|||
PROVIDE (end = .); |
|||
|
|||
|
|||
.stab 0 : { *(.stab) } |
|||
.stabstr 0 : { *(.stabstr) } |
|||
|
|||
|
|||
|
|||
|
|||
.debug 0 : { *(.debug) } |
|||
.debug_srcinfo 0 : { *(.debug_srcinfo) } |
|||
.debug_aranges 0 : { *(.debug_aranges) } |
|||
.debug_pubnames 0 : { *(.debug_pubnames) } |
|||
.debug_sfnames 0 : { *(.debug_sfnames) } |
|||
.line 0 : { *(.line) } |
|||
|
|||
.gptab.sdata : { *(.gptab.data) *(.gptab.sdata) } |
|||
.gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) } |
|||
} |
|||
@ -0,0 +1,195 @@ |
|||
/* $Id: localbus.c,v 1.1.1.1 2006/09/14 01:59:09 root Exp $ */ |
|||
|
|||
/*
|
|||
* Copyright (c) 2001 Opsycon AB (www.opsycon.se) |
|||
* |
|||
* Redistribution and use in source and binary forms, with or without |
|||
* modification, are permitted provided that the following conditions |
|||
* are met: |
|||
* 1. Redistributions of source code must retain the above copyright |
|||
* notice, this list of conditions and the following disclaimer. |
|||
* 2. Redistributions in binary form must reproduce the above copyright |
|||
* notice, this list of conditions and the following disclaimer in the |
|||
* documentation and/or other materials provided with the distribution. |
|||
* 3. All advertising materials mentioning features or use of this software |
|||
* must display the following acknowledgement: |
|||
* This product includes software developed by Opsycon AB, Sweden. |
|||
* 4. The name of the author may not be used to endorse or promote products |
|||
* derived from this software without specific prior written permission. |
|||
* |
|||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS |
|||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
|||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
|||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY |
|||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
|||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
|||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
|||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
|||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
|||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
|||
* SUCH DAMAGE. |
|||
* |
|||
*/ |
|||
|
|||
/*
|
|||
* This is the localbus driver. It handles configuration of all |
|||
* devices on the Discovery localbus. |
|||
*/ |
|||
|
|||
#include <sys/param.h> |
|||
#include <sys/systm.h> |
|||
#include <sys/conf.h> |
|||
#include <sys/malloc.h> |
|||
#include <sys/device.h> |
|||
#include <sys/tty.h> |
|||
|
|||
#include <autoconf.h> |
|||
|
|||
#include <pmon/dev/gt64240reg.h> |
|||
|
|||
int localbusmatch __P((struct device *, void *, void *)); |
|||
void localbusattach __P((struct device *, struct device *, void *)); |
|||
int localbusprint __P((void *, const char *)); |
|||
void localbusscan __P((struct device *, void *)); |
|||
|
|||
|
|||
struct cfattach localbus_ca = { |
|||
sizeof(struct device), localbusmatch, localbusattach |
|||
}; |
|||
|
|||
struct cfdriver localbus_cd = { |
|||
NULL, "localbus", DV_DULL, 1 |
|||
}; |
|||
|
|||
int |
|||
localbusmatch(parent, match, aux) |
|||
struct device *parent; |
|||
void *match; |
|||
void *aux; |
|||
{ |
|||
return (1); |
|||
} |
|||
|
|||
int |
|||
localbusprint(aux, localbus) |
|||
void *aux; |
|||
const char *localbus; |
|||
{ |
|||
/* XXXX print flags */ |
|||
return (QUIET); |
|||
} |
|||
|
|||
|
|||
void |
|||
localbusscan(parent, match) |
|||
struct device *parent; |
|||
void *match; |
|||
{ |
|||
struct device *dev = match; |
|||
struct cfdata *cf = dev->dv_cfdata; |
|||
struct confargs lba; |
|||
bushook_t lbus; |
|||
|
|||
if (cf->cf_fstate == FSTATE_STAR) { |
|||
printf("localbus '*' devs not allowed!\n"); |
|||
free(dev, M_DEVBUF); |
|||
} |
|||
|
|||
if (cf->cf_loc[0] == -1) { |
|||
lba.ca_baseaddr = 0; |
|||
lba.ca_intr = 0; |
|||
lba.ca_nintr = 0; |
|||
} else { |
|||
lba.ca_baseaddr = cf->cf_loc[0]; |
|||
lba.ca_nintr= cf->cf_loc[1]; |
|||
lba.ca_intr = 0; |
|||
} |
|||
|
|||
lba.ca_bus = &lbus; |
|||
lba.ca_bus->bh_type = BUS_LOCAL; |
|||
lba.ca_bus->bh_matchname = NULL; |
|||
|
|||
#if 0 |
|||
lba.ca_iot = &sys_config.local; |
|||
lba.ca_memt = &sys_config.local; |
|||
#endif |
|||
|
|||
|
|||
if ((*cf->cf_attach->ca_match)(parent, dev, &lba) > 0) { |
|||
config_attach(parent, dev, &lba, localbusprint); |
|||
} |
|||
else { |
|||
free(dev, M_DEVBUF); |
|||
} |
|||
} |
|||
|
|||
void |
|||
localbusattach(parent, self, aux) |
|||
struct device *parent; |
|||
struct device *self; |
|||
void *aux; |
|||
{ |
|||
printf("\n"); |
|||
|
|||
config_scan(localbusscan, self); |
|||
} |
|||
|
|||
#if 0 |
|||
|
|||
void |
|||
gt64240_map() |
|||
{ |
|||
u_int32_t rval; |
|||
|
|||
static int gt64240_initialized; |
|||
|
|||
if(!gt64240_initialized) { |
|||
/*
|
|||
* Map GT register space. We map the entire chip at |
|||
* once since functions are scattered all over the |
|||
* address space and mapping functionwise would |
|||
* require a lot of small mappings. |
|||
* The objects gt64240_bt and gt64240_bh can |
|||
* be used by all functions require access to the GT. |
|||
*/ |
|||
if(bus_space_map(&sys_config.local, GT_REG(0), 65536, |
|||
0, >64240_bh) != 0 ) { |
|||
panic("localbus: unable to map GT64240 regs\n"); |
|||
} |
|||
gt64240_bt = &sys_config.local; |
|||
gt64240_initialized = 1; |
|||
|
|||
/*
|
|||
* Kill any active ethernet channels. |
|||
*/ |
|||
GT_WRITE(ETHERNET0_PORT_CONFIGURATION_REGISTER, 0); |
|||
GT_WRITE(ETHERNET1_PORT_CONFIGURATION_REGISTER, 0); |
|||
GT_WRITE(ETHERNET2_PORT_CONFIGURATION_REGISTER, 0); |
|||
GT_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER, 0); |
|||
GT_WRITE(ETHERNET1_SDMA_COMMAND_REGISTER, 0); |
|||
GT_WRITE(ETHERNET2_SDMA_COMMAND_REGISTER, 0); |
|||
|
|||
/*
|
|||
* Initialize the interrupt controller. Route MPP pins. |
|||
*/ |
|||
rval = GT_READ(MPP_CONTROL3); |
|||
rval &= 0xff0f00ff; /* Reset bits 29 and 27 */ |
|||
GT_WRITE(MPP_CONTROL3, rval); |
|||
|
|||
rval = GT_READ(MPP_CONTROL2); |
|||
rval &= 0xf00fffff; /* Reset bits 22 and 21 */ |
|||
GT_WRITE(MPP_CONTROL2, rval); |
|||
|
|||
rval = GT_READ(GPP_LEVEL_CONTROL); |
|||
rval |= 0x28600000; /* Active low transition == int */ |
|||
GT_WRITE(GPP_LEVEL_CONTROL, rval); |
|||
|
|||
rval = GT_READ(GPP_INTERRUPT_MASK); |
|||
rval |= 0x28600000; /* Enable PCI + Serial */ |
|||
GT_WRITE(GPP_INTERRUPT_MASK, rval); |
|||
/* Clear all pending ints. */ |
|||
GT_WRITE(GPP_INTERRUPT_CAUSE, 0); |
|||
} |
|||
return; |
|||
} |
|||
#endif |
|||
@ -0,0 +1,60 @@ |
|||
/* $Id: pflash_tgt.h,v 1.1.1.1 2006/09/14 01:59:09 root Exp $ */ |
|||
|
|||
/*
|
|||
* Copyright (c) 2000 Opsycon AB (www.opsycon.se) |
|||
* |
|||
* Redistribution and use in source and binary forms, with or without |
|||
* modification, are permitted provided that the following conditions |
|||
* are met: |
|||
* 1. Redistributions of source code must retain the above copyright |
|||
* notice, this list of conditions and the following disclaimer. |
|||
* 2. Redistributions in binary form must reproduce the above copyright |
|||
* notice, this list of conditions and the following disclaimer in the |
|||
* documentation and/or other materials provided with the distribution. |
|||
* 3. All advertising materials mentioning features or use of this software |
|||
* must display the following acknowledgement: |
|||
* This product includes software developed by |
|||
* Opsycon Open System Consulting AB, Sweden. |
|||
* 4. The name of the author may not be used to endorse or promote products |
|||
* derived from this software without specific prior written permission. |
|||
* |
|||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS |
|||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
|||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
|||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY |
|||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
|||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
|||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
|||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
|||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
|||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
|||
* SUCH DAMAGE. |
|||
* |
|||
*/ |
|||
|
|||
/*
|
|||
* Define a 'struct fl_map' init set for each flash area on the target. |
|||
*/ |
|||
|
|||
/* Note! Not requiered but prefered, sort in ascending address order */ |
|||
|
|||
/*
|
|||
* NOTE about 'width' codes. Usually the 'width' is the number of |
|||
* bytes that are accessed at the same time while the next value |
|||
* is the number of chips. Bytes per chips can be found by dividing |
|||
* 'width' with 'chips'. The code 9 for width is special to handle |
|||
* how the cp7000 addresses the AMD single chip when not mapped as |
|||
* boot device. |
|||
*/ |
|||
|
|||
#ifdef SST008A |
|||
#define FLASH_SIZE_BYTE 0x100000 |
|||
#else |
|||
#define FLASH_SIZE_BYTE 0x80000 |
|||
#endif |
|||
|
|||
#define TARGET_FLASH_DEVICES_16 \ |
|||
{ PHYS_TO_UNCACHED(BONITO_FLASH_BASE), FLASH_SIZE_BYTE, 1, 1, FL_BUS_8 }, \ |
|||
{ PHYS_TO_UNCACHED(0x1e000000), 0x02000000, 1, 1, FL_BUS_16 }, \ |
|||
{ 0x00000000, 0x00000000 } |
|||
|
|||
@ -0,0 +1,507 @@ |
|||
/*
|
|||
* Bonito Register Map |
|||
* Copyright (c) 1999 Algorithmics Ltd |
|||
* |
|||
* Algorithmics gives permission for anyone to use and modify this file |
|||
* without any obligation or license condition except that you retain |
|||
* this copyright message in any source redistribution in whole or part. |
|||
* |
|||
* Updated copies of this and other files can be found at |
|||
* ftp://ftp.algor.co.uk/pub/bonito/
|
|||
* |
|||
* Users of the Bonito controller are warmly recommended to contribute |
|||
* any useful changes back to Algorithmics (mail to |
|||
* bonito@algor.co.uk). |
|||
*/ |
|||
|
|||
/* Revision 1.48 autogenerated on 08/17/99 15:20:01 */ |
|||
|
|||
#ifndef _BONITO_H_ |
|||
|
|||
#ifdef __ASSEMBLER__ |
|||
//__ASSEMBLER__ is not defined
|
|||
/* offsets from base register */ |
|||
#define BONITO(x) (x) |
|||
|
|||
#else /* !__ASSEMBLER */ |
|||
extern char *heaptop; |
|||
|
|||
/* offsets from base pointer, this construct allows optimisation */ |
|||
/* static char * const _bonito = PA_TO_KVA1(BONITO_BASE); */ |
|||
/*#define BONITO(x) *(volatile unsigned long *)(PHYS_TO_UNCACHED(BONITO_REG_BASE)+(x))*/ |
|||
#define BONITO(x) *(volatile unsigned long *)(0xbfe00000+(x)) |
|||
#endif /* __ASSEMBLER__ */ |
|||
|
|||
#define RTC_INDEX_REG 0x70 |
|||
#define RTC_DATA_REG 0x71 |
|||
#define RTC_NVRAM_BASE 0x0e |
|||
|
|||
|
|||
#define COM1_BASE_ADDR 0xbfe001e0 |
|||
#define COM2_BASE_ADDR 0xbfd002f8 |
|||
#define COM3_BASE_ADDR 0xbfd003f8 |
|||
#ifndef COM3_BASE_ADDR |
|||
#define COM3_BASE_ADDR 0xbff003f8 |
|||
#endif |
|||
//#define NS16550HZ 1843200
|
|||
#define NS16550HZ 3686400 |
|||
/*********************************************************************/ |
|||
/*nvram define */ |
|||
/*********************************************************************/ |
|||
#ifdef NVRAM_IN_FLASH |
|||
# define NVRAM_SIZE 492 /*modified by tangyt*/ |
|||
# define NVRAM_SECSIZE 506 |
|||
# define ACTIVECOM_OFFS 492 /*added by tangyt*/ |
|||
# define MASTER_BRIDGE_OFFS 493 /*added by tangyt*/ |
|||
|
|||
#ifdef SST008A |
|||
# define NVRAM_OFFS 0x000ff000 |
|||
#else |
|||
# define NVRAM_OFFS 0x0007f000 |
|||
#endif |
|||
|
|||
# define ETHER_OFFS 494 /* Ethernet address base */ |
|||
# define ETHER1_OFFS 500 /* Ethernet address base */ |
|||
#else /* Use clock ram, 256 bytes only */ |
|||
# define NVRAM_SIZE 114 |
|||
# define NVRAM_SECSIZE NVRAM_SIZE /* Helper */ |
|||
# define NVRAM_OFFS 0 |
|||
# define ETHER_OFFS 108 /* Ethernet address base */ |
|||
# define ETHER1_OFFS 114 |
|||
#endif |
|||
|
|||
|
|||
#define TEST_CS5536_USE_EHCI |
|||
#define TEST_CS5536_USE_UDC |
|||
//#define TEST_CS5536_USE_OTG
|
|||
//#define TEST_USB_HOST
|
|||
//#define TEST_USB_DEVICE
|
|||
|
|||
/*********************************************************************/ |
|||
/*PCI map */ |
|||
/*********************************************************************/ |
|||
|
|||
#ifdef X86_LIKE_SPACE |
|||
/* To make address spaces alike with x86 system, we put sdram
|
|||
* start address at 0 and pci devices' start address at 0x14000000 for |
|||
* both CPU address space & PCI memory address space. |
|||
* |
|||
* We have 3 64M window in CPU address space to access PCI memory,but the |
|||
* legacy PCI start pci memory from 0x10000000, so we can use the same address to access |
|||
* them from cpu memory space. But to access the 0xc0000 vga ram, we have to |
|||
* reserve the first window. Only the last two are used for pci devices. |
|||
* --zfx 060716 |
|||
*/ |
|||
/* make sdram appear at both cpu & pci memory space 0,
|
|||
* so for dma the physical address can be directly used |
|||
* as bus address. --zfx 060716 |
|||
*/ |
|||
|
|||
#define PCI_MEM_SPACE_PCI_BASE 0x10000000 |
|||
#define PCI_LOCAL_MEM_PCI_BASE 0x00000000 |
|||
#define PCI_LOCAL_MEM_ISA_BASE 0x80000000 |
|||
#define PCI_LOCAL_REG_PCI_BASE 0x90000000 |
|||
|
|||
#else |
|||
|
|||
#define PCI_MEM_SPACE_PCI_BASE 0x00000000 |
|||
#define PCI_LOCAL_MEM_PCI_BASE 0x80000000 |
|||
#define PCI_LOCAL_MEM_ISA_BASE 0x00800000 |
|||
#define PCI_LOCAL_REG_PCI_BASE 0x90000000 |
|||
|
|||
#endif |
|||
|
|||
#define PCI_IO_SPACE_BASE 0x00000000 |
|||
|
|||
#define BONITO_BOOT_BASE 0x1fc00000 |
|||
#define BONITO_BOOT_SIZE 0x00100000 |
|||
#define BONITO_BOOT_TOP (BONITO_BOOT_BASE+BONITO_BOOT_SIZE-1) |
|||
#define BONITO_FLASH_BASE 0x1fc00000 |
|||
#define BONITO_FLASH_SIZE 0x03000000 |
|||
#define BONITO_FLASH_TOP (BONITO_FLASH_BASE+BONITO_FLASH_SIZE-1) |
|||
#define BONITO_SOCKET_BASE 0x1f800000 |
|||
#define BONITO_SOCKET_SIZE 0x00400000 |
|||
#define BONITO_SOCKET_TOP (BONITO_SOCKET_BASE+BONITO_SOCKET_SIZE-1) |
|||
#define BONITO_REG_BASE 0x1fe00000 |
|||
#define BONITO_REG_SIZE 0x00040000 |
|||
#define BONITO_REG_TOP (BONITO_REG_BASE+BONITO_REG_SIZE-1) |
|||
#define BONITO_DEV_BASE 0x1ff00000 |
|||
#define BONITO_DEV_SIZE 0x00100000 |
|||
#define BONITO_DEV_TOP (BONITO_DEV_BASE+BONITO_DEV_SIZE-1) |
|||
#define BONITO_PCILO_BASE 0x10000000 |
|||
#define BONITO_PCILO_BASE_VA 0xb0000000 |
|||
#define BONITO_PCILO_SIZE 0x0c000000 |
|||
#define BONITO_PCILO_TOP (BONITO_PCILO_BASE+BONITO_PCILO_SIZE-1) |
|||
#define BONITO_PCILO0_BASE 0x10000000 |
|||
#define BONITO_PCILO1_BASE 0x14000000 |
|||
#define BONITO_PCILO2_BASE 0x18000000 |
|||
#define BONITO_PCIHI_BASE 0x20000000 |
|||
#define BONITO_PCIHI_SIZE 0x20000000 |
|||
#define BONITO_PCIHI_TOP (BONITO_PCIHI_BASE+BONITO_PCIHI_SIZE-1) |
|||
#define BONITO_PCIIO_BASE 0x1fd00000 |
|||
#define BONITO_PCIIO_BASE_VA 0xbfd00000 |
|||
#define BONITO_PCIIO_SIZE 0x00010000 |
|||
#define BONITO_PCIIO_TOP (BONITO_PCIIO_BASE+BONITO_PCIIO_SIZE-1) |
|||
#define BONITO_PCICFG_BASE 0x1fe80000 |
|||
#define BONITO_PCICFG_SIZE 0x00080000 |
|||
#define BONITO_PCICFG_TOP (BONITO_PCICFG_BASE+BONITO_PCICFG_SIZE-1) |
|||
|
|||
|
|||
/* Bonito Register Bases */ |
|||
|
|||
#define BONITO_PCICONFIGBASE 0x00 |
|||
#define BONITO_REGBASE 0x100 |
|||
|
|||
|
|||
/* PCI Configuration Registers */ |
|||
|
|||
#define BONITO_PCI_REG(x) BONITO(BONITO_PCICONFIGBASE + (x)) |
|||
#define BONITO_PCIDID BONITO_PCI_REG(0x00) |
|||
#define BONITO_PCICMD BONITO_PCI_REG(0x04) |
|||
#define BONITO_PCICLASS BONITO_PCI_REG(0x08) |
|||
#define BONITO_PCILTIMER BONITO_PCI_REG(0x0c) |
|||
#define BONITO_PCIBASE0 BONITO_PCI_REG(0x10) |
|||
#define BONITO_PCIBASE1 BONITO_PCI_REG(0x14) |
|||
#define BONITO_PCIBASE2 BONITO_PCI_REG(0x18) |
|||
#define BONITO_PCIEXPRBASE BONITO_PCI_REG(0x30) |
|||
#define BONITO_PCIINT BONITO_PCI_REG(0x3c) |
|||
|
|||
#define BONITO_PCICMD_PERR_CLR 0x80000000 |
|||
#define BONITO_PCICMD_SERR_CLR 0x40000000 |
|||
#define BONITO_PCICMD_MABORT_CLR 0x20000000 |
|||
#define BONITO_PCICMD_MTABORT_CLR 0x10000000 |
|||
#define BONITO_PCICMD_TABORT_CLR 0x08000000 |
|||
#define BONITO_PCICMD_MPERR_CLR 0x01000000 |
|||
#define BONITO_PCICMD_PERRRESPEN 0x00000040 |
|||
#define BONITO_PCICMD_ASTEPEN 0x00000080 |
|||
#define BONITO_PCICMD_SERREN 0x00000100 |
|||
#define BONITO_PCILTIMER_BUSLATENCY 0x0000ff00 |
|||
#define BONITO_PCILTIMER_BUSLATENCY_SHIFT 8 |
|||
|
|||
|
|||
|
|||
|
|||
/* 1. Bonito h/w Configuration */ |
|||
/* Power on register */ |
|||
|
|||
#define BONITO_BONPONCFG BONITO(BONITO_REGBASE + 0x00) |
|||
|
|||
#define BONITO_BONPONCFG_SYSCONTROLLERRD 0x00040000 |
|||
#define BONITO_BONPONCFG_ROMCS1SAMP 0x00020000 |
|||
#define BONITO_BONPONCFG_ROMCS0SAMP 0x00010000 |
|||
#define BONITO_BONPONCFG_CPUBIGEND 0x00004000 |
|||
#define BONITO_BONPONCFG_CPUPARITY 0x00002000 |
|||
#define BONITO_BONPONCFG_CPUTYPE 0x00000007 |
|||
#define BONITO_BONPONCFG_CPUTYPE_SHIFT 0 |
|||
#define BONITO_BONPONCFG_PCIRESET_OUT 0x00000008 |
|||
#define BONITO_BONPONCFG_IS_ARBITER 0x00000010 |
|||
#define BONITO_BONPONCFG_ROMBOOT 0x000000c0 |
|||
#define BONITO_BONPONCFG_ROMBOOT_SHIFT 6 |
|||
|
|||
#define BONITO_BONPONCFG_ROMBOOT_FLASH (0x0<<BONITO_BONPONCFG_ROMBOOT_SHIFT) |
|||
#define BONITO_BONPONCFG_ROMBOOT_SOCKET (0x1<<BONITO_BONPONCFG_ROMBOOT_SHIFT) |
|||
#define BONITO_BONPONCFG_ROMBOOT_SDRAM (0x2<<BONITO_BONPONCFG_ROMBOOT_SHIFT) |
|||
#define BONITO_BONPONCFG_ROMBOOT_CPURESET (0x3<<BONITO_BONPONCFG_ROMBOOT_SHIFT) |
|||
|
|||
#define BONITO_BONPONCFG_ROMCS0WIDTH 0x00000100 |
|||
#define BONITO_BONPONCFG_ROMCS1WIDTH 0x00000200 |
|||
#define BONITO_BONPONCFG_ROMCS0FAST 0x00000400 |
|||
#define BONITO_BONPONCFG_ROMCS1FAST 0x00000800 |
|||
#define BONITO_BONPONCFG_CONFIG_DIS 0x00000020 |
|||
|
|||
|
|||
/* Other Bonito configuration */ |
|||
|
|||
#define BONITO_BONGENCFG_OFFSET 0x4 |
|||
#define BONITO_BONGENCFG BONITO(BONITO_REGBASE + BONITO_BONGENCFG_OFFSET) |
|||
|
|||
#define BONITO_BONGENCFG_DEBUGMODE 0x00000001 |
|||
#define BONITO_BONGENCFG_SNOOPEN 0x00000002 |
|||
#define BONITO_BONGENCFG_CPUSELFRESET 0x00000004 |
|||
|
|||
#define BONITO_BONGENCFG_FORCE_IRQA 0x00000008 |
|||
#define BONITO_BONGENCFG_IRQA_ISOUT 0x00000010 |
|||
#define BONITO_BONGENCFG_IRQA_FROM_INT1 0x00000020 |
|||
#define BONITO_BONGENCFG_BYTESWAP 0x00000040 |
|||
|
|||
#define BONITO_BONGENCFG_PREFETCHEN 0x00000100 |
|||
#define BONITO_BONGENCFG_WBEHINDEN 0x00000200 |
|||
#define BONITO_BONGENCFG_CACHEALG 0x00000c00 |
|||
#define BONITO_BONGENCFG_CACHEALG_SHIFT 10 |
|||
#define BONITO_BONGENCFG_PCIQUEUE 0x00001000 |
|||
#define BONITO_BONGENCFG_CACHESTOP 0x00002000 |
|||
#define BONITO_BONGENCFG_MSTRBYTESWAP 0x00004000 |
|||
#define BONITO_BONGENCFG_BUSERREN 0x00008000 |
|||
#define BONITO_BONGENCFG_NORETRYTIMEOUT 0x00010000 |
|||
#define BONITO_BONGENCFG_SHORTCOPYTIMEOUT 0x00020000 |
|||
|
|||
/* 2. IO & IDE configuration */ |
|||
|
|||
#define BONITO_IODEVCFG BONITO(BONITO_REGBASE + 0x08) |
|||
|
|||
/* 3. IO & IDE configuration */ |
|||
|
|||
#define BONITO_SDCFG BONITO(BONITO_REGBASE + 0x0c) |
|||
|
|||
/* 4. PCI address map control */ |
|||
|
|||
#define BONITO_PCIMAP BONITO(BONITO_REGBASE + 0x10) |
|||
#define BONITO_PCIMEMBASECFG BONITO(BONITO_REGBASE + 0x14) |
|||
#define BONITO_PCIMAP_CFG BONITO(BONITO_REGBASE + 0x18) |
|||
|
|||
/* 5. ICU & GPIO regs */ |
|||
|
|||
/* GPIO Regs - r/w */ |
|||
|
|||
#define BONITO_GPIODATA_OFFSET 0x1c |
|||
#define BONITO_GPIODATA BONITO(BONITO_REGBASE + BONITO_GPIODATA_OFFSET) |
|||
#define BONITO_GPIOIE BONITO(BONITO_REGBASE + 0x20) |
|||
|
|||
/* ICU Configuration Regs - r/w */ |
|||
|
|||
#define BONITO_INTEDGE BONITO(BONITO_REGBASE + 0x24) |
|||
#define BONITO_INTSTEER BONITO(BONITO_REGBASE + 0x28) |
|||
#define BONITO_INTPOL BONITO(BONITO_REGBASE + 0x2c) |
|||
|
|||
/* ICU Enable Regs - IntEn & IntISR are r/o. */ |
|||
|
|||
#define BONITO_INTENSET BONITO(BONITO_REGBASE + 0x30) |
|||
#define BONITO_INTENCLR BONITO(BONITO_REGBASE + 0x34) |
|||
#define BONITO_INTEN BONITO(BONITO_REGBASE + 0x38) |
|||
#define BONITO_INTISR BONITO(BONITO_REGBASE + 0x3c) |
|||
|
|||
/* PCI mail boxes */ |
|||
|
|||
#define BONITO_PCIMAIL0_OFFSET 0x40 |
|||
#define BONITO_PCIMAIL1_OFFSET 0x44 |
|||
#define BONITO_PCIMAIL2_OFFSET 0x48 |
|||
#define BONITO_PCIMAIL3_OFFSET 0x4c |
|||
#define BONITO_PCIMAIL0 BONITO(BONITO_REGBASE + 0x40) |
|||
#define BONITO_PCIMAIL1 BONITO(BONITO_REGBASE + 0x44) |
|||
#define BONITO_PCIMAIL2 BONITO(BONITO_REGBASE + 0x48) |
|||
#define BONITO_PCIMAIL3 BONITO(BONITO_REGBASE + 0x4c) |
|||
|
|||
|
|||
/* 6. PCI cache */ |
|||
|
|||
#define BONITO_PCICACHECTRL BONITO(BONITO_REGBASE + 0x50) |
|||
#define BONITO_PCICACHETAG BONITO(BONITO_REGBASE + 0x54) |
|||
|
|||
#define BONITO_PCIBADADDR BONITO(BONITO_REGBASE + 0x58) |
|||
#define BONITO_PCIMSTAT BONITO(BONITO_REGBASE + 0x5c) |
|||
|
|||
|
|||
/*
|
|||
#define BONITO_PCIRDPOST BONITO(BONITO_REGBASE + 0x60) |
|||
#define BONITO_PCIDATA BONITO(BONITO_REGBASE + 0x64) |
|||
*/ |
|||
|
|||
/* 7. IDE DMA & Copier */ |
|||
|
|||
#define BONITO_CONFIGBASE 0x000 |
|||
#define BONITO_BONITOBASE 0x100 |
|||
#define BONITO_LDMABASE 0x200 |
|||
#define BONITO_COPBASE 0x300 |
|||
#define BONITO_REG_BLOCKMASK 0x300 |
|||
|
|||
#define BONITO_LDMACTRL BONITO(BONITO_LDMABASE + 0x0) |
|||
#define BONITO_LDMASTAT BONITO(BONITO_LDMABASE + 0x0) |
|||
#define BONITO_LDMAADDR BONITO(BONITO_LDMABASE + 0x4) |
|||
#define BONITO_LDMAGO BONITO(BONITO_LDMABASE + 0x8) |
|||
#define BONITO_LDMADATA BONITO(BONITO_LDMABASE + 0xc) |
|||
|
|||
#define BONITO_COPCTRL BONITO(BONITO_COPBASE + 0x0) |
|||
#define BONITO_COPSTAT BONITO(BONITO_COPBASE + 0x0) |
|||
#define BONITO_COPPADDR BONITO(BONITO_COPBASE + 0x4) |
|||
#define BONITO_COPDADDR BONITO(BONITO_COPBASE + 0x8) |
|||
#define BONITO_COPGO BONITO(BONITO_COPBASE + 0xc) |
|||
|
|||
|
|||
/* ###### Bit Definitions for individual Registers #### */ |
|||
|
|||
/* Gen DMA. */ |
|||
|
|||
#define BONITO_IDECOPDADDR_DMA_DADDR 0x0ffffffc |
|||
#define BONITO_IDECOPDADDR_DMA_DADDR_SHIFT 2 |
|||
#define BONITO_IDECOPPADDR_DMA_PADDR 0xfffffffc |
|||
#define BONITO_IDECOPPADDR_DMA_PADDR_SHIFT 2 |
|||
#define BONITO_IDECOPGO_DMA_SIZE 0x0000fffe |
|||
#define BONITO_IDECOPGO_DMA_SIZE_SHIFT 0 |
|||
#define BONITO_IDECOPGO_DMA_WRITE 0x00010000 |
|||
#define BONITO_IDECOPGO_DMAWCOUNT 0x000f0000 |
|||
#define BONITO_IDECOPGO_DMAWCOUNT_SHIFT 16 |
|||
|
|||
#define BONITO_IDECOPCTRL_DMA_STARTBIT 0x80000000 |
|||
#define BONITO_IDECOPCTRL_DMA_RSTBIT 0x40000000 |
|||
|
|||
/* DRAM - sdCfg */ |
|||
|
|||
#define BONITO_SDCFG_AROWBITS 0x00000003 |
|||
#define BONITO_SDCFG_AROWBITS_SHIFT 0 |
|||
#define BONITO_SDCFG_ACOLBITS 0x0000000c |
|||
#define BONITO_SDCFG_ACOLBITS_SHIFT 2 |
|||
#define BONITO_SDCFG_ABANKBIT 0x00000010 |
|||
#define BONITO_SDCFG_ASIDES 0x00000020 |
|||
#define BONITO_SDCFG_AABSENT 0x00000040 |
|||
#define BONITO_SDCFG_AWIDTH64 0x00000080 |
|||
|
|||
#define BONITO_SDCFG_BROWBITS 0x00000300 |
|||
#define BONITO_SDCFG_BROWBITS_SHIFT 8 |
|||
#define BONITO_SDCFG_BCOLBITS 0x00000c00 |
|||
#define BONITO_SDCFG_BCOLBITS_SHIFT 10 |
|||
#define BONITO_SDCFG_BBANKBIT 0x00001000 |
|||
#define BONITO_SDCFG_BSIDES 0x00002000 |
|||
#define BONITO_SDCFG_BABSENT 0x00004000 |
|||
#define BONITO_SDCFG_BWIDTH64 0x00008000 |
|||
|
|||
#define BONITO_SDCFG_EXTRDDATA 0x00010000 |
|||
#define BONITO_SDCFG_EXTRASCAS 0x00020000 |
|||
#define BONITO_SDCFG_EXTPRECH 0x00040000 |
|||
#define BONITO_SDCFG_EXTRASWIDTH 0x00180000 |
|||
#define BONITO_SDCFG_EXTRASWIDTH_SHIFT 19 |
|||
#define BONITO_SDCFG_DRAMRESET 0x00200000 |
|||
#define BONITO_SDCFG_DRAMEXTREGS 0x00400000 |
|||
#define BONITO_SDCFG_DRAMPARITY 0x00800000 |
|||
|
|||
/* PCI Cache - pciCacheCtrl */ |
|||
|
|||
#define BONITO_PCICACHECTRL_CACHECMD 0x00000007 |
|||
#define BONITO_PCICACHECTRL_CACHECMD_SHIFT 0 |
|||
#define BONITO_PCICACHECTRL_CACHECMDLINE 0x00000018 |
|||
#define BONITO_PCICACHECTRL_CACHECMDLINE_SHIFT 3 |
|||
#define BONITO_PCICACHECTRL_CMDEXEC 0x00000020 |
|||
|
|||
#define BONITO_IODEVCFG_BUFFBIT_CS0 0x00000001 |
|||
#define BONITO_IODEVCFG_SPEEDBIT_CS0 0x00000002 |
|||
#define BONITO_IODEVCFG_MOREABITS_CS0 0x00000004 |
|||
|
|||
#define BONITO_IODEVCFG_BUFFBIT_CS1 0x00000008 |
|||
#define BONITO_IODEVCFG_SPEEDBIT_CS1 0x00000010 |
|||
#define BONITO_IODEVCFG_MOREABITS_CS1 0x00000020 |
|||
|
|||
#define BONITO_IODEVCFG_BUFFBIT_CS2 0x00000040 |
|||
#define BONITO_IODEVCFG_SPEEDBIT_CS2 0x00000080 |
|||
#define BONITO_IODEVCFG_MOREABITS_CS2 0x00000100 |
|||
|
|||
#define BONITO_IODEVCFG_BUFFBIT_CS3 0x00000200 |
|||
#define BONITO_IODEVCFG_SPEEDBIT_CS3 0x00000400 |
|||
#define BONITO_IODEVCFG_MOREABITS_CS3 0x00000800 |
|||
|
|||
#define BONITO_IODEVCFG_BUFFBIT_IDE 0x00001000 |
|||
#define BONITO_IODEVCFG_SPEEDBIT_IDE 0x00002000 |
|||
#define BONITO_IODEVCFG_WORDSWAPBIT_IDE 0x00004000 |
|||
#define BONITO_IODEVCFG_MODEBIT_IDE 0x00008000 |
|||
#define BONITO_IODEVCFG_DMAON_IDE 0x001f0000 |
|||
#define BONITO_IODEVCFG_DMAON_IDE_SHIFT 16 |
|||
#define BONITO_IODEVCFG_DMAOFF_IDE 0x01e00000 |
|||
#define BONITO_IODEVCFG_DMAOFF_IDE_SHIFT 21 |
|||
#define BONITO_IODEVCFG_EPROMSPLIT 0x02000000 |
|||
|
|||
/* gpio */ |
|||
#define BONITO_GPIO_GPIOW 0x000003ff |
|||
#define BONITO_GPIO_GPIOW_SHIFT 0 |
|||
#define BONITO_GPIO_GPIOR 0x01ff0000 |
|||
#define BONITO_GPIO_GPIOR_SHIFT 16 |
|||
#define BONITO_GPIO_GPINR 0xfe000000 |
|||
#define BONITO_GPIO_GPINR_SHIFT 25 |
|||
#define BONITO_GPIO_IOW(N) (1<<(BONITO_GPIO_GPIOW_SHIFT+(N))) |
|||
#define BONITO_GPIO_IOR(N) (1<<(BONITO_GPIO_GPIOR_SHIFT+(N))) |
|||
#define BONITO_GPIO_INR(N) (1<<(BONITO_GPIO_GPINR_SHIFT+(N))) |
|||
|
|||
/* ICU */ |
|||
#define BONITO_ICU_MBOXES 0x0000000f |
|||
#define BONITO_ICU_MBOXES_SHIFT 0 |
|||
#define BONITO_ICU_DMARDY 0x00000010 |
|||
#define BONITO_ICU_DMAEMPTY 0x00000020 |
|||
#define BONITO_ICU_COPYRDY 0x00000040 |
|||
#define BONITO_ICU_COPYEMPTY 0x00000080 |
|||
#define BONITO_ICU_COPYERR 0x00000100 |
|||
#define BONITO_ICU_PCIIRQ 0x00000200 |
|||
#define BONITO_ICU_MASTERERR 0x00000400 |
|||
#define BONITO_ICU_SYSTEMERR 0x00000800 |
|||
#define BONITO_ICU_DRAMPERR 0x00001000 |
|||
#define BONITO_ICU_RETRYERR 0x00002000 |
|||
#define BONITO_ICU_GPIOS 0x01ff0000 |
|||
#define BONITO_ICU_GPIOS_SHIFT 16 |
|||
#define BONITO_ICU_GPINS 0x7e000000 |
|||
#define BONITO_ICU_GPINS_SHIFT 25 |
|||
#define BONITO_ICU_MBOX(N) (1<<(BONITO_ICU_MBOXES_SHIFT+(N))) |
|||
#define BONITO_ICU_GPIO(N) (1<<(BONITO_ICU_GPIOS_SHIFT+(N))) |
|||
#define BONITO_ICU_GPIN(N) (1<<(BONITO_ICU_GPINS_SHIFT+(N))) |
|||
|
|||
/* pcimap */ |
|||
|
|||
#define BONITO_PCIMAP_PCIMAP_LO0 0x0000003f |
|||
#define BONITO_PCIMAP_PCIMAP_LO0_SHIFT 0 |
|||
#define BONITO_PCIMAP_PCIMAP_LO1 0x00000fc0 |
|||
#define BONITO_PCIMAP_PCIMAP_LO1_SHIFT 6 |
|||
#define BONITO_PCIMAP_PCIMAP_LO2 0x0003f000 |
|||
#define BONITO_PCIMAP_PCIMAP_LO2_SHIFT 12 |
|||
#define BONITO_PCIMAP_PCIMAP_2 0x00040000 |
|||
#define BONITO_PCIMAP_WIN(WIN,ADDR) ((((ADDR)>>26) & BONITO_PCIMAP_PCIMAP_LO0) << ((WIN)*6)) |
|||
|
|||
#define BONITO_PCIMAP_WINSIZE (1<<26) |
|||
#define BONITO_PCIMAP_WINOFFSET(ADDR) ((ADDR) & (BONITO_PCIMAP_WINSIZE - 1)) |
|||
#define BONITO_PCIMAP_WINBASE(ADDR) ((ADDR) << 26) |
|||
|
|||
/* pcimembaseCfg */ |
|||
|
|||
#define BONITO_PCIMEMBASECFG_MASK 0xf0000000 |
|||
#define BONITO_PCIMEMBASECFG_MEMBASE0_MASK 0x0000001f |
|||
#define BONITO_PCIMEMBASECFG_MEMBASE0_MASK_SHIFT 0 |
|||
#define BONITO_PCIMEMBASECFG_MEMBASE0_TRANS 0x000003e0 |
|||
#define BONITO_PCIMEMBASECFG_MEMBASE0_TRANS_SHIFT 5 |
|||
#define BONITO_PCIMEMBASECFG_MEMBASE0_CACHED 0x00000400 |
|||
#define BONITO_PCIMEMBASECFG_MEMBASE0_IO 0x00000800 |
|||
|
|||
#define BONITO_PCIMEMBASECFG_MEMBASE1_MASK 0x0001f000 |
|||
#define BONITO_PCIMEMBASECFG_MEMBASE1_MASK_SHIFT 12 |
|||
#define BONITO_PCIMEMBASECFG_MEMBASE1_TRANS 0x003e0000 |
|||
#define BONITO_PCIMEMBASECFG_MEMBASE1_TRANS_SHIFT 17 |
|||
#define BONITO_PCIMEMBASECFG_MEMBASE1_CACHED 0x00400000 |
|||
#define BONITO_PCIMEMBASECFG_MEMBASE1_IO 0x00800000 |
|||
|
|||
#define BONITO_PCIMEMBASECFG_ASHIFT 23 |
|||
#define BONITO_PCIMEMBASECFG_AMASK 0x007fffff |
|||
#define BONITO_PCIMEMBASECFGSIZE(WIN,SIZE) (((~((SIZE)-1))>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) |
|||
#define BONITO_PCIMEMBASECFGBASE(WIN,BASE) (((BASE)>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS) |
|||
|
|||
#define BONITO_PCIMEMBASECFG_SIZE(WIN,CFG) (((((~(CFG)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK)) << (BONITO_PCIMEMBASECFG_ASHIFT - BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) | BONITO_PCIMEMBASECFG_AMASK) |
|||
|
|||
|
|||
#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN,CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT) |
|||
#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN,CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT) |
|||
#define BONITO_PCIMEMBASECFG_ADDRTRANS(WIN,CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT) |
|||
|
|||
#define BONITO_PCITOPHYS(WIN,ADDR,CFG) ( \ |
|||
(((ADDR) & (~(BONITO_PCIMEMBASECFG_MASK))) & (~(BONITO_PCIMEMBASECFG_ADDRMASK(WIN,CFG)))) | \ |
|||
(BONITO_PCIMEMBASECFG_ADDRTRANS(WIN,CFG)) \ |
|||
) |
|||
|
|||
/* PCICmd */ |
|||
|
|||
#define BONITO_PCICMD_MEMEN 0x00000002 |
|||
#define BONITO_PCICMD_MSTREN 0x00000004 |
|||
|
|||
/* DDR - sdCfg */ |
|||
#define BONITO_SDCFG_TRC_SHIFT 0 |
|||
#define BONITO_SDCFG_TRP_SHIFT 2 |
|||
#define BONITO_SDCFG_TWR_SHIFT 3 |
|||
#define BONITO_SDCFG_TCAS_SHIFT 4 |
|||
#define BONITO_SDCFG_TRAS_SHIFT 6 |
|||
#define BONITO_SDCFG_TRFC_SHIFT 7 |
|||
#define BONITO_SDCFG_TRCD_SHIFT 9 |
|||
#define BONITO_SDCFG_TREF_SHIFT 10 |
|||
#define BONITO_SDCFG_DDRTYPE_SHIFT 22 |
|||
#define BONITO_SDCFG_ISSEQ_SHIFT 26 |
|||
#define BONITO_SDCFG_DIMM_MOD_NUM_SHIFT 27 |
|||
|
|||
#define VTSB_BUS 0 |
|||
#ifdef PCI_IDSEL_VIA686B |
|||
#define VTSB_DEV PCI_IDSEL_VIA686B |
|||
#else |
|||
#define VTSB_DEV 17 |
|||
#endif |
|||
#define VTSB_ISA_FUNC 0 |
|||
#define VTSB_IDE_FUNC 1 |
|||
#endif /* _BONITO_H_ */ |
|||
@ -0,0 +1,571 @@ |
|||
/*
|
|||
* cs5536.h |
|||
* |
|||
* The include file of cs5536 sourthbridge define which is used in the pmon only. |
|||
* you can modify it or change it, please set the modify time and steps. |
|||
* |
|||
* Author : jlliu <liujl@lemote.com> |
|||
* Data : 07-6-27 |
|||
*/ |
|||
|
|||
#ifndef _CS5536_H |
|||
#define _CS5536_H |
|||
|
|||
/*************************************************************************/ |
|||
|
|||
/*
|
|||
* basic define |
|||
*/ |
|||
#define PCI_IO_BASE 0x1fd00000 //( < 0x1fe00000)
|
|||
#define PCI_IO_BASE_VA 0xbfd00000 |
|||
#define PCI_MEM_BASE 0x10000000 //( < 0x1c000000 )
|
|||
#define PCI_MEM_BASE_VA 0xb0000000 |
|||
|
|||
/*
|
|||
* MSR module base |
|||
*/ |
|||
#define GET_MSR_ADDR(x) (((x<<9)&0xff100000)|(x&0x3fff)) |
|||
#define CS5536_SB_MSR_BASE (0x00000000) |
|||
#define CS5536_GLIU_MSR_BASE (0x10000000) |
|||
#define CS5536_ILLEGAL_MSR_BASE (0x20000000) |
|||
#define CS5536_USB_MSR_BASE (0x40000000) |
|||
#define CS5536_IDE_MSR_BASE (0x60000000) |
|||
#define CS5536_DIVIL_MSR_BASE (0x80000000) |
|||
#define CS5536_ACC_MSR_BASE (0xa0000000) |
|||
#define CS5536_UNUSED_MSR_BASE (0xc0000000) |
|||
#define CS5536_GLCP_MSR_BASE (0xe0000000) |
|||
|
|||
#define SB_MSR_REG(offset) (CS5536_SB_MSR_BASE | offset) |
|||
#define GLIU_MSR_REG(offset) (CS5536_GLIU_MSR_BASE | offset) |
|||
#define ILLEGAL_MSR_REG(offset) (CS5536_ILLEGAL_MSR_BASE| offset) |
|||
#define USB_MSR_REG(offset) (CS5536_USB_MSR_BASE | offset) |
|||
#define IDE_MSR_REG(offset) (CS5536_IDE_MSR_BASE | offset) |
|||
#define DIVIL_MSR_REG(offset) (CS5536_DIVIL_MSR_BASE | offset) |
|||
#define ACC_MSR_REG(offset) (CS5536_ACC_MSR_BASE | offset) |
|||
#define UNUSED_MSR_REG(offset) (CS5536_UNUSED_MSR_BASE | offset) |
|||
#define GLCP_MSR_REG(offset) (CS5536_GLCP_MSR_BASE | offset) |
|||
/*
|
|||
* PCI MSR ACCESS |
|||
*/ |
|||
#define PCI_MSR_CTRL 0xF0 |
|||
#define PCI_MSR_ADDR 0xF4 |
|||
#define PCI_MSR_DATA_LO 0xF8 |
|||
#define PCI_MSR_DATA_HI 0xFC |
|||
|
|||
/******************************* MSR *****************************************/ |
|||
|
|||
/*
|
|||
* GLIU STANDARD MSR |
|||
*/ |
|||
#define GLIU_CAP 0x00 |
|||
#define GLIU_CONFIG 0x01 |
|||
#define GLIU_SMI 0x02 |
|||
#define GLIU_ERROR 0x03 |
|||
#define GLIU_PM 0x04 |
|||
#define GLIU_DIAG 0x05 |
|||
|
|||
/*
|
|||
* GLIU SPEC. MSR |
|||
*/ |
|||
#define GLIU_P2D_BM0 0x20 |
|||
#define GLIU_P2D_BM1 0x21 |
|||
#define GLIU_P2D_BM2 0x22 |
|||
#define GLIU_P2D_BMK0 0x23 |
|||
#define GLIU_P2D_BMK1 0x24 |
|||
#define GLIU_P2D_BM3 0x25 |
|||
#define GLIU_P2D_BM4 0x26 |
|||
#define GLIU_COH 0x80 |
|||
#define GLIU_PAE 0x81 |
|||
#define GLIU_ARB 0x82 |
|||
#define GLIU_ASMI 0x83 |
|||
#define GLIU_AERR 0x84 |
|||
#define GLIU_DEBUG 0x85 |
|||
#define GLIU_PHY_CAP 0x86 |
|||
#define GLIU_NOUT_RESP 0x87 |
|||
#define GLIU_NOUT_WDATA 0x88 |
|||
#define GLIU_WHOAMI 0x8B |
|||
#define GLIU_SLV_DIS 0x8C |
|||
#define GLIU_IOD_BM0 0xE0 |
|||
#define GLIU_IOD_BM1 0xE1 |
|||
#define GLIU_IOD_BM2 0xE2 |
|||
#define GLIU_IOD_BM3 0xE3 |
|||
#define GLIU_IOD_BM4 0xE4 |
|||
#define GLIU_IOD_BM5 0xE5 |
|||
#define GLIU_IOD_BM6 0xE6 |
|||
#define GLIU_IOD_BM7 0xE7 |
|||
#define GLIU_IOD_BM8 0xE8 |
|||
#define GLIU_IOD_BM9 0xE9 |
|||
#define GLIU_IOD_SC0 0xEA |
|||
#define GLIU_IOD_SC1 0xEB |
|||
#define GLIU_IOD_SC2 0xEC |
|||
#define GLIU_IOD_SC3 0xED |
|||
#define GLIU_IOD_SC4 0xEE |
|||
#define GLIU_IOD_SC5 0xEF |
|||
#define GLIU_IOD_SC6 0xF0 |
|||
#define GLIU_IOD_SC7 0xF1 |
|||
|
|||
/*
|
|||
* SB STANDARD |
|||
*/ |
|||
#define SB_CAP 0x00 |
|||
#define SB_CONFIG 0x01 |
|||
#define SB_SMI 0x02 |
|||
#define SB_ERROR 0x03 |
|||
#define SB_MAR_ERR_EN 0x00000001 |
|||
#define SB_TAR_ERR_EN 0x00000002 |
|||
#define SB_RSVD_BIT1 0x00000004 |
|||
#define SB_EXCEP_ERR_EN 0x00000008 |
|||
#define SB_SYSE_ERR_EN 0x00000010 |
|||
#define SB_PARE_ERR_EN 0x00000020 |
|||
#define SB_TAS_ERR_EN 0x00000040 |
|||
#define SB_MAR_ERR_FLAG 0x00010000 |
|||
#define SB_TAR_ERR_FLAG 0x00020000 |
|||
#define SB_RSVD_BIT2 0x00040000 |
|||
#define SB_EXCEP_ERR_FLAG 0x00080000 |
|||
#define SB_SYSE_ERR_FLAG 0x00100000 |
|||
#define SB_PARE_ERR_FLAG 0x00200000 |
|||
#define SB_TAS_ERR_FLAG 0x00400000 |
|||
#define SB_PM 0x04 |
|||
#define SB_DIAG 0x05 |
|||
|
|||
/*
|
|||
* SB SPEC. |
|||
*/ |
|||
#define SB_CTRL 0x10 |
|||
#define SB_R0 0x20 |
|||
#define SB_R1 0x21 |
|||
#define SB_R2 0x22 |
|||
#define SB_R3 0x23 |
|||
#define SB_R4 0x24 |
|||
#define SB_R5 0x25 |
|||
#define SB_R6 0x26 |
|||
#define SB_R7 0x27 |
|||
#define SB_R8 0x28 |
|||
#define SB_R9 0x29 |
|||
#define SB_R10 0x2A |
|||
#define SB_R11 0x2B |
|||
#define SB_R12 0x2C |
|||
#define SB_R13 0x2D |
|||
#define SB_R14 0x2E |
|||
#define SB_R15 0x2F |
|||
|
|||
/*
|
|||
* GLCP STANDARD |
|||
*/ |
|||
#define GLCP_CAP 0x00 |
|||
#define GLCP_CONFIG 0x01 |
|||
#define GLCP_SMI 0x02 |
|||
#define GLCP_ERROR 0x03 |
|||
#define GLCP_PM 0x04 |
|||
#define GLCP_DIAG 0x05 |
|||
|
|||
/*
|
|||
* GLCP SPEC. |
|||
*/ |
|||
#define GLCP_CLK_DIS_DELAY 0x08 |
|||
#define GLCP_PM_CLK_DISABLE 0x09 |
|||
#define GLCP_GLB_PM 0x0B |
|||
#define GLCP_DBG_OUT 0x0C |
|||
#define GLCP_RSVD1 0x0D |
|||
#define GLCP_SOFT_COM 0x0E |
|||
#define SOFT_BAR_SMB_FLAG 0x00000001 |
|||
#define SOFT_BAR_GPIO_FLAG 0x00000002 |
|||
#define SOFT_BAR_MFGPT_FLAG 0x00000004 |
|||
#define SOFT_BAR_IRQ_FLAG 0x00000008 |
|||
#define SOFT_BAR_PMS_FLAG 0x00000010 |
|||
#define SOFT_BAR_ACPI_FLAG 0x00000020 |
|||
#define SOFT_BAR_FLSH0_FLAG 0x00000040 |
|||
#define SOFT_BAR_FLSH1_FLAG 0x00000080 |
|||
#define SOFT_BAR_FLSH2_FLAG 0x00000100 |
|||
#define SOFT_BAR_FLSH3_FLAG 0x00000200 |
|||
#define SOFT_BAR_IDE_FLAG 0x00000400 |
|||
#define SOFT_BAR_ACC_FLAG 0x00000800 |
|||
#define SOFT_BAR_OHCI_FLAG 0x00001000 |
|||
#define SOFT_BAR_EHCI_FLAG 0x00002000 |
|||
#define SOFT_BAR_UDC_FLAG 0x00004000 |
|||
#define SOFT_BAR_OTG_FLAG 0x00008000 |
|||
#define GLCP_RSVD2 0x0F |
|||
#define GLCP_CLK_OFF 0x10 |
|||
#define GLCP_CLK_ACTIVE 0x11 |
|||
#define GLCP_CLK_DISABLE 0x12 |
|||
#define GLCP_CLK4ACK 0x13 |
|||
#define GLCP_SYS_RST 0x14 |
|||
#define GLCP_RSVD3 0x15 |
|||
#define GLCP_DBG_CLK_CTRL 0x16 |
|||
#define GLCP_CHIP_REV_ID 0x17 |
|||
|
|||
/*
|
|||
* DIVIL STANDARD |
|||
*/ |
|||
#define DIVIL_CAP 0x00 |
|||
#define DIVIL_CONFIG 0x01 |
|||
#define DIVIL_SMI 0x02 |
|||
#define DIVIL_ERROR 0x03 |
|||
#define DIVIL_PM 0x04 |
|||
#define DIVIL_DIAG 0x05 |
|||
|
|||
/*
|
|||
* DIVIL SPEC. |
|||
*/ |
|||
#define DIVIL_LBAR_IRQ 0x08 |
|||
#define DIVIL_LBAR_KEL 0x09 |
|||
#define DIVIL_LBAR_SMB 0x0B |
|||
#define DIVIL_LBAR_GPIO 0x0C |
|||
#define DIVIL_LBAR_MFGPT 0x0D |
|||
#define DIVIL_LBAR_ACPI 0x0E |
|||
#define DIVIL_LBAR_PMS 0x0F |
|||
#define DIVIL_LBAR_FLSH0 0x10 |
|||
#define DIVIL_LBAR_FLSH1 0x11 |
|||
#define DIVIL_LBAR_FLSH2 0x12 |
|||
#define DIVIL_LBAR_FLSH3 0x13 |
|||
#define DIVIL_LEG_IO 0x14 |
|||
#define DIVIL_BALL_OPTS 0x15 |
|||
#define DIVIL_SOFT_IRQ 0x16 |
|||
#define DIVIL_SOFT_RESET 0x17 |
|||
// NOR FLASH
|
|||
#define NORF_CTRL 0x18 |
|||
#define NORF_T01 0x19 |
|||
#define NORF_T23 0x1A |
|||
// NAND FLASH
|
|||
#define NANDF_DATA 0x1B |
|||
#define NANDF_CTRL 0x1C |
|||
#define NANDF_RSVD 0x1D |
|||
// KEL Keyboard Emulation Logic
|
|||
#define KEL_CTRL 0x1F |
|||
// PIC
|
|||
#define PIC_YZSEL_LOW 0x20 |
|||
#define PIC_YSEL_HIGH 0x21 |
|||
#define PIC_ZSEL_LOW 0x22 |
|||
#define PIC_ZSEL_HIGH 0x23 |
|||
#define PIC_IRQM_PRIM 0x24 |
|||
#define PIC_IRQM_LPC 0x25 |
|||
#define PIC_XIRR_STS_LOW 0x26 |
|||
#define PIC_XIRR_STS_HIGH 0x27 |
|||
#define PCI_SHDW 0x34 |
|||
// MFGPT
|
|||
#define MFGPT_IRQ 0x28 |
|||
#define MFGPT_NR 0x29 |
|||
#define MFGPT_RSVD 0x2A |
|||
#define MFGPT_SETUP 0x2B |
|||
// FLOPPY
|
|||
#define FLPY_3F2_SHDW 0x30 |
|||
#define FLPY_3F7_SHDW 0x31 |
|||
#define FLPY_372_SHDW 0x32 |
|||
#define FLPY_377_SHDW 0x33 |
|||
// PIT
|
|||
#define PIT_SHDW 0x36 |
|||
#define PIT_CNTRL 0x37 |
|||
// UART
|
|||
#define UART1_MOD 0x38 |
|||
#define UART1_DONG 0x39 |
|||
#define UART1_CONF 0x3A |
|||
#define UART1_RSVD 0x3B |
|||
#define UART2_MOD 0x3C |
|||
#define UART2_DONG 0x3D |
|||
#define UART2_CONF 0x3E |
|||
#define UART2_RSVD 0x3F |
|||
// DMA
|
|||
#define DIVIL_AC_DMA 0x1E |
|||
#define DMA_MAP 0x40 |
|||
#define DMA_SHDW_CH0 0x41 |
|||
#define DMA_SHDW_CH1 0x42 |
|||
#define DMA_SHDW_CH2 0x43 |
|||
#define DMA_SHDW_CH3 0x44 |
|||
#define DMA_SHDW_CH4 0x45 |
|||
#define DMA_SHDW_CH5 0x46 |
|||
#define DMA_SHDW_CH6 0x47 |
|||
#define DMA_SHDW_CH7 0x48 |
|||
#define DMA_MSK_SHDW 0x49 |
|||
// LPC
|
|||
#define LPC_EADDR 0x4C |
|||
#define LPC_ESTAT 0x4D |
|||
#define LPC_SIRQ 0x4E |
|||
#define LPC_RSVD 0x4F |
|||
// PMC
|
|||
#define PMC_LTMR 0x50 |
|||
#define PMC_RSVD 0x51 |
|||
// RTC
|
|||
#define RTC_RAM_LOCK 0x54 |
|||
#define RTC_DOMA_OFFSET 0x55 |
|||
#define RTC_MONA_OFFSET 0x56 |
|||
#define RTC_CEN_OFFSET 0x57 |
|||
|
|||
/*
|
|||
* IDE STANDARD |
|||
*/ |
|||
#define IDE_CAP 0x00 |
|||
#define IDE_CONFIG 0x01 |
|||
#define IDE_SMI 0x02 |
|||
#define IDE_ERROR 0x03 |
|||
#define IDE_PM 0x04 |
|||
#define IDE_DIAG 0x05 |
|||
|
|||
/*
|
|||
* ACC STANDARD |
|||
*/ |
|||
#define ACC_CAP 0x00 |
|||
#define ACC_CONFIG 0x01 |
|||
#define ACC_SMI 0x02 |
|||
#define ACC_ERROR 0x03 |
|||
#define ACC_PM 0x04 |
|||
#define ACC_DIAG 0x05 |
|||
|
|||
/*
|
|||
* IDE SPEC. |
|||
*/ |
|||
#define IDE_IO_BAR 0x08 |
|||
#define IDE_CFG 0x10 |
|||
#define IDE_DTC 0x12 |
|||
#define IDE_CAST 0x13 |
|||
#define IDE_ETC 0x14 |
|||
#define IDE_INTERNAL_PM 0x15 |
|||
|
|||
/*
|
|||
* USB STANDARD |
|||
*/ |
|||
#define USB_CAP 0x00 |
|||
#define USB_CONFIG 0x01 |
|||
#define USB_SMI 0x02 |
|||
#define USB_ERROR 0x03 |
|||
#define USB_PM 0x04 |
|||
#define USB_DIAG 0x05 |
|||
|
|||
/*
|
|||
* USB SPEC. |
|||
*/ |
|||
#define USB_OHCI 0x08 |
|||
#define USB_EHCI 0x09 |
|||
#define USB_UDC 0x0A |
|||
#define USB_OTG 0x0B |
|||
|
|||
/********************************** NATIVE ************************************/ |
|||
|
|||
#define CS5536_IDE_RANGE 0xfffffff0 |
|||
#define CS5536_IDE_LENGTH 0x10 |
|||
|
|||
/*
|
|||
* IDE NATIVE : I/O SPACE |
|||
* REG : 8BITS WIDTH |
|||
* BASE : DETERMINED BY MSR |
|||
*/ |
|||
#define IDE_BM_CMD 0x00 |
|||
#define IDE_BM_STS 0x02 |
|||
#define IDE_BM_PRD 0x04 |
|||
|
|||
/*
|
|||
* ACC |
|||
*/ |
|||
#define CS5536_ACC_RANGE 0xffffff80 |
|||
#define CS5536_ACC_LENGTH 0x80 |
|||
|
|||
/*
|
|||
* USB NATIVE : MEM SPACE |
|||
* REG : 32BITS WIDTH |
|||
*/ |
|||
#define CS5536_OHCI_RANGE 0xfffff000 |
|||
#define CS5536_OHCI_LENGTH 0x1000 |
|||
|
|||
#define CS5536_EHCI_RANGE 0xfffff000 |
|||
#define CS5536_EHCI_LENGTH 0x1000 |
|||
|
|||
#define CS5536_UDC_RANGE 0xffffe000 |
|||
#define CS5536_UDC_LENGTH 0x2000 |
|||
|
|||
#define CS5536_OTG_RANGE 0xfffff000 |
|||
#define CS5536_OTG_LENGTH 0x1000 |
|||
|
|||
// OHCI NATIVE
|
|||
#define OHCI_REVISION 0x00 |
|||
#define OHCI_CONTROL 0x04 |
|||
#define OHCI_COMMAND_STATUS 0x08 |
|||
#define OHCI_INT_STATUS 0x0C |
|||
#define OHCI_INT_ENABLE 0x10 |
|||
#define OHCI_INT_DISABLE 0x14 |
|||
#define OHCI_HCCA 0x18 |
|||
#define OHCI_PERI_CUR_ED 0x1C |
|||
#define OHCI_CTRL_HEAD_ED 0x20 |
|||
#define OHCI_CTRL_CUR_ED 0x24 |
|||
#define OHCI_BULK_HEAD_ED 0x28 |
|||
#define OHCI_BULK_CUR_ED 0x2C |
|||
#define OHCI_DONE_HEAD 0x30 |
|||
#define OHCI_FM_INTERVAL 0x34 |
|||
#define OHCI_FM_REMAINING 0x38 |
|||
#define OHCI_FM_NUMBER 0x3C |
|||
#define OHCI_PERI_START 0x40 |
|||
#define OHCI_LS_THRESHOLD 0x44 |
|||
#define OHCI_RH_DESCRIPTORA 0x48 |
|||
#define OHCI_RH_DESCRIPTORB 0x4C |
|||
#define OHCI_RH_STATUS 0x50 |
|||
#define OHCI_RH_PORT_STATUS1 0x54 |
|||
#define OHCI_RH_PORT_STATUS2 0x58 |
|||
#define OHCI_RH_PORT_STATUS3 0x5C |
|||
#define OHCI_RH_PORT_STATUS4 0x60 |
|||
|
|||
/*
|
|||
* DIVIL NATIVE |
|||
*/ |
|||
#define CS5536_IRQ_RANGE 0xffffffe0 // USERD FOR PCI PROBE
|
|||
#define CS5536_IRQ_LENGTH 0x20 // THE REGS ACTUAL LENGTH
|
|||
|
|||
#define CS5536_SMB_RANGE 0xfffffff8 |
|||
#define CS5536_SMB_LENGTH 0x08 |
|||
|
|||
#define CS5536_GPIO_RANGE 0xffffff00 |
|||
#define CS5536_GPIO_LENGTH 0x100 |
|||
|
|||
#define CS5536_MFGPT_RANGE 0xffffffc0 |
|||
#define CS5536_MFGPT_LENGTH 0x40 |
|||
|
|||
#define CS5536_ACPI_RANGE 0xffffffe0 |
|||
#define CS5536_ACPI_LENGTH 0x20 |
|||
|
|||
#define CS5536_PMS_RANGE 0xffffff80 |
|||
#define CS5536_PMS_LENGTH 0x80 |
|||
|
|||
|
|||
// KEL : MEM SPACE; REG :32BITS WIDTH
|
|||
#define KEL_HCE_CTRL 0x100 |
|||
#define KEL_HCE_IN 0x104 |
|||
#define KEL_HCE_OUT 0x108 |
|||
#define KEL_HCE_STS 0x10C |
|||
#define KEL_PORTA 0x92 //8bits
|
|||
// PIC : I/O SPACE; REG : 8BITS
|
|||
#define PIC_ICW1_MASTER 0x20 |
|||
#define PIC_ICW1_SLAVE 0xA0 |
|||
#define PIC_ICW2_MASTER 0x21 |
|||
#define PIC_ICW2_SLAVE 0xA1 |
|||
#define PIC_ICW3_MASTER 0x21 |
|||
#define PIC_ICW3_SLAVE 0xA1 |
|||
#define PIC_ICW4_MASTER 0x21 |
|||
#define PIC_ICW4_SLAVE 0xA1 |
|||
#define PIC_OCW1_MASTER 0x21 |
|||
#define PIC_OCW1_SLAVE 0xA1 |
|||
#define PIC_OCW2_MASTER 0x20 |
|||
#define PIC_OCW2_SLAVE 0xA0 |
|||
#define PIC_OCW3_MASTER 0x20 |
|||
#define PIC_OCW3_SLAVE 0xA0 |
|||
#define PIC_IRR_MASTER 0x20 |
|||
#define PIC_IRR_SLAVE 0xA0 |
|||
#define PIC_ISR_MASTER 0x20 |
|||
#define PIC_ISR_SLAVE 0xA0 |
|||
#define PIC_INT_SEL1 0x4D0 |
|||
#define PIC_INT_SEL2 0x4D1 |
|||
// GPIO : I/O SPACE; REG : 32BITS
|
|||
#define GPIOL_OUT_VAL 0x00 |
|||
#define GPIOL_OUT_EN 0x04 |
|||
#define GPIOL_OUT_OD_EN 0x08 |
|||
#define GPIOL_OUT_INVRT_EN 0x0c |
|||
#define GPIOL_OUT_AUX1_SEL 0x10 |
|||
#define GPIOL_OUT_AUX2_SEL 0x14 |
|||
#define GPIOL_PU_EN 0x18 |
|||
#define GPIOL_PD_EN 0x1c |
|||
#define GPIOL_IN_EN 0x20 |
|||
#define GPIOL_IN_INVRT_EN 0x24 |
|||
#define GPIOL_IN_FLTR_EN 0x28 |
|||
#define GPIOL_IN_EVNTCNT_EN 0x2c |
|||
#define GPIOL_IN_READBACK 0x30 |
|||
#define GPIOL_IN_AUX1_SEL 0x34 |
|||
#define GPIOL_EVNT_EN 0x38 |
|||
#define GPIOL_LOCK_EN 0x3c |
|||
#define GPIOL_IN_POSEDGE_EN 0x40 |
|||
#define GPIOL_IN_NEGEDGE_EN 0x44 |
|||
#define GPIOL_IN_POSEDGE_STS 0x48 |
|||
#define GPIOL_IN_NEGEDGE_STS 0x4c |
|||
#define GPIOH_OUT_VAL 0x80 |
|||
#define GPIOH_OUT_EN 0x84 |
|||
#define GPIOH_OUT_OD_EN 0x88 |
|||
#define GPIOH_OUT_INVRT_EN 0x8c |
|||
#define GPIOH_OUT_AUX1_SEL 0x90 |
|||
#define GPIOH_OUT_AUX2_SEL 0x94 |
|||
#define GPIOH_PU_EN 0x98 |
|||
#define GPIOH_PD_EN 0x9c |
|||
#define GPIOH_IN_EN 0xA0 |
|||
#define GPIOH_IN_INVRT_EN 0xA4 |
|||
#define GPIOH_IN_FLTR_EN 0xA8 |
|||
#define GPIOH_IN_EVNTCNT_EN 0xAc |
|||
#define GPIOH_IN_READBACK 0xB0 |
|||
#define GPIOH_IN_AUX1_SEL 0xB4 |
|||
#define GPIOH_EVNT_EN 0xB8 |
|||
#define GPIOH_LOCK_EN 0xBc |
|||
#define GPIOH_IN_POSEDGE_EN 0xC0 |
|||
#define GPIOH_IN_NEGEDGE_EN 0xC4 |
|||
#define GPIOH_IN_POSEDGE_STS 0xC8 |
|||
#define GPIOH_IN_NEGEDGE_STS 0xCC |
|||
// SMB : I/O SPACE, REG : 8BITS WIDTH
|
|||
#define SMB_SDA 0x00 |
|||
#define SMB_STS 0x01 |
|||
#define SMB_STS_SLVSTP (1 << 7) |
|||
#define SMB_STS_SDAST (1 << 6) |
|||
#define SMB_STS_BER (1 << 5) |
|||
#define SMB_STS_NEGACK (1 << 4) |
|||
#define SMB_STS_STASTR (1 << 3) |
|||
#define SMB_STS_NMATCH (1 << 2) |
|||
#define SMB_STS_MASTER (1 << 1) |
|||
#define SMB_STS_XMIT (1 << 0) |
|||
#define SMB_CTRL_STS 0x02 |
|||
#define SMB_CSTS_TGSTL (1 << 5) |
|||
#define SMB_CSTS_TSDA (1 << 4) |
|||
#define SMB_CSTS_GCMTCH (1 << 3) |
|||
#define SMB_CSTS_MATCH (1 << 2) |
|||
#define SMB_CSTS_BB (1 << 1) |
|||
#define SMB_CSTS_BUSY (1 << 0) |
|||
#define SMB_CTRL1 0x03 |
|||
#define SMB_CTRL1_STASTRE (1 << 7) |
|||
#define SMB_CTRL1_NMINTE (1 << 6) |
|||
#define SMB_CTRL1_GCMEN (1 << 5) |
|||
#define SMB_CTRL1_ACK (1 << 4) |
|||
#define SMB_CTRL1_RSVD (1 << 3) |
|||
#define SMB_CTRL1_INTEN (1 << 2) |
|||
#define SMB_CTRL1_STOP (1 << 1) |
|||
#define SMB_CTRL1_START (1 << 0) |
|||
#define SMB_ADDR 0x04 |
|||
#define SMB_ADDR_SAEN (1 << 7) |
|||
#define SMB_CTRL2 0x05 |
|||
#define SMB_ENABLE (1 << 0) |
|||
#define SMB_CTRL3 0x06 |
|||
|
|||
/*********************************** LEGACY I/O *******************************/ |
|||
|
|||
/*
|
|||
* LEGACY I/O SPACE BASE |
|||
*/ |
|||
#define CS5536_LEGACY_BASE_ADDR (PCI_IO_BASE_VA | 0x0000) |
|||
|
|||
/*
|
|||
* IDE LEGACY REG : legacy IO address is 0x170~0x177 and 0x376 (0x1f0~0x1f7 and 0x3f6) |
|||
* all registers are 16bits except the IDE_LEGACY_DATA reg |
|||
* some registers are read only and the |
|||
*/ |
|||
#define PRI_IDE_LEGACY_REG(offset) (CS5536_LEGACY_BASE_ADDR | 0x1f0 | offset) |
|||
#define SEC_IDE_LEGACY_REG(offset) (CS5536_LEGACY_BASE_ADDR | 0x170 | offset) |
|||
|
|||
#define IDE_LEGACY_DATA 0x00 // RW
|
|||
#define IDE_LEGACY_ERROR 0x01 // RO
|
|||
#define IDE_LEGACY_FEATURE 0x01 // WO
|
|||
#define IDE_LEGACY_SECTOR_COUNT 0x02 // RW
|
|||
#define IDE_LEGACY_SECTOR_NUM 0x03 // RW
|
|||
#define IDE_LEGACY_CYL_LO 0x04 // RW
|
|||
#define IDE_LEGACY_CYL_HI 0x05 // RW
|
|||
#define IDE_LEGACY_HEAD 0x06 // RW
|
|||
#define IDE_LEGACY_HEAD_DRV (1 << 4) |
|||
#define IDE_LEGACY_HEAD_LBA (1 << 6) |
|||
#define IDE_LEGACY_HEAD_IBM (1 << 7 | 1 << 5) |
|||
#define IDE_LEGACY_STATUS 0x07 // RO
|
|||
#define IDE_LEGACY_STATUS_ERR (1 << 0) |
|||
#define IDE_LEGACY_STATUS_IDX (1 << 1) |
|||
#define IDE_LEGACY_STATUS_CORR (1 << 2) |
|||
#define IDE_LEGACY_STATUS_DRQ (1 << 3) |
|||
#define IDE_LEGACY_STATUS_DSC (1 << 4) |
|||
#define IDE_LEGACY_STATUS_DWF (1 << 5) |
|||
#define IDE_LEGACY_STATUS_DRDY (1 << 6) |
|||
#define IDE_LEGACY_STATUS_BUSY (1 << 7) |
|||
#define IDE_LEGACY_COMMAND 0x07 // WO
|
|||
#define IDE_LEGACY_ASTATUS 0x206 // RO
|
|||
#define IDE_LEGACY_CTRL 0x206 // WO
|
|||
#define IDE_LEGACY_CTRL_IDS 0x02 |
|||
#define IDE_LEGACY_CTRL_RST 0x04 |
|||
#define IDE_LEGACY_CTRL_4BIT 0x08 |
|||
|
|||
/**********************************************************************************/ |
|||
|
|||
#endif /* _CS5536_H */ |
|||
@ -0,0 +1,138 @@ |
|||
/*
|
|||
* cs5536_vsm.h |
|||
* the definition file of cs5536 Virtual Support Module(VSM). |
|||
* pci configuration space can be accessed through the VSM, so |
|||
* there is no need the MSR read/write now, except the spec. MSR |
|||
* registers which are not implemented yet. |
|||
* |
|||
* Author : jlliu <liujl@lemote.com> |
|||
* Date : 07-07-04 |
|||
* |
|||
*/ |
|||
|
|||
#ifndef _CS5536_PCI_H |
|||
#define _CS5536_PCI_H |
|||
|
|||
/**********************************************************************/ |
|||
|
|||
#define PCI_SPECIAL_SHUTDOWN 1 |
|||
|
|||
/************************* PCI BUS DEVICE FUNCTION ********************/ |
|||
|
|||
/*
|
|||
* PCI bus device function |
|||
*/ |
|||
#define PCI_BUS_CS5536 0 |
|||
#define PCI_CFG_BASE 0x02000000 |
|||
|
|||
#define CS5536_ISA_FUNC 0 |
|||
#define CS5536_FLASH_FUNC 1 |
|||
#define CS5536_IDE_FUNC 2 |
|||
#define CS5536_ACC_FUNC 3 |
|||
#define CS5536_OHCI_FUNC 4 |
|||
#define CS5536_EHCI_FUNC 5 |
|||
#define CS5536_UDC_FUNC 6 |
|||
#define CS5536_OTG_FUNC 7 |
|||
#define CS5536_FUNC_START 0 |
|||
#define CS5536_FUNC_END 7 |
|||
#define CS5536_FUNC_COUNT (CS5536_FUNC_END - CS5536_FUNC_START + 1) |
|||
|
|||
/***************************** STANDARD PCI-2.2 EXPANSION ***********************/ |
|||
|
|||
/*
|
|||
* PCI configuration space |
|||
* we have to virtualize the PCI configure space head, so we should |
|||
* define the necessary IDs and some others. |
|||
*/ |
|||
/* VENDOR ID */ |
|||
#define CS5536_VENDOR_ID 0x1022 |
|||
|
|||
/* DEVICE ID */ |
|||
#define CS5536_ISA_DEVICE_ID 0x2090 |
|||
#define CS5536_FLASH_DEVICE_ID 0x2091 |
|||
#define CS5536_IDE_DEVICE_ID 0x2092 |
|||
#define CS5536_ACC_DEVICE_ID 0x2093 |
|||
#define CS5536_OHCI_DEVICE_ID 0x2094 |
|||
#define CS5536_EHCI_DEVICE_ID 0x2095 |
|||
#define CS5536_UDC_DEVICE_ID 0x2096 |
|||
#define CS5536_OTG_DEVICE_ID 0x2097 |
|||
|
|||
/* CLASS CODE : CLASS SUB-CLASS INTERFACE */ |
|||
#define CS5536_ISA_CLASS_CODE 0x060100 |
|||
#define CS5536_FLASH_CLASS_CODE 0x050100 |
|||
#define CS5536_IDE_CLASS_CODE 0x010180 |
|||
#define CS5536_ACC_CLASS_CODE 0x040100 |
|||
#define CS5536_OHCI_CLASS_CODE 0x0C0310 |
|||
#define CS5536_EHCI_CLASS_CODE 0x0C0320 |
|||
#define CS5536_UDC_CLASS_CODE 0x0C03FE |
|||
#define CS5536_OTG_CLASS_CODE 0x0C0380 |
|||
|
|||
/* BHLC : BIST HEADER-TYPE LATENCY-TIMER CACHE-LINE-SIZE */ |
|||
#define PCI_NONE_BIST 0x00 //RO not implemented yet.
|
|||
#define PCI_BRIDGE_HEADER_TYPE 0x80 //RO
|
|||
#define PCI_NORMAL_HEADER_TYPE 0x00 |
|||
#define PCI_NORMAL_LATENCY_TIMER 0x40 |
|||
#define PCI_NORMAL_CACHE_LINE_SIZE 0x08 //RW
|
|||
|
|||
/* BAR */ |
|||
#define PCI_BAR0_REG 0x10 |
|||
#define PCI_BAR1_REG 0x14 |
|||
#define PCI_BAR2_REG 0x18 |
|||
#define PCI_BAR3_REG 0x1c |
|||
#define PCI_BAR4_REG 0x20 |
|||
#define PCI_BAR5_REG 0x24 |
|||
#define PCI_BAR_COUNT 6 |
|||
#define PCI_BAR_RANGE_MASK 0xFFFFFFFE |
|||
|
|||
/* CARDBUS CIS POINTER */ |
|||
#define PCI_CARDBUS_CIS_POINTER 0x00000000 |
|||
|
|||
/* SUBSYSTEM VENDOR ID */ |
|||
#define CS5536_SUB_VENDOR_ID CS5536_VENDOR_ID |
|||
|
|||
/* SUBSYSTEM ID */ |
|||
#define CS5536_ISA_SUB_ID CS5536_ISA_DEVICE_ID |
|||
#define CS5536_FLASH_SUB_ID CS5536_FLASH_DEVICE_ID |
|||
#define CS5536_IDE_SUB_ID CS5536_IDE_DEVICE_ID |
|||
#define CS5536_ACC_SUB_ID CS5536_ACC_DEVICE_ID |
|||
#define CS5536_OHCI_SUB_ID CS5536_OHCI_DEVICE_ID |
|||
#define CS5536_EHCI_SUB_ID CS5536_EHCI_DEVICE_ID |
|||
#define CS5536_UDC_SUB_ID CS5536_UDC_DEVICE_ID |
|||
#define CS5536_OTG_SUB_ID CS5536_OTG_DEVICE_ID |
|||
|
|||
/* EXPANSION ROM BAR */ |
|||
#define PCI_EXPANSION_ROM_BAR 0x00000000 |
|||
|
|||
/* CAPABILITIES POINTER */ |
|||
#define PCI_CAPLIST_POINTER 0x00000000 |
|||
#define PCI_CAPLIST_USB_POINTER 0x40 |
|||
/* INTERRUPT */ |
|||
#define PCI_MAX_LATENCY 0x00 |
|||
#define PCI_MIN_GRANT 0x00 |
|||
|
|||
/**************************** EXPANSION PCI REG **************************************/ |
|||
|
|||
/*
|
|||
* IDE EXPANSION |
|||
*/ |
|||
#define PCI_IDE_CFG_REG 0x40 |
|||
#define CS5536_IDE_FLASH_SIGNATURE 0xDEADBEEF |
|||
#define PCI_IDE_DTC_REG 0x48 |
|||
#define PCI_IDE_CAST_REG 0x4C |
|||
#define PCI_IDE_ETC_REG 0x50 |
|||
#define PCI_IDE_PM_REG 0x54 |
|||
|
|||
/*
|
|||
* OHCI EXPANSION |
|||
*/ |
|||
#define PCI_USB_PM_REG 0x40 |
|||
|
|||
/*
|
|||
* EHCI EXPANSION |
|||
*/ |
|||
#define PCI_EHCI_LEGSMIEN_REG 0x50 |
|||
#define PCI_EHCI_LEGSMISTS_REG 0x54 |
|||
#define PCI_EHCI_FLADJ_REG 0x60 |
|||
|
|||
#endif /* _CS5536_PCI_H_ */ |
|||
|
|||
@ -0,0 +1,18 @@ |
|||
#ifndef FIREWALL_H |
|||
#define FIREWALL_H |
|||
|
|||
#define PCI_IDSEL_ATP8260 9 |
|||
#define IOG 0x4000 |
|||
#define I2CREG_ADDR (0xbfd00000|(IOG)|0xB0) |
|||
#define I2C_NACK 0x80 |
|||
#define I2C_RD 0x20 |
|||
#define I2C_WR 0x10 |
|||
#define I2C_START 0x80 |
|||
#define I2C_STOP 0x40 |
|||
|
|||
#define LS2F_COMA_ADDR 0xbe000000 |
|||
#define LS2F_COMB_ADDR 0xbe000020 |
|||
#define LS2F_PP_ADDR 0xbe000040 |
|||
#define LS2F_COM_CLK 1843200 |
|||
|
|||
#endif |
|||
@ -0,0 +1,81 @@ |
|||
/*
|
|||
* i8254.h: definitions for i8254 programmable interval timer in P5064 |
|||
* |
|||
* Copyright (c) 1997-1999, Algorithmics Ltd. All rights reserved. |
|||
* |
|||
* This program is free software; you can redistribute it and/or modify |
|||
* it under the terms of the "Free MIPS" License Agreement, a copy of |
|||
* which is available at: |
|||
* |
|||
* http://www.algor.co.uk/ftp/pub/doc/freemips-license.txt
|
|||
* |
|||
* You may not, however, modify or remove any part of this copyright |
|||
* message if this program is redistributed or reused in whole or in |
|||
* part. |
|||
* |
|||
* This program is distributed in the hope that it will be useful, |
|||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
|||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|||
* "Free MIPS" License for more details. |
|||
*/ |
|||
|
|||
/* Timer 0 is clock interrupt (irq0)
|
|||
* Timer 1 is refresh clock |
|||
* Timer 2 is speaker tone |
|||
*/ |
|||
|
|||
#define PT_CLOCK 0 |
|||
#define PT_REFRESH 1 |
|||
#define PT_SPEAKER 2 |
|||
#define PT_CONTROL 3 |
|||
|
|||
#ifndef __ASSEMBLER__ |
|||
struct i8254 { |
|||
unsigned char pt_counter0; |
|||
unsigned char pt_counter1; |
|||
unsigned char pt_counter2; |
|||
unsigned char pt_control; |
|||
}; |
|||
|
|||
#define pt_clock pt_counter0 |
|||
#define pt_refresh pt_counter1 |
|||
#define pt_speaker pt_counter2 |
|||
|
|||
#else |
|||
|
|||
#define PT_REG(x) (x) |
|||
|
|||
#endif |
|||
|
|||
/*
|
|||
* control word definitions |
|||
*/ |
|||
#define PTCW_RBCMD (3<<6) /* read-back command */ |
|||
#define PTCW_RB_NCNT 0x20 /* rb: no count */ |
|||
#define PTCW_RB_NSTAT 0x10 /* rb: no status */ |
|||
#define PTCW_RB_SC(x) (0x02<<(x)) /* rb: select counter x */ |
|||
#define PTCW_SC(x) ((x)<<6) /* select counter x */ |
|||
#define PTCW_CLCMD (0<<4) /* counter latch command */ |
|||
#define PTCW_LSB (1<<4) /* r/w least signif. byte only */ |
|||
#define PTCW_MSB (2<<4) /* r/w most signif. byte only */ |
|||
#define PTCW_16B (3<<4) /* r/w 16 bits, lsb then msb */ |
|||
#define PTCW_MODE(x) ((x)<<1) /* set mode to x */ |
|||
#define PTCW_BCD 0x1 /* operate in BCD mode */ |
|||
|
|||
/*
|
|||
* Status word definitions |
|||
*/ |
|||
#define PTSW_OUTPUT 0x80 /* output pin active */ |
|||
#define PTSW_NULL 0x40 /* null count */ |
|||
|
|||
/*
|
|||
* Mode definitions |
|||
*/ |
|||
#define MODE_ITC 0 /* interrupt on terminal count */ |
|||
#define MODE_HROS 1 /* hw retriggerable one-shot */ |
|||
#define MODE_RG 2 /* rate generator */ |
|||
#define MODE_SQW 3 /* square wave generator */ |
|||
#define MODE_STS 4 /* software triggered strobe */ |
|||
#define MODE_HTS 5 /* hardware triggered strobe */ |
|||
|
|||
#define PT_CRYSTAL 14318180 /* timer crystal hz (ticks/sec) */ |
|||
@ -0,0 +1,189 @@ |
|||
/* $OpenBSD: isapnpreg.h,v 1.4 1997/12/25 09:22:41 downsj Exp $ */ |
|||
/* $NetBSD: isapnpreg.h,v 1.5 1997/08/12 07:34:34 mikel Exp $ */ |
|||
|
|||
/*
|
|||
* Copyright (c) 199 Christos Zoulas. All rights reserved. |
|||
* |
|||
* Redistribution and use in source and binary forms, with or without |
|||
* modification, are permitted provided that the following conditions |
|||
* are met: |
|||
* 1. Redistributions of source code must retain the above copyright |
|||
* notice, this list of conditions and the following disclaimer. |
|||
* 2. Redistributions in binary form must reproduce the above copyright |
|||
* notice, this list of conditions and the following disclaimer in the |
|||
* documentation and/or other materials provided with the distribution. |
|||
* 3. All advertising materials mentioning features or use of this software |
|||
* must display the following acknowledgement: |
|||
* This product includes software developed by Christos Zoulas. |
|||
* 4. The name of the author may not be used to endorse or promote products |
|||
* derived from this software without specific prior written permission. |
|||
* |
|||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
|||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
|||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
|||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
|||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
|||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
|||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
|||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
|||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
|||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
|||
*/ |
|||
|
|||
#ifndef _DEV_ISA_ISAPNPREG_H_ |
|||
#define _DEV_ISA_ISAPNPREG_H_ |
|||
|
|||
/*
|
|||
* ISA Plug and Play register definitions; |
|||
* From Plug and Play ISA Specification V1.0a, May 5 1994 |
|||
*/ |
|||
|
|||
#define ISAPNP_MAX_CARDS 8 |
|||
#define ISAPNP_MAX_IDENT 32 |
|||
#define ISAPNP_MAX_DEVCLASS 16 |
|||
#define ISAPNP_SERIAL_SIZE 9 |
|||
#define ISAPNP_MAX_TAGSIZE 256 |
|||
|
|||
#define ISAPNP_ADDR 0x279 /* Write only */ |
|||
#define ISAPNP_WRDATA 0xa79 /* Write only */ |
|||
|
|||
/* The read port is in range 0x203 to 0x3ff */ |
|||
#define ISAPNP_RDDATA_MIN 0x203 /* Read only */ |
|||
#define ISAPNP_RDDATA_MAX 0x3ff |
|||
|
|||
#define ISAPNP_LFSR_INIT 0x6A /* Initial value of LFSR sequence */ |
|||
#define ISAPNP_LFSR_LENGTH 32 /* Number of values in LFSR sequence */ |
|||
/* Formula to compute the next value */ |
|||
#define ISAPNP_LFSR_NEXT(v) (((v) >> 1) | (((v) & 1) ^ (((v) & 2) >> 1)) << 7) |
|||
|
|||
#define ISAPNP_SET_RD_PORT 0x00 |
|||
#define ISAPNP_SERIAL_ISOLATION 0x01 |
|||
#define ISAPNP_CONFIG_CONTROL 0x02 |
|||
#define ISAPNP_CC_RESET 0x01 |
|||
#define ISAPNP_CC_WAIT_FOR_KEY 0x02 |
|||
#define ISAPNP_CC_RESET_CSN 0x04 |
|||
#define ISAPNP_CC_RESET_DRV 0x07 |
|||
#define ISAPNP_WAKE 0x03 |
|||
#define ISAPNP_RESOURCE_DATA 0x04 |
|||
#define ISAPNP_STATUS 0x05 |
|||
#define ISAPNP_CARD_SELECT_NUM 0x06 |
|||
#define ISAPNP_LOGICAL_DEV_NUM 0x07 |
|||
|
|||
#define ISAPNP_ACTIVATE 0x30 |
|||
#define ISAPNP_IO_RANGE_CHECK 0x31 |
|||
|
|||
#define ISAPNP_NUM_MEM 4 |
|||
#define ISAPNP_MEM_DESC { 0x40, 0x48, 0x50, 0x58 } |
|||
#define ISAPNP_MEM_BASE_23_16 0x0 |
|||
#define ISAPNP_MEM_BASE_15_8 0x1 |
|||
#define ISAPNP_MEM_CONTROL 0x2 |
|||
#define ISAPNP_MEM_CONTROL_LIMIT 1 |
|||
#define ISAPNP_MEM_CONTROL_16 2 |
|||
#define ISAPNP_MEM_LRANGE_23_16 0x3 |
|||
#define ISAPNP_MEM_LRANGE_15_8 0x4 |
|||
|
|||
#define ISAPNP_NUM_IO 8 |
|||
|
|||
#define ISAPNP_IO_DESC0 0x60 |
|||
#define ISAPNP_IO_DESC1 0x62 |
|||
#define ISAPNP_IO_DESC2 0x64 |
|||
#define ISAPNP_IO_DESC3 0x66 |
|||
#define ISAPNP_IO_DESC4 0x68 |
|||
#define ISAPNP_IO_DESC5 0x6a |
|||
#define ISAPNP_IO_DESC6 0x6c |
|||
#define ISAPNP_IO_DESC7 0x6e |
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#define ISAPNP_IO_DESC { 0x60, 0x62, 0x64, 0x68, 0x6a, 0x6c, 0x6e } |
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#define ISAPNP_IO_BASE_15_8 0x0 |
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#define ISAPNP_IO_BASE_7_0 0x1 |
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|
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#define ISAPNP_IRQ_DESC0 0x70 |
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#define ISAPNP_IRQ_DESC1 0x72 |
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#define ISAPNP_NUM_IRQ 16 |
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#define ISAPNP_IRQ_DESC { 0x70, 0x72 } |
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#define ISAPNP_IRQ_NUMBER 0x0 |
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#define ISAPNP_IRQ_CONTROL 0x1 |
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#define ISAPNP_IRQ_LEVEL 1 |
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#define ISAPNP_IRQ_HIGH 2 |
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|
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#define ISAPNP_NUM_DRQ 8 |
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#define ISAPNP_DRQ_DESC { 0x74, 0x75 } |
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|
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#define ISAPNP_NUM_MEM32 4 |
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#define ISAPNP_MEM32_DESC { 0x76, 0x80, 0x90, 0xa0 } |
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#define ISAPNP_MEM32_BASE_31_24 0x0 |
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#define ISAPNP_MEM32_BASE_23_16 0x1 |
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#define ISAPNP_MEM32_BASE_15_8 0x2 |
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#define ISAPNP_MEM32_BASE_7_0 0x3 |
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#define ISAPNP_MEM32_CONTROL 0x4 |
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#define ISAPNP_MEM32_CONTROL_LIMIT 1 |
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#define ISAPNP_MEM32_CONTROL_16 2 |
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#define ISAPNP_MEM32_CONTROL_32 6 |
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#define ISAPNP_MEM32_LRANGE_31_24 0x5 |
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#define ISAPNP_MEM32_LRANGE_23_16 0x6 |
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#define ISAPNP_MEM32_LRANGE_15_8 0x7 |
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#define ISAPNP_MEM32_LRANGE_7_0 0x8 |
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|
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/* Small Tags */ |
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#define ISAPNP_TAG_VERSION_NUM 0x1 |
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#define ISAPNP_TAG_LOGICAL_DEV_ID 0x2 |
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#define ISAPNP_TAG_COMPAT_DEV_ID 0x3 |
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#define ISAPNP_TAG_IRQ_FORMAT 0x4 |
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#define ISAPNP_IRQTYPE_EDGE_PLUS 1 |
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#define ISAPNP_IRQTYPE_EDGE_MINUS 2 |
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#define ISAPNP_IRQTYPE_LEVEL_PLUS 4 |
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#define ISAPNP_IRQTYPE_LEVEL_MINUS 8 |
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#define ISAPNP_TAG_DMA_FORMAT 0x5 |
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#define ISAPNP_DMAWIDTH_8 0x00 |
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#define ISAPNP_DMAWIDTH_8_16 0x01 |
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#define ISAPNP_DMAWIDTH_16 0x02 |
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#define ISAPNP_DMAWIDTH_RESERVED 0x03 |
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#define ISAPNP_DMAWIDTH_MASK 0x03 |
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#define ISAPNP_DMAATTR_BUS_MASTER 0x04 |
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#define ISAPNP_DMAATTR_INCR_8 0x08 |
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#define ISAPNP_DMAATTR_INCR_16 0x10 |
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#define ISAPNP_DMAATTR_MASK 0x1c |
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#define ISAPNP_DMASPEED_COMPAT 0x00 |
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#define ISAPNP_DMASPEED_A 0x20 |
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#define ISAPNP_DMASPEED_B 0x40 |
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#define ISAPNP_DMASPEED_F 0x60 |
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#define ISAPNP_DMASPEED_MASK 0x60 |
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#define ISAPNP_TAG_DEP_START 0x6 |
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#define ISAPNP_DEP_PREFERRED 0x0 |
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#define ISAPNP_DEP_ACCEPTABLE 0x1 |
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#define ISAPNP_DEP_FUNCTIONAL 0x2 |
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#define ISAPNP_DEP_RESERVED 0x3 |
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#define ISAPNP_DEP_MASK 0x3 |
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#define ISAPNP_DEP_UNSET 0x80 /* Internal */ |
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#define ISAPNP_DEP_CONFLICTING 0x81 /* Internal */ |
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#define ISAPNP_TAG_DEP_END 0x7 |
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#define ISAPNP_TAG_IO_PORT_DESC 0x8 |
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#define ISAPNP_IOFLAGS_16 0x1 |
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#define ISAPNP_TAG_FIXED_IO_PORT_DESC 0x9 |
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#define ISAPNP_TAG_RESERVED1 0xa |
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#define ISAPNP_TAG_RESERVED2 0xb |
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#define ISAPNP_TAG_RESERVED3 0xc |
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#define ISAPNP_TAG_RESERVED4 0xd |
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#define ISAPNP_TAG_VENDOR_DEF 0xe |
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#define ISAPNP_TAG_END 0xf |
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|
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/* Large Tags */ |
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#define ISAPNP_LARGE_TAG 0x80 |
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#define ISAPNP_TAG_MEM_RANGE_DESC 0x81 |
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#define ISAPNP_MEMATTR_WRITEABLE 0x01 |
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#define ISAPNP_MEMATTR_CACHEABLE 0x02 |
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#define ISAPNP_MEMATTR_HIGH_ADDR 0x04 |
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#define ISAPNP_MEMATTR_SHADOWABLE 0x20 |
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#define ISAPNP_MEMATTR_ROM 0x40 |
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#define ISAPNP_MEMATTR_MASK 0x67 |
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#define ISAPNP_MEMWIDTH_8 0x00 |
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#define ISAPNP_MEMWIDTH_16 0x08 |
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#define ISAPNP_MEMWIDTH_8_16 0x10 |
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#define ISAPNP_MEMWIDTH_32 0x18 |
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#define ISAPNP_MEMWIDTH_MASK 0x18 |
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#define ISAPNP_TAG_ANSI_IDENT_STRING 0x82 |
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#define ISAPNP_TAG_UNICODE_IDENT_STRING 0x83 |
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#define ISAPNP_TAG_VENDOR_DEFINED 0x84 |
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#define ISAPNP_TAG_MEM32_RANGE_DESC 0x85 |
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#define ISAPNP_TAG_FIXED_MEM32_RANGE_DESC 0x86 |
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|
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#endif /* _DEV_ISA_ISAPNPREG_H_ */ |
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