From b13a558832b9da2b901553a88d42a555eb168184 Mon Sep 17 00:00:00 2001 From: Chen Xinke Date: Mon, 22 Jan 2018 11:29:21 +0800 Subject: [PATCH] Fix LPC IO-BAR fail problem. Change-Id: I1b7b1c8f79523f366fa357bc83a193ff72d546d7 --- Targets/Bonito3a3000_7a/pci/ls7a_pci.c | 19 +++++++++++++++++++ pmon/arch/mips/ls7a/ls7a_init.S | 2 ++ 2 files changed, 21 insertions(+) diff --git a/Targets/Bonito3a3000_7a/pci/ls7a_pci.c b/Targets/Bonito3a3000_7a/pci/ls7a_pci.c index 6f947a2a..cd395993 100644 --- a/Targets/Bonito3a3000_7a/pci/ls7a_pci.c +++ b/Targets/Bonito3a3000_7a/pci/ls7a_pci.c @@ -57,6 +57,7 @@ void pci_write_type1_config32(u32 bus, u32 dev, u32 func, u32 reg, u32 val){ u32 _pci_conf_readn(device_t tag, int reg, int width) { int bus, device, function; + u32 val_raw; if ((width != 4) || (reg & 3) || reg < 0 || reg >= 0x100) { printf("_pci_conf_readn: bad reg 0x%x, tag 0x%x, width 0x%x\n", reg, tag, width); @@ -69,6 +70,19 @@ u32 _pci_conf_readn(device_t tag, int reg, int width) if(bus == 0 && (device >=9 && device <= 20) && reg == 0x8){ return 0x06040001; } + //workaround LPC BAR5 + if(bus == 0 && device == 23 && function == 0 && reg == 0x24){ + return 0; + } + //workaround LPC BAR4 + if(bus == 0 && device == 23 && function == 0 && reg == 0x20){ + val_raw = pci_read_type0_config32(device, function, reg); + if(val_raw == 0xfffe0001) + return val_raw; + else + return val_raw & ~0xfc000000; + } + if (bus == 0) { /* Type 0 configuration on onboard PCI bus */ @@ -160,6 +174,11 @@ void _pci_conf_writen(device_t tag, int reg, u32 data,int width) data = data << ((reg & 3) * 8); data = (ori & mask) | data; + //workaround LPC BAR4 + if(bus == 0 && device == 23 && function == 0 && (reg & 0xfc) == 0x20){ + data |= 0xfc000000; + } + if (bus == 0) { return pci_write_type0_config32(device, function, reg & 0xfc, data); diff --git a/pmon/arch/mips/ls7a/ls7a_init.S b/pmon/arch/mips/ls7a/ls7a_init.S index aa55236d..c4c8cfd6 100644 --- a/pmon/arch/mips/ls7a/ls7a_init.S +++ b/pmon/arch/mips/ls7a/ls7a_init.S @@ -208,6 +208,8 @@ //fix LPC class code li a2, 0x06010000 sw a2, 0x3448(t0) + li a2, 0xfd + sw a2, 0x3464(t0) //disable pci scan of MISC and confbus lw a0, 0x3800(t0)