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2k dll clk loop test trainning 

Change-Id: Iaf7a5350f4637af2c6579046f2fb5a505fb6de8d
master
baoqingyuan 7 years ago
committed by wuze
parent
d4a83e8a1e
commit
b375862b20
4 changed files with 2916 additions and 2190 deletions
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  1. 3466
      Targets/LS2K/ls2k/ddr_dir/loongson3C_ddr3_leveling.S
  2. 1513
      Targets/LS2K/ls2k/ddr_dir/ls3A8_ddr_config.S
  3. 2
      Targets/LS2K/ls2k/loongson_mc2_param.S
  4. 1
      Targets/LS2K/ls2k/start.S

3466
Targets/LS2K/ls2k/ddr_dir/loongson3C_ddr3_leveling.S
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File diff suppressed because it is too large

1513
Targets/LS2K/ls2k/ddr_dir/ls3A8_ddr_config.S
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File diff suppressed because it is too large

2
Targets/LS2K/ls2k/loongson_mc2_param.S
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@ -368,7 +368,7 @@ MC0_DDR3_RDIMM_CTRL_0x1c0: .dword 0x3030c80c03042005
//_00000000 pm_tRESET _00000000 pm_tCKE _00000000 pm_tXPR _00000000 pm_tMOD _00000000 pm_tZQCL _00000000 pm_tZQ_CMD _00000000 pm_tWLDQSEN 000_00000 pm_tRDDATA //_00000000 pm_tRESET _00000000 pm_tCKE _00000000 pm_tXPR _00000000 pm_tMOD _00000000 pm_tZQCL _00000000 pm_tZQ_CMD _00000000 pm_tWLDQSEN 000_00000 pm_tRDDATA
MC0_DDR3_RDIMM_CTRL_0x1c8: .dword 0x1107070715854080 MC0_DDR3_RDIMM_CTRL_0x1c8: .dword 0x1107070715854080
//00_000000 pm_tFAW 0000_0000 pm_tRRD 0000_0000 pm_tRCD _00000000 pm_tRP _00000000 pm_tREF _00000000 pm_tRFC _00000000 pm_tZQCS _00000000 pm_tZQperiod //00_000000 pm_tFAW 0000_0000 pm_tRRD 0000_0000 pm_tRCD _00000000 pm_tRP _00000000 pm_tREF _00000000 pm_tRFC _00000000 pm_tZQCS _00000000 pm_tZQperiod
MC0_DDR3_RDIMM_CTRL_0x1d0: .dword 0x0a02090402000019 MC0_DDR3_RDIMM_CTRL_0x1d0: .dword 0x0a020c0402000019
//0000_0000 pm_tODTL _00000000 pm_tXSRD 0000_0000 pm_tPHY_RDLAT 000_00000 pm_tPHY_WRLAT 000000_00_00000000_00000000 pm_tRAS_max 00_000000 pm_tRAS_min //0000_0000 pm_tODTL _00000000 pm_tXSRD 0000_0000 pm_tPHY_RDLAT 000_00000 pm_tPHY_WRLAT 000000_00_00000000_00000000 pm_tRAS_max 00_000000 pm_tRAS_min
MC0_DDR3_RDIMM_CTRL_0x1d8: .dword 0x14050c0608070406 MC0_DDR3_RDIMM_CTRL_0x1d8: .dword 0x14050c0608070406
//_00000000 pm_tXPDLL _00000000 pm_tXP 000_00000 pm_tWR 0000_0000 pm_tRTP 0000_0000 pm_tRL 0000_0000 pm_tWL 0000_0000 pm_tCCD 0000_0000 pm_tWTR //_00000000 pm_tXPDLL _00000000 pm_tXP 000_00000 pm_tWR 0000_0000 pm_tRTP 0000_0000 pm_tRL 0000_0000 pm_tWL 0000_0000 pm_tCCD 0000_0000 pm_tWTR

1
Targets/LS2K/ls2k/start.S
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@ -754,6 +754,7 @@ start_now:
//#define DEBUG_DDR //#define DEBUG_DDR
//#define DEBUG_DDR_PARAM //#define DEBUG_DDR_PARAM
//#define PRINT_DDR_LEVELING //#define PRINT_DDR_LEVELING
//#define DLL_DELAY_LOOP
TTYDBG("\r\nStart Init Memory, wait a while......\r\n") TTYDBG("\r\nStart Init Memory, wait a while......\r\n")
#################################### ####################################

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