Fixup 3A X1BAR for PCIE DEVICE:

1.Add x1bar window 0x0000000040000000 -> 0x00000e50000000f7(1GB) for pcie mem1 space
2.Add x1bar window 0x0000000020000000 -> 0x00000e00000000f7(256MB) for ls2h framebuffer
3.Add TLB table entry 0xe0000000      -> 0x20000000 for ls2h frambuffer,and change framebuffer
  base address from 0xc0000000 to 0xe0000000

Change-Id: Ia76c704dbd082cfe00caf4620683ae1e6f51ceae
Target:LS3A2H

Targets/Bonito3a2h/Bonito/loongson3_HT_init_2h.S

@@ -49,16 +49,24 @@
 
 #endif
 
-// below added for ls2h dc frame buffer
-  
- //map 0x90000e00_00000000 --> 0x40000000
+// below added for ls2h pcie device mem1 space
+ //map 0x90000e50_00000000 --> 0x40000000
     dli t1, 0x0000000040000000
     sd  t1, 0x18(t0)
     dli t1, 0xffffffffc0000000
     sd  t1, 0x58(t0)
-    dli t1, 0x00000e00000000f7
+    dli t1, 0x00000e50000000f7
     sd  t1, 0x98(t0)
 
+// below added for ls2h dc frame buffer
+ //map 0x90000e00_00000000 --> 0x20000000
+
+    dli t1, 0x0000000020000000
+    sd  t1, 0x20(t0)
+    dli t1, 0xfffffffff0000000
+    sd  t1, 0x60(t0)
+    dli t1, 0x00000e00000000f7
+    sd  t1, 0xa0(t0)
 #if 0
  //HT Space enable
  //map 0x90000e00_00000000 --> 0x90000e00_00000000

Targets/Bonito3a2h/Bonito/pcitlb.S

@@ -5,7 +5,8 @@
 
 /***********************************************************************************************************/
 /**************************************** MAP KSEG2 ********************************************************/
-/** MAP virtual address: 0xc0000000~ 0xffffffff to physical address:  0x40000000~ 0x7fffffff for PCI-MEM  **/
+/** MAP virtual address: 0xc0000000~ 0xdfffffff to physical address:  0x40000000~ 0x5fffffff for PCI-MEM  **/
+/** MAP virtual address: 0xe0000000~ 0xffffffff to physical address:  0x60000000~ 0x7fffffff for PCI-MEM  **/
 /***********************************************************************************************************/
 
 	li	t0, 0x40000000
@@ -60,9 +61,49 @@
 	nop
 	tlbwi                             # random++
 
-	bgez	t0, 1b
+	addiu	t1,t0,-16
+	bgez	t1, 1b
 	addiu	t0, t0, -1
+	
+	li	t0, 16
+
+	li	t3,  0xe0000000   # entry_hi
+	#dli	t4, (0x00000e0020000000 >> 6)|0x17   # entry_lo, uncached, valid, dirty, global
+	#li	t4, 0x0e004000
+
+	li	t4, 0x00002000
+	#li	t4, 0x0efdf000
+
+	.set mips64
+	dsll	t4, t4, 10
+	.set mips3
+	ori	t4, t4, 0x17
+
+	li	t5, (0x1000000>>6)            # 16M stride
+	li	t6, 0x2000000             # VPN2 32M stride
+
+	.set mips64
+1:
+	dmtc0	t3, COP_0_TLB_HI
+	daddu	t3, t3, t6
 
+	dmtc0	t4, COP_0_TLB_LO0
+	daddu	t4, t4, t5
+	dmtc0	t4, COP_0_TLB_LO1
+	daddu	t4, t4, t5
+
+	.set mips3
+
+	mtc0	t0, COP_0_TLB_INDEX           # 16MB page
+	nop
+	nop
+	nop
+	nop
+	nop
+	tlbwi                             # random++
+
+	bgez	t0, 1b
+	addiu	t0, t0, -1
 
 	li	t0, 32
 	mtc0	t0, COP_0_TLB_WIRED    # 16MB page

Targets/Bonito3a2h/dev/dc.c

@@ -34,8 +34,8 @@ typedef unsigned long dma_addr_t;
 
 #define RANDOM_HEIGHT_Z 37
 
-static char *ADDR_CURSOR = 0xc6000000;
-static char *MEM_ptr = 0xc2000000;	/* frame buffer address register on ls2h mem */
+static char *ADDR_CURSOR = 0xe6000000;
+static char *MEM_ptr = 0xe2000000;	/* frame buffer address register on ls2h mem */
 
 static int MEM_ADDR = 0;
 

Targets/Bonito3a2h/pci/pci_machdep.c

@@ -126,7 +126,7 @@ _pci_hwinit(initialise, iot, memt)
 		pd->pa.pa_memt = pmalloc(sizeof(bus_space_tag_t));
 		pd->pa.pa_memt->bus_reverse = 1;
 		//pd->pa.pa_memt->bus_base = PCI_LOCAL_MEM_PCI_BASE;
-		pd->pa.pa_memt->bus_base = 0xc0000000;
+		pd->pa.pa_memt->bus_base = 0xb0000000;
 		pd->pa.pa_dmat = &bus_dmamap_tag;
 		pd->bridge.secbus = pb;