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Add cmds: usbinstall and cdinstall to install linux system from CD-ROM and USB DISK 

Add DDR3 auto configration, now probe DDR DIMM one by one then merge values together

Add autoinstall function befor auto load by enter <ENTER> (<F2> seems better) key
master
xiaqichao 14 years ago
parent
6262f42009
commit
bd7b1d8bd8
4 changed files with 840 additions and 93 deletions
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  1. 563
      Targets/Bonito3a780e/Bonito/i2c.S
  2. 51
      Targets/Bonito3a780e/Bonito/loongson3_ddr2_config.S
  3. 226
      Targets/Bonito3a780e/Bonito/start.S
  4. 93
      pmon/cmds/install.c

563
Targets/Bonito3a780e/Bonito/i2c.S
View File

@ -74,7 +74,8 @@ END(i2cread)
#define SPD_NODEVICE 0xff
#define SPD_TYPEDDR2 0x8
#define SPD_TYPEDDR3 0xc
#define SPD_TYPEDDR3 0xb
#define SPD_NODIMM 0x0
#define DDRTYPE_MASK 0x7
#define DDRPERSZ_512M 0x10
@ -96,40 +97,87 @@ END(i2cread)
#define DDR2SIZE_2G_MASK 0x30
#define DDR2SIZE_MASK 0x70
/************************************************************
* Input: a0, i2c device ID; a1, in MC0 or MC1 flags
* Output: v0, equals orignal s1, included all DIMM info
************************************************************/
LEAF(PROBE_DIMM)
move a2,ra;
move s2,a0; //store a0: i2C DEVICE id
move s3,a1; //store a1: REG offset in i2c dev
move s2,a0; //store a0: i2C DEVICE id, s2 can be only used before mszie set
move s3,a1; //store a1: MC0 or MC1 used flags
li a1, 2;
bal i2cread;
nop;
beq v0,SPD_NODEVICE, out;
beq v0,SPD_TYPEDDR3, 4f;
nop;
beq v0,SPD_TYPEDDR2, 4f;
nop;
/* set DIMM type @ s1[7:7] */
/* assumed here v0 should be 0xc or 0x8 */
xor v0,v0
jr a2
nop
4:
li s1,0x0
/* set DDR type @ s1[7:7] */
/* assumed here v0 should be 0xb or 0x8 */
//bne v0,SPD_TYPEDDR3, ddr2
andi v0,0x4;
srl v0,0x2;
move t1,v0
subu t1, 0x8
beqz t1, 400f
nop
li v0,0x1
b 500f
nop
400:
li v0, 0x0
500:
sll v0,DDRTYPE_MASK ;
or s1,v0;
/* set CONTROLLER_SELECT@ s1[3:2] */
/* a1 should set to be MC0_USED or MC1_USD */
/* Firt check whether BOTH MC0 and MC1 used, if
true,set s1[3:2] = 2b'00
*/
or s1,s3;
andi t1,s3,0xc
or s1,t1;
#if 0 /* left done in MERGE_CHANNEL */
andi t1,s1,0xc;
bne t1,0xc,10f;
nop
subu s1,0xc
#endif
10:
/* added for DDR3 check */
// if not ddr3,jump to 100f
// else, directly set ddr3 size to be 2G
li a0, 0x80
and a0, s1,a0
beqz a0,100f //DDR2
nop
#if 1
ori s1,DDRPERSZ_1G // DDR3, default size 2G
b 15f
nop
#else
//DDR3
move a0, s2; //store a1: REG offset in i2c dev
li a1, 4;
bal i2cread;
nop;
andi v0, v0, 0xf
addi v0, v0, 1
sll v0, v0, 4
nop
or s1, s1, v0
nop
b 15f
nop
#endif
100:
/* set SIZE_PER_CONTROLLE @ s1[6:4] */
/* step 1: read out number of DIMMS Ranks(CS) */
move a0, s2; //store a1: REG offset in i2c dev
@ -177,6 +225,7 @@ LEAF(PROBE_DIMM)
bne v0,0x20000000, 13f
nop;
#if 0
/* check whther this channel is smaller than others
if smller: remove other bits,and set DDRPERSZ_512M
else: do nothing, don't set PERSIZE_BIT
@ -193,6 +242,7 @@ LEAF(PROBE_DIMM)
and s1,t2;
211:
#endif // let compare size outside
ori s1,DDRPERSZ_512M ;
b 15f;
nop
@ -200,6 +250,7 @@ LEAF(PROBE_DIMM)
bne v0,0x40000000, 14f
nop
#if 0
/* check whther this channel is smaller than others
if smller: remove other bits,and set DDRPERSZ_1G
else: do nothing, don't set PERSIZE_BIT
@ -214,6 +265,7 @@ LEAF(PROBE_DIMM)
and s1,t2;
131:
#endif // let compare size outside
ori s1,DDRPERSZ_1G;
b 15f;
nop
@ -222,6 +274,7 @@ LEAF(PROBE_DIMM)
bne v0,0x80000000, 15f
nop
#if 0
/* check whther this channel is smaller than others
if smller: remove other bits,and set DDRPERSZ_2G
else: do nothing, don't set PERSIZE_BIT
@ -236,15 +289,41 @@ LEAF(PROBE_DIMM)
and s1,t2;
141:
#endif // let compare size outside
ori s1,DDRPERSZ_2G;
15:
/* check whether MC0 or MC1 used to set CS_MAP */
//bne s3, MC0_USED, 2f;
bne s3, 0x4, 2f;
move a0,s3
andi a0,0xc
bne a0, MC0_USED, 2f;
nop;
/* set DDR MC0_CS_MAP @s1[11:8] */
ori s1, 0x400 // at leaset one bit is selected
// First,check whether MC0DIMM0 used
move a0,s3
andi a0,0xf0
bne a0,0x30,160f
nop
// MC0_DIMM0
ori s1, 0x100 // at leaset one bit is selected, CS_MAP[0]
move a0,s2;
li a1, 5;
bal i2cread;
nop;
andi v0,0x1;
beq v0,0x0,16f;
nop;
ori s1,0x200; // set CS_MAP[1] = 1'b1
b 16f
nop
160:
// MC0_DIMM1
ori s1, 0x400 // at leaset one bit is selected, CS_MAP[2]
move a0,s2;
li a1, 5;
bal i2cread;
@ -255,7 +334,12 @@ LEAF(PROBE_DIMM)
ori s1,0x800;
16:
/* set DDR MC0_COL_SIZE @s1[18:16] */
andi a0, s1,0x80
bnez a0, 1601f
nop
/* set DDR2 MC0_COL_SIZE @s1[18:16] */
move a0,s2;
li a1, 4;
bal i2cread;
@ -285,13 +369,108 @@ LEAF(PROBE_DIMM)
sll t0,0x14;
or s1,t0;
/* set MC0_ECC bit @s1[32] */
move a0,s2;
li a1, 11;
bal i2cread;
li t0,0x2;
andi v0,0x2;
srl v0,0x1;
dsll v0,32;
//dli v0,0x100000000 // for test
or s1,v0;
/* set DIMM Type information @s1[33:33] */
move a0,s2;
li a1, 20;
bal i2cread;
nop;
andi v0,0x1; // only to check whether in Register Dual In_line memory module
dsll v0,33;
or s1,v0;
b 1602f
nop
1601: //DDR3
/* set DDR3 MC0_COL_SIZE @s1[18:16] */
move a0,s2;
li a1, 5;
bal i2cread;
nop;
andi v0,0x7
addi v0,0x9
li t0,14;
sub t0,v0;
sll t0,0x10;
or s1,t0;
/* set MC0_EIGHT_BANK @s1[19] */
li a0,0x80000
or s1,a0; // at leaset 8 banks
/* set DDR MC0_ROW_SIZE @s1[22:20] */
move a0,s2;
li a1, 5;
bal i2cread;
nop;
andi v0,0x38
srl v0,0x3
li t0,3;
sub t0,v0;
sll t0,0x14;
or s1,t0;
#if 0
/* set MC0_ECC bit @s1[32] */
move a0,s2;
li a1, 11;
bal i2cread;
li t0,0x2;
andi v0,0x2;
srl v0,0x1;
dsll v0,32;
//dli v0,0x100000000 // for test
or s1,v0;
/* set DIMM Type information @s1[33:33] */
move a0,s2;
li a1, 20;
bal i2cread;
nop;
andi v0,0x1; // only to check whether in Register Dual In_line memory module
dsll v0,33;
or s1,v0;
#endif
1602:
///////////////////
b out;
nop;
2: /* MC1_USED */
#if 1
// First,check whether MC1DIMM0 used
move a0,s3
andi a0,0xf0
bne a0,0x30,260f
nop
/* set DDR MC1_CS_MAP @s1[15:12] ? */
//below check for MC1_DIMM0
ori s1, 0x1000 // at leaset one bit is selected, CS_MAP[0]
move a0,s2;
li a1, 5;
bal i2cread;
nop;
andi v0,0x1;
beq v0,0x0,26f;
nop;
ori s1,0x2000; // set CS_MAP[1] = 1'b1
b 26f
nop
260: // MC1_DIMM1
ori s1, 0x4000 // at leaset one bit is selected
move a0,s2;
li a1, 5;
@ -303,6 +482,10 @@ LEAF(PROBE_DIMM)
ori s1,0x8000
26:
andi a0, s1,0x80
bnez a0, 2601f
nop
/* set DDR MC1_COL_SIZE @s1[26:24] */
move a0,s2;
li a1, 4;
@ -332,10 +515,352 @@ LEAF(PROBE_DIMM)
sub t0,v0;
sll t0,0x1c;
or s1,t0;
/* set MC1_ECC bit @s1[34] */
move a0,s2;
li a1, 11;
bal i2cread;
li t0,0x2;
andi v0,0x2;
srl v0,0x1;
dsll v0,34;
or s1,v0;
/* set DIMM Type information @s1[35:35] */
move a0,s2;
li a1, 20;
bal i2cread;
nop;
and v0,0x1; // only to check whether in Register Dual In_line memory module
dsll v0,35;
or s1,v0;
b 2602f
nop
2601:
/* set DDR3 MC1_COL_SIZE @s1[26:24] */
move a0,s2;
li a1, 5;
bal i2cread;
nop;
andi v0,0x7
addi v0,0x9
li t0,14;
sub t0,v0;
sll t0,0x18;
or s1,t0;
/* set MC0_EIGHT_BANK @s1[19] */
li a0,0x8000000
or s1,a0 // at leaset 8 banks
/* set DDR MC0_ROW_SIZE @s1[30:28] */
move a0,s2;
li a1, 5;
bal i2cread;
nop;
andi v0,0x38
srl v0,0x3
li t0,3;
sub t0,v0;
sll t0,0x1c;
or s1,t0;
#if 0
/* set MC0_ECC bit @s1[32] */
move a0,s2;
li a1, 11;
bal i2cread;
li t0,0x2;
andi v0,0x2;
srl v0,0x1;
dsll v0,32;
//dli v0,0x100000000 // for test
or s1,v0;
/* set DIMM Type information @s1[33:33] */
move a0,s2;
li a1, 20;
bal i2cread;
nop;
andi v0,0x1; // only to check whether in Register Dual In_line memory module
dsll v0,33;
or s1,v0;
#endif
out:/* out of MC0_CS_MAP or MC1_CS_MAP */
2602:
out: /* out of MC0_CS_MAP or MC1_CS_MAP */
//jr ra
move v0,s1
jr a2
nop
END(PROBE_DIMM)
/*******************************************************************
* input a0: deteced info on DIMM bonded to CS[1:0], 0 means no dimm
* input a1: deteced info on DIMM bonded to CS[3:2],0 means no dimm
* output v0: merged a0/a1 together, 0 means no mem
*******************************************************************/
.global MERGE_DIMM
.ent MERGE_DIMM
.set noreorder
.set mips3
MERGE_DIMM:
/* check whether CS[1:0] and CS[3:2] tied to DIMM */
bne a0,0x0,10f
nop
move v0,a1 /* no DIMM on CS[1:0], return a1 */
jr ra
10:
bne a1,0x0,12f
nop
move v0,a0 /* no DIMM on CS[3:2], return a0 */
jr ra
/* both CS[3:2] and CS[1:0] conncted to DIMM */
12:
/* check whther both DD2 or DD3 */
andi t0,a0,0x80
andi t1,a1,0x80
bne t0,t1,err
nop
beq a2, MC1_USED,1f
nop
############## first check MC0 ###########
/* check whther both Register or Unbuffered */
dli t2, 0x200000000
and t0,a0,t2
and t1,a1,t2
bne t0,t1, err
nop
/* check whther has same row */
dli t2, 0x700000
and t0,a0,t2
and t1,a1,t2
bne t0,t1, err
nop
/* check whther has same bank */
dli t2, 0x80000
and t0,a0,t2
and t1,a1,t2
bne t0,t1, err
nop
/* check whther has same col */
dli t2, 0x70000
and t0,a0,t2
and t1,a1,t2
bne t0,t1, err
nop
b 2f
nop
1:
############## now check MC1 ###########
/* check whther both Register or Unbuffered */
dli t2, 0x800000000
and t0,a0,t2
and t1,a1,t2
bne t0,t1, err
nop
/* check whther has same row */
dli t2, 0x70000000
and t0,a0,t2
and t1,a1,t2
bne t0,t1, err
nop
/* check whther has same bank */
dli t2, 0x8000000
and t0,a0,t2
and t1,a1,t2
bne t0,t1, err
nop
/* check whther has same col */
dli t2, 0x7000000
and t0,a0,t2
and t1,a1,t2
bne t0,t1, err
nop
2: ## now merge mem size together of DIMM0 and DIMM1 on the same MC ##
/* set v0 with a0 first */
move v0, a0
/* merge CS_MAP together */
// shift right 2 bits, NOTICE here assume cs[3:2] connected DIMMB
//andi t0, a0, 0xc00
//srl t0,0x2
//or v0,t0
andi t0, a1, 0xc00
or v0,t0
/* merge MIMM mem size together */
dli t3,0x1
andi t0,a0,0x70;
srl t0,0x4
addi t0,0x1c
dsll t4, t3,t0 /* t4: DIMM0 size */
andi t1,a1,0x70;
srl t1,0x4
addi t1,0x1c
dsll t5, t3,t1 /* t5: DIMM1 size */
daddu t6,t4,t5 /* total mem size of DIMM0 and DMME1 */
li t7,0x1c /* 0x1 << 0x1c = 256M */
dsrl t6, t6,t7
/* now calculate out SIZE_PER_CONTROLER */
li t4,0x0 /* t4 =log2(memsize/256M) */
4:
dsrl t6,0x1
addu t4,0x1
bne t6,0x1,4b
nop
// first clean orignal SIZE_PER_CONTROLLER
dli t5,0xffffffff8f
and v0,t5
sll t4,0x4
or v0, t4
jr ra
nop
err:
li v0,0x0;
jr ra
nop
.end MERGE_DIMM
/*******************************************************************
* input a0: deteced info on DIMM bonded to MC0, 0 means no dimm
* input a1: deteced info on DIMM bonded to MC1, 0 means no dimm
* output v0: availabe mem size from compare a0/a1, passed to L2XBAR
*******************************************************************/
LEAF(CALCULATE_MEMSZ)
andi t0,a0,0x70
andi t1,a1,0x70
srl t0,0x4
srl t1,0x4
beq t0,$0,1f
nop
beq t1,$0,2f
nop
########## calculate and set memsz #################
ble t0, t1, 3f
nop
move t0,t1
3: /* t0 used to record smller size */
li t1, 0x1
addu t0, 28+1;/* both MC0 and CM1 used */
dsll t1, t0
dsubu t1, 0x1000000 /* remain 16M according linux kernel */
move v0, t1
b 4f
nop
1: // MC0 has no DIMM, only MC1 used
########## calculate and set memsz #################
li t0, 0x1
addu t1, 28
dsll t0, t1
dsubu t0, 0x1000000 /* remain 16M according linux kernel */
move v0, t0
b 4f
nop
2: // MC1 has no DIMM, only MC0 used
########## calculate and set memsz #################
li t1, 0x1
addu t0, 28
dsll t1, t0
dsubu t1, 0x1000000 /* remain 16M according linux kernel */
move v0, t1
b 4f
nop
4:
jr ra
END(CALCULATE_MEMSZ)
/*******************************************************************
* input a0: deteced info on MC0, 0 means no mem
* input a1: deteced info on MC1, 0 means no mem
* output v0: availabe mem size from compare a0/a1, passed to L2XBAR
* The case when MC0 and MC1 not the same DDR2 or DDR3 not concerned
*******************************************************************/
LEAF(MERGE_CHANNEL)
#move v0,a0
or v0,a1,a0
/* check whter both MCO and MC1 used, set s1[3:2]=2'b00 */
andi t0,v0,0xc
bne t0,0xc,3f
nop
li t0,0xfffffff3 /* set s1[3:2]=2'b00 */
and v0,v0,t0
3:
andi t0,a0,0x70
andi t1,a1,0x70
beq t0,$0,1f
nop
beq t1,$0,2f
nop
########## calculate and merge channel memsz #################
ble t0, t1, 5f
nop
move t0,t1
5: /* t0 used to record smller size */
li t2,0xffffff8f
and v0,t2
or v0,v0,t0
b 4f
nop
1: // MC0 has no DIMM, only MC1 used
########## calculate and set memsz #################
li t2,0xffffff8f
and v0,t2
or v0,v0,t1
b 4f
nop
2: // MC1 has no DIMM, only MC0 used
########## calculate and set memsz #################
li t2,0xffffff8f
and v0,t2
or v0,v0,t0
b 4f
nop
4:
jr ra
nop
END(MERGE_CHANNEL)

51
Targets/Bonito3a780e/Bonito/loongson3_ddr2_config.S
View File

@ -6,14 +6,14 @@
#######################################################
/* Undefine the two to enable both */
/* !!!NOT USE ANYMORE !!!!! */
#define MC0_ONLY
//#define MC1_ONLY
///////#define MC0_ONLY
///////#define MC1_ONLY
/* Size of each DDR controller */
/* !!!NOT USE ANYMORE !!!!! */
//#define DDR_512
//#define DDR_1G
#define DDR_2G
//#define DDR_2G
/* Only DDR_1G CAN USE INTERLEAVE by now */
/* Interleave pattern when both controller enabled */
@ -25,7 +25,16 @@
#######################################################
/***********************************************************
s1:
| s1: |
|[35:35]| MC1_DIMM_TYPE | 1'b1 | Registered Dual |
| | | 1'b0 | Unbuffered Dual |
|[34:34]| MC1_ECC | 1'b1 | WITH DATA ECC |
| | | 1'b0 | NO DATA ECC |
|[33:33]| MC0_DIMM_TYPE | 1'b1 | Registered Dual |
| | | 1'b0 | Unbuffered Dual |
|[32:32]| MC0_ECC | 1'b1 | WITH DATA ECC |
| | | 1'b0 | NO DATA ECC |
|[31:31]| | 1'b0 | NOT USED |
|[30:28]| MC1_ROW | MC0_ROW | 15 - MC1_ROW_SIZE |
|[27:27]| MC1_EIGHT_BANK | 1'b0 | FOUR BANKS |
| | | 1'b1 | EIGHT BANKS |
@ -36,11 +45,12 @@
|[18:16]| MC0_COL_SIZE | MC0_COL | 14 - COL_SIZE |
|[15:12]| MC1_CS_MAP | | |
|[11: 8]| MC0_CS_MAP | | |
|[ 7: 7]| DIMM_TYPE | 1'b0 | DDR2 |
|[ 7: 7]| DDR_TYPE | 1'b0 | DDR2 |
| | | 1'b1 | DDR3 |
|[ 6: 4]| SIZE_PER_CONTROLLER| 3'b001 | 512MB |
| | | 3'b010 | 1G |
| | | 3'b011 | 2G |
| | | 3'b100 | 4G |
|[ 3: 2]| CONTROLLER_SELECT | 2'b00 | USE BOTH |
| | | 2'b01 | MC0_ONLY |
| | | 2'b10 | MC1_ONLY |
@ -51,16 +61,20 @@
#define GET_MC1_ONLY dli a0, 0x00000008; and a0, s1, a0;
#define GET_DDR_SIZE dli a0, 0x00000070; and a0, s1, a0;
#define GET_DDR_TYPE dli a1, 0x00000080; and a1, s1, a1;
#define GET_MC0_CS_MAP dli a1, 0x00000f00; and a1, s1, a1; dsll a1, 8
#define GET_MC1_CS_MAP dli a1, 0x0000f000; and a1, s1, a1; dsll a1, 4;
#define GET_MC0_CS_MAP dli a1, 0x00000f00; and a1, s1, a1; dsll a1, 8
#define GET_MC1_CS_MAP dli a1, 0x0000f000; and a1, s1, a1; dsll a1, 4;
#define GET_MC0_EIGHT dli a1, 0x00080000; and a1, s1, a1; dsll a1, 13;
#define GET_MC0_ROW dli a1, 0x00700000; and a1, s1, a1; dsrl a1, 12;
#define GET_MC0_COL dli a1, 0x00070000; and a1, s1, a1; dsll a1, 8;
#define GET_MC1_EIGHT dli a1, 0x08000000; and a1, s1, a1; dsll a1, 5;
#define GET_MC1_ROW dli a1, 0x70000000; and a1, s1, a1; dsrl a1, 20;
#define GET_MC1_COL dli a1, 0x07000000; and a1, s1, a1;
#define GET_MC0_ECC dli a1, 0x100000000; and a1, s1, a1; dsrl a1, 32;
#define GET_MC0_DIMM dli a1, 0x200000000; and a1, s1, a1; dsrl a1, 33;
#define GET_MC1_ECC dli a1, 0x400000000; and a1, s1, a1; dsrl a1, 34;
#define GET_MC1_DIMM dli a1, 0x800000000; and a1, s1, a1; dsrl a1, 35;
#define XBAR_CONFIG_NODE_a0(OFFSET, BASE, MASK, MMAP) \
daddi v0, t0, OFFSET; \
daddi v0, t0, OFFSET; \
dli t1, BASE; \
or t1, t1, a0; \
sd t1, 0x00(v0); \
@ -80,6 +94,7 @@
bnez a0, 3f
nop
#if 0
GET_DDR_SIZE
dli a1, 0x10
beq a1, a0, ddr_512MB
@ -121,6 +136,7 @@ ddr_1GB:
// li a0, 0x02000000
//#endif
sub msize, msize, a0
#endif
3:
@ -136,11 +152,11 @@ ddr_1GB:
#endif
#if 1
//#ifdef AUTO_DDR_CONFIG
#ifdef AUTO_DDR_CONFIG
GET_MC0_CS_MAP
beqz a1, 1f
nop
//#endif
#endif
GET_NODE_ID_a0;
XBAR_CONFIG_NODE_a0(0x10, \
0x0000000000000000, \
@ -571,25 +587,28 @@ ddr_512MB_MC1:
2:
#if 0 //print registers
//li t1, 152 ##0x72
li t1, 180 ##0x72
li t1, 151
li t2, 0xaff00000
reg_read:
ld a0, 0x0(t2)
lw a0, 0x4(t2)
bal hexserial
nop
PRINTSTR(" ")
//bal hexserial
bal hexserial64
lw a0, 0x0(t2)
bal hexserial
nop
PRINTSTR("\r\n")
addiu t2, t2, 16
bnez t1, reg_read
addiu t1, t1, -1
#endif
#if 0 /* read ddr2 registers */
/* No use in Loongson 3A */
li t0, 0xaff00000

226
Targets/Bonito3a780e/Bonito/start.S
View File

@ -1126,10 +1126,15 @@ gs_2f_v3_ddr2_cfg:
|[ 1: 0]| NODE ID | | |
***********************************************************/
TTYDBG("NODE 0 MEMORY CONFIG BEGIN\r\n")
#define MC0DIMM0_USED 0x34 /* 0x3 ---> CS[1:0]=2'b11, 4 ----> MC0 */
#define MC0DIMM1_USED 0xc4 /* 0xc ---> CS[3:2]=2'b11, 4 ----> MC0 */
#define MC1DIMM0_USED 0x38 /* 0x3 ---> CS[1:0]=2'b11, 8 ----> MC1 */
#define MC1DIMM1_USED 0xc8 /* 0xc ---> CS[3:2]=2'b11, 8 ----> MC1 */
#define MC0_USED 0x04 /* 0x4 ----> MC0 */
#define MC1_USED 0x08 /* 0x8 ----> MC1 */
#define AUTO_DDR_CONFIG
#ifdef AUTO_DDR_CONFIG
#define MC0_USED 0x4
#define MC1_USED 0x8
/* Open the SMBUS controller */
dli a1,0x90000efdfe00a090 ; #b:d:f:r=0:14:0:90 set tmp config address
@ -1138,66 +1143,171 @@ gs_2f_v3_ddr2_cfg:
/* enable the host controller */
dli a1,0x90000efdfe00a0d0 ; #b:d:f:r=0:14:0:d2 bit0=1
lw a0,0x0(a1);
lw a0,0x0(a1);
li t1, 0x10000;
or a0, t1
sw a0, 0x0(a1);
li s1,0x0
PRINTSTR("\r\nProbe MC0:JB09: ");
li a0,0xa1;
li a1,MC0_USED;
bal PROBE_DIMM;
nop;
move a0,s1;
bal hexserial;
nop;
PRINTSTR("\r\nProbe MC0:JB10: ");
li a0,0xa3;
li a1,MC0_USED;
bal PROBE_DIMM;
nop;
move a0,s1;
bal hexserial;
nop;
PRINTSTR("\r\nProbe MC1:JB11: ");
li a0,0xa5;
li a1,MC1_USED;
bal PROBE_DIMM;
nop;
move a0,s1;
bal hexserial;
nop;
PRINTSTR("\r\nProbe MC1:JB12: ");
li a0,0xa7;
li a1,MC1_USED;
bal PROBE_DIMM;
nop;
move a0,s1;
bal hexserial;
nop;
PRINTSTR("\r\n");
sw a0, 0x0(a1);
/*************************************************************
* NOTICE HERE: scan dimm of MC0 first, then dimm of MC1 *
* below define need to be CHANGED according different board *
*************************************************************/
#define MC0DIMM0 0xa1 /* SA2 = 0, SA1 = 0, SA0 = 0 <---> MAP_CS 0011 */ //CON36
#define MC0DIMM1 0xa3 /* SA2 = 0, SA1 = 0, SA0 = 1 <---> MAP_CS 1100 */ //CON37
#define MC1DIMM0 0xa5 /* SA2 = 0, SA1 = 1, SA0 = 0 <---> MAP_CS 0011 */ //CON38
#define MC1DIMM1 0xa7 /* SA2 = 0, SA1 = 1, SA0 = 1 <---> MAP_CS 1100 */ //CON39
PRINTSTR("\r\nProbing DDR SLOT: ");
PRINTSTR("\r\nProbe MC0DIMM0: ");
li s1,0x0
li v0,0x0
li a0,MC0DIMM0;
li a1,MC0DIMM0_USED;
bal PROBE_DIMM;
nop;
move s4,v0;
move a0,v0;
bal hexserial;
nop;
PRINTSTR("\r\nProbe MC0DIMM1: ");
li s1,0x0
li v0,0x0
li a0,MC0DIMM1;
li a1,MC0DIMM1_USED;
bal PROBE_DIMM;
nop;
move s5,v0
move a0,v0;
bal hexserial;
nop;
/* check whether DDR in the same MC controler has same BANK/ROW/COL/TYP */
li v0,0x0
move a0,s4
move a1,s5
li a2,MC0_USED
bal MERGE_DIMM
nop
move s6, v0 /* s6 used to save detected infomation from MC0 */
beqz v0, probe_mc1
nop
/* show value of 64 bit s1 of MC0 */
PRINTSTR("\r\nNow Merged MC0: ");
move a0,s6;
dsrl a0,32;
bal hexserial;
nop;
PRINTSTR("_");
move a0,s6;
bal hexserial;
nop;
PRINTSTR("\r\n");
probe_mc1:
PRINTSTR("\r\nProbe MC1DIMM0: ");
li s1,0x0
li v0,0x0
li a0,MC1DIMM0;
li a1,MC1DIMM0_USED;
bal PROBE_DIMM;
nop;
move s4,v0;
move a0,v0;
bal hexserial;
nop;
PRINTSTR("\r\nProbe MC1DIMM1: ");
li s1,0x0
li v0,0x0
li a0,MC1DIMM1;
li a1,MC1DIMM1_USED;
bal PROBE_DIMM;
nop;
move s5,v0
move a0,v0;
bal hexserial;
nop;
/* now check whether DDR in the same MC controler has same BANK/ROW/COL/TYPE */
li v0,0x0
move a0,s4
move a1,s5
li a2,MC1_USED
bal MERGE_DIMM
nop
move s7, v0
/* show value of 64 bit s1 of MC1 */
PRINTSTR("\r\nNow Merged MC1: ");
move a0,s7;
dsrl a0,32;
bal hexserial;
nop;
PRINTSTR("_");
move a0,s7;
bal hexserial;
nop;
PRINTSTR("\r\n");
#else
li s1, 0x1c1c33a4
bal tgt_testchar
la v0, 0
nop
beqz v0, ddr_config_entry
nop
li s6, 0x14140c24 /* s6 used to save detected infomation from MC0 */
li s7, 0x14140c24 /* s7 used to save detected infomation from MC1 */
#endif
//PRINTSTR("[ 6: 4]: SIZE_PER_CONTROLLER\r\n | 3'b001: 512MB |\r\n | 3'b010: 1G |\r\n | 3'b011: 2G |\r\n[ 3: 2]:CONTROLLER_SELECT\r\n | 2'b00 : USE BOTH |\r\n | 2'b01 : MC0_ONLY |\r\n | 2'b10 : MC1_ONLY |\r\n[ 1: 0]: NODE ID\r\n")
li t6, 0x00
bal inputaddress #input value stored in v0
nop
move s1, v0 #store v0 to s1
/* calculate memory size */
move a0,s6
move a1,s7
bal CALCULATE_MEMSZ
nop
move msize,v0
PRINTSTR("\r\nTotal Memory Size: ");
/* show value of 64 bit memsize */
move a0,msize;
dsrl a0,32;
bal hexserial;
nop;
PRINTSTR("_");
move a0,msize;
bal hexserial;
nop;
PRINTSTR("\r\n");
PRINTSTR("\r\nLast S1: ");
/* merge mem deteced info together */
li v0,0x0
move a0,s6
move a1,s7
bal MERGE_CHANNEL
nop
move s1,v0
/* show value of 64 bit s1 of MC0 and MC1 */
move a0,s1;
dsrl a0,32;
bal hexserial;
nop;
PRINTSTR("_");
move a0,s1;
bal hexserial;
nop;
PRINTSTR("\r\n");
//#define DEBUG_DDR
#ifdef DEBUG_DDR
bal tgt_testchar
nop
beqz v0, ddr_config_entry
nop
//PRINTSTR("[ 6: 4]: SIZE_PER_CONTROLLER\r\n | 3'b001: 512MB |\r\n | 3'b010: 1G |\r\n | 3'b011: 2G |\r\n[ 3: 2]: CONTROLLER_SELECT\r\n | 2'b00 : USE BOTH |\r\n | 2'b01 : MC0_ONLY |\r\n | 2'b10 : MC1_ONLY |\r\n[ 1: 0]: NODE ID\r\n")
li t6, 0x00
bal inputaddress #input value stored in v0
nop
move s1, v0 #store v0 to s1
ddr_config_entry:
#endif
#include "loongson3_ddr2_config.S"
@ -1847,7 +1957,7 @@ ddr_config_entry:
li t1,128
# addiu a2,a0,3
sb t1,3(a0)
li t1,0x12 # divider, highest possible baud rate
li t1,0x0e # divider, highest possible baud rate
sb t1,0(a0)
li t1,0x0 # divider, highest possible baud rate
sb t1,1(a0)

93
pmon/cmds/install.c
View File

@ -0,0 +1,93 @@
/* $Id: memcmds.c,v 1.1.1.1 2006/09/14 01:59:08 root Exp $ */
/*
* Copyright (c) 2000-2001 Opsycon AB (www.opsycon.se)
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Opsycon AB, Sweden.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
*/
#include <stdio.h>
#include <termio.h>
#include <string.h>
#include <setjmp.h>
#include <sys/endian.h>
#include <ctype.h>
#include <unistd.h>
#include <stdlib.h>
#include <fcntl.h>
#ifdef _KERNEL
#undef _KERNEL
#include <sys/ioctl.h>
#define _KERNEL
#else
#include <sys/ioctl.h>
#endif
#include <pmon.h>
//int cmd_install __P((void));
void cmd_cdinstall(void)
{
char buf[100];
sprintf(buf, "load /dev/fs/iso9660@cd0/vmlinuxb");
//buf = "load /dev/fs/iso9660@cd0/vmlinuxb";
do_cmd(buf);
sprintf(buf, "g console=tty rdinit=/sbin/init video=vfb:1");
do_cmd(buf);
}
void cmd_usbinstall(void)
{
char buf[100];
sprintf(buf, "load /dev/fs/ext2@usb0/vmlinuxboot");
do_cmd(buf);
sprintf(buf, "g console=tty rdinit=/sbin/init video=vfb:1");
do_cmd(buf);
}
static const Cmd Cmds[] =
{
{"Misc"},
{"cdinstall", "",0,"install Linux system from CD-ROM", cmd_cdinstall, 1, 99, 0},
{"usbinstall", "",0,"install Linux system from USB DISK", cmd_usbinstall, 1, 99, 0},
{0, 0}
};
static void init_cmd __P((void)) __attribute__ ((constructor));
static void
init_cmd()
{
cmdlist_expand(Cmds, 1);
}
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