From d1c30cf00e88787eebe887f3279494c41c2996b1 Mon Sep 17 00:00:00 2001 From: Chong Qiao Date: Fri, 21 Jan 2022 11:48:53 +0800 Subject: [PATCH] add signal test. Change-Id: Iee8f92f15ed0928cbb25c06621d90a3aa2cd33a5 Signed-off-by: Chong Qiao --- examples/signal/Makefile | 28 +++++ examples/signal/ld.script | 85 ++++++++++++++ examples/signal/raw.S | 59 ++++++++++ examples/signal/signal_test.c | 215 ++++++++++++++++++++++++++++++++++ 4 files changed, 387 insertions(+) create mode 100644 examples/signal/Makefile create mode 100644 examples/signal/ld.script create mode 100644 examples/signal/raw.S create mode 100644 examples/signal/signal_test.c diff --git a/examples/signal/Makefile b/examples/signal/Makefile new file mode 100644 index 00000000..bac53c6a --- /dev/null +++ b/examples/signal/Makefile @@ -0,0 +1,28 @@ +# +# Makefile to build hello.c +# + +CROSS_COMPILE =/opt/gcc-4.4-gnu/bin/mipsel-linux- + +# +# Include the make variables (CC, etc...) +# + +AS = $(CROSS_COMPILE)as +LD = $(CROSS_COMPILE)ld +CC = $(CROSS_COMPILE)gcc +CPP = $(CC) -E +AR = $(CROSS_COMPILE)ar +NM = $(CROSS_COMPILE)nm +STRIP = $(CROSS_COMPILE)strip +OBJCOPY = $(CROSS_COMPILE)objcopy +OBJDUMP = $(CROSS_COMPILE)objdump +SIZE = $(CROSS_COMPILE)size + +%.o: %.c + ${CC} -I../../sys/arch/mips/include/ -G 0 -O2 -fno-pic -mno-abicalls -fno-builtin -nostdinc -mips3 -c -o $@ $< +%.o: %.S + ${CC} -I../../sys/arch/mips/include/ -G 0 -O2 -fno-pic -mno-abicalls -fno-builtin -nostdinc -mips3 -c -o $@ $< + +signal_test: signal_test.o raw.o + ${LD} -Ttext=0xffffffff80200000 -nostdlib -e main -m elf32ltsmip -T ld.script -static -o $@ $^ diff --git a/examples/signal/ld.script b/examples/signal/ld.script new file mode 100644 index 00000000..cdc1e7ad --- /dev/null +++ b/examples/signal/ld.script @@ -0,0 +1,85 @@ +ENTRY(_start) +SECTIONS +{ + . = 0x80200000; + . = ALIGN(8); + _text = .; + .text : + { + *(.starttext) + *(.startrodata) + *(.text) + *(.text.*) + } + _etext = .; + + . = ALIGN(8); + .rodata : { *(.rodata) } + + . = ALIGN(8); + .data : { + _fdata = . ; + *(.data) + } + + .ctors : + { + __CTOR_LIST__ = .; + *(.ctors) + __CTOR_END__ = .; + } + .dtors : + { + __DTOR_LIST__ = .; + *(.dtors) + __DTOR_END__ = .; + } + + .polls : + { + __POLL_LIST__ = .; + *(.polls) + __POLL_END__ = .; + } + + .timers : + { + __TIMER_LIST__ = .; + *(.timers) + __TIMER_END__ = .; + } + + . = .; + _gp = ALIGN(16) + 0x7ff0; + + .got : { + __got_start = .; + *(.got) + __got_end = .; + } + + .sdata : { *(.sdata) } + + .u_boot_cmd : { + __u_boot_cmd_start = .; + *(.u_boot_cmd) + __u_boot_cmd_end = .; + } + + .myconfig : { + __u_boot_myconfig_start = .; + *(.myconfig) + __u_boot_myconfig_end = .; + } + + uboot_end_data = .; + _edata = .; + num_got_entries = (__got_end - __got_start) >> 2; + + . = ALIGN(8); + .sbss (NOLOAD) : { *(.sbss) *(.scommon) } + .bss (NOLOAD) : { *(.bss) *(COMMON) . = ALIGN(8); } + uboot_end = .; + _end = .; + _heap = . ; +} diff --git a/examples/signal/raw.S b/examples/signal/raw.S new file mode 100644 index 00000000..342d78bd --- /dev/null +++ b/examples/signal/raw.S @@ -0,0 +1,59 @@ +#include +#include "mipsregs.h" + /* u64 __raw__readw(u64 addr) + * a0, a1 hold low 32 and high 32 + * v0 hold 32 of ret + */ + .text + .global __raw__readw + .ent __raw__readw + .set mips3 +__raw__readw: + + dsll32 a1, a1, 0 + dsll32 a0, a0, 0 + dsrl32 a0, a0, 0 + or a0, a1, a0 + + lw v0, 0(a0) +// dsra32 v1, v0, 0 + jr ra + sll v0, v0, 0 + .set mips0 + .end __raw__readw + + /* u64 __raw__writeq(u64 addr, u64 val) + * a0, a1 hold low 32 and high 32 of addr, + * a2, a2 hold low 32 and high 32 of val, + * v0, v1 hold low 32 and high 32 of ret + */ + + + /* u64 __raw__writew(u64 addr, u32 val) + * a0, a1 hold low 32 and high 32 of addr, + * a2 hold 32 of val, + * v0 hold 32 of ret + */ + + .global __raw__writew + .set mips3 + .ent __raw__writew +__raw__writew: + + dsll32 a1, a1, 0 + dsll32 a0, a0, 0 + dsrl32 a0, a0, 0 + or a0, a1, a0 + +// dsll32 a3, a3, 0 + dsll32 a2, a2, 0 + dsrl32 a2, a2, 0 +// or a2, a2, a3 + + sw a2, 0(a0) + lw v0, 0(a0) +// dsra32 v1, v0, 0 + jr ra + sll v0, v0, 0 + .set mips0 + .end __raw__writew diff --git a/examples/signal/signal_test.c b/examples/signal/signal_test.c new file mode 100644 index 00000000..1b519b41 --- /dev/null +++ b/examples/signal/signal_test.c @@ -0,0 +1,215 @@ +/* $Id: fan.c,v 1.1.1.1 2006/09/14 01:59:08 xqch Exp $ */ +/* + * Copyright (c) 2001 Opsycon AB (www.opsycon.se) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Opsycon AB, Sweden. + * 4. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ + + +typedef long long off_t; + +struct callvectors { + int (*open) (char *, int, int); + int (*close) (int); + int (*read) (int, void *, int); + int (*write) (int, void *, int); + off_t (*lseek) (int, off_t, int); + int (*printf) (const char *, ...); + void (*cacheflush) (void); + char *(*gets) (char *); +}; + +struct callvectors *callvec; + +#define printf (*callvec->printf) +#define gets (*callvec->gets) + +typedef unsigned int u32; +typedef unsigned long long u64; + +extern u64 __raw__writeq(u64 addr, u64 val); +extern u64 __raw__readq(u64 q); + +extern u32 __raw__writew(u64 addr, u32 val); +extern u32 __raw__readw(u64 q); + +int atoi(char *s) +{ + return s[0] - '0'; +} + +unsigned char +cmd_pcietest(ac, av) + int ac; + char *av[]; +{ + unsigned int port, gen; + unsigned int base,test_mode; + unsigned int pcie_clock_source; + unsigned int port_num; + unsigned int dev_num; + unsigned long long header; + unsigned long long bar0; + unsigned int bar0_low; + unsigned int bar0_high; + if ((ac != 3) && (ac != 4)){ + printf("usage: pcietest [test mode for gen2]\n"); + printf("port num: 0 -> f0 x4\n"); + printf("port num: 1 -> f1 x4\n"); + printf("port num: 2 -> g0 x8\n"); + printf("port num: 3 -> g1 x8\n"); + printf("port num: 4 -> h x8\n"); + printf("gen2_test_mode: 1 ->0xf052, -3.5db De-emphasis \n"); + printf("gen2_test_mode: 2 ->0xf012, -6db De-emphasis \n"); + printf("gen2_test_mode: 3 ->0xf452, -3.5db De-emphasis, modified compliance \n"); + printf("gen2_test_mode: 4 ->0xf412, -6db De-emphasis, modified compliance \n"); + printf("gen2_test_mode: 5 ->0xfc52, -3.5db De-emphasis, modified compliance, compliance SOS \n"); + printf("gen2_test_mode: 6 ->0xfc12, -6db De-emphasis, modified compliance, compliance \n"); + printf("For example0:pcietest 0 1 \n"); + printf("For example1:pcietest 0 2 1\n"); + return 0; + } + + port_num = (unsigned int)atoi(av[1]); + printf("pcie port = 0x%x\n",port_num); + + dev_num = port_num == 0 ? 9 : + port_num == 1 ? 13 : + port_num == 2 ? 15 : + port_num == 3 ? 17 : + port_num == 4 ? 19 : + 9; + + header = 0x90000efe00000000ULL | (dev_num << 11); + + gen = (unsigned int)atoi(av[2]); + + if (gen == 2) { + test_mode = (unsigned int)atoi(av[3]); + +// pt32(header + 0x7c) = 0x533c42;// the low 4 bit must be 2. + __raw__writew(header + 0x7c, 0x533c42); + + } + +// pt64(header + (0x8 << 24) + 0x0c) = 0x2040f; + __raw__writew(header + (0x8<<24) + 0x0c, 0x2040f); + +// unsigned int conf_base = 0xb0010000; +// unsigned int f0_base = conf_base + 0x588; +// //set to x1 mode +// pt32(f0_base) &= 0x4000000; +// pt32(f0_base) |= 0x8000000; + + //TODO PHY cfg, override GEN mode + //for (port = 0;port < 4;port++) { + // pt8(base | (port * 0x100) | 0x11) = 0x21; + // pt8(base | (port * 0x100) | 0x10) = 0xb; + //} + + //if (gen == 2) { + // for (port = 0;port < 4;port++) + // pt8(base | (port * 0x100) | 0x12) = 0xa; + //} + + + bar0_low = (__raw__readw(header + 0x10) & 0xffffffff0ULL); + bar0_high = (__raw__readw(header + 0x14)); + bar0 = ((long long)bar0_high << 32 | bar0_low) + 0x90000e0000000000ULL; +// printf("pcie header = 0x%llx\n",header); +// printf("pcie bar0_low = 0x%x\n",bar0_low); +// printf("pcie bar0_high = 0x%x\n",bar0_high); +// printf("pcie bar0 = 0x%llx\n",bar0); +// pt64(bar0) = 0xff204c; + __raw__writew(bar0, 0xff204c); + + + if (gen == 0x1) { + __raw__writew(header + 0xa0, 0xfc51); + } else if (gen == 0x2){ + switch (test_mode) { + case 1: + __raw__writew(header + 0xa0, 0xf052); + break; + case 2: + __raw__writew(header + 0xa0, 0xf012); + break; + case 3: + __raw__writew(header + 0xa0, 0xf452); + break; + case 4: + __raw__writew(header + 0xa0, 0xf412); + break; + case 5: + __raw__writew(header + 0xa0, 0xfc52); + break; + case 6: + __raw__writew(header + 0xa0, 0xfc12); + break; + default: + break; + } + } + + __raw__writew(header + (0x7 << 24) + 0x08, 0x7028004); + + return(1); +} + +char * +strchr(const char *p, int c) +{ + if (!p) + return (0); + + for (; *p; p++) + if (*p == c) + return ((char *)p); + return (0); +} + +void __gccmain(void); +void __gccmain(void){} +int +main(int argc, char **argv, char **env, struct callvectors *cv) +{ + + int i, t; + callvec = cv; + for (i = 1, t = 0; i < argc; i++) { + if (strchr(argv[i], '=')) { + t++; + } + } + argc -= t; + for (i =0; i < argc; i++) + printf("%d: %s\n", i, argv[i]); + + cmd_pcietest(argc, argv); + return(0); +}