1. Organize the MC initialization related code for ~3A5/~3B4/2G.

For the same MC, extract the public code for configure MC parameters to lsmcd3_config_param.S.
For different chips, use different mc_init file.
~3A5/2GQ: ddr_config.S
~3B4    : 3B_ddr_config.S
2G      : 2G_ddr_config.S
2. move code of configure MC frequency by software for ~3A5 to subrutine.
3. Modify code to support auto arb_level when change the DDR frequency by software configuration.

Change-Id: I9a1d2b08aa4f282523dfb3b62d17e2c0291b6a17

Targets/Bonito3a780e/Bonito/start.S

@@ -391,7 +391,28 @@ gs_2f_v3_ddr2_cfg:
 	WatchDog_Close;
 
 ##########################################
+//configure DDR freq by software
+#if 1
+    li      t5, 0x17
+#if 0
+    PRINTSTR("Please input DDR frequency SELLECT[4:0](default: 0x1e;0x1f: skip software setting):\r\n");
+    dli     t6, 0x00
+    bal     inputaddress #input value stored in v0
+    nop
+    dli     t6, 0x1f
+    and     v0, v0, t6
+    beq     v0, t6, 88f
+    nop
+    move    t5, v0
+#endif
 
+    TTYDBG  ("\r\nSet DDR frequency by software\r\n")
+    move    a2, $0
+    bal     config_mc_frequency
+    nop
+
+88:
+#endif
 
 	PRINTSTR("Init TLB...\r\n")
 	bal     tlb_init
@@ -527,7 +548,7 @@ wait_l2_ok:
 	nop
 	and     v0, v0, 0xf
 	dli     a1, 0x1
-	bgt     v0, a1, 2f
+	bgt     v0, a1, 3f
 	nop
 
 	dli     s1, 0x0010000080000000  //NODE 0, start from 0x80000000
@@ -562,6 +583,7 @@ wait_l2_ok:
 	PRINTSTR("  Error found!!\r\n")
 2:
 
+3:
 #endif
 ##########################################
 

pmon/arch/mips/mm/ddr_config_define.h

@@ -56,7 +56,8 @@ DIMM infor:
 |       |                    | 1'b0    | Unbuffered DIMM   |
 |[27:27]| DIMM_WIDTH         | 1'b1    | REDUC--32bits     |
 |       |                    | 1'b0    | NORMAL--64 bits   |
-|[26:24]| SDRAM_ROW_SIZE     | MC_ROW  | 15 - ROW_SIZE     |
+|[26:24]| SDRAM_ROW_SIZE     | MC_ROW  | 15 - ROW_SIZE(for lsmcd3)  |
+|                                        16 - ROW_SIZE(for lsmc)    |
 |[23:23]| SDRAM_EIGHT_BANK   | 1'b0    | FOUR  BANKS       |
 |       |                    | 1'b1    | EIGHT BANKS       |
 |[22:22]| ADDR_MIRROR        | 1'b1    | ADDR MIRROR       |
@@ -90,8 +91,12 @@ temparary used in PROBE_DIMM
 #define CHIP_CONFIG_ADDR        0x900000001fe00180
 #define CHIP_CONFIG_BASE_ADDR   0x900000001fe00180
 #define CHIP_SAMPLE_BASE_ADDR   0x900000001fe00190
+#define DDR_CLKSEL_EN_OFFSET        3
 #define DDR_CLKSEL_OFFSET           37
 #define DDR_CLKSEL_MASK             0x1F
+#define DDR_CLKSEL_WIDTH            5
+#define DDR_CLKSEL_SOFT_OFFSET      24
+#define DDR_CLKSEL_SOFT_MASK        0x1F
 #ifdef  LSMC_2
 #define DDR_CONFIG_DISABLE_OFFSET   4
 #else
@@ -106,8 +111,12 @@ temparary used in PROBE_DIMM
 #define CHIP_CONFIG_ADDR        0x900000001fe00180
 #define CHIP_CONFIG_BASE_ADDR   0x900000001fe00180
 #define CHIP_SAMPLE_BASE_ADDR   0x900000001fe00190
+#define DDR_CLKSEL_EN_OFFSET        3
 #define DDR_CLKSEL_OFFSET           37
 #define DDR_CLKSEL_MASK             0x1F
+#define DDR_CLKSEL_WIDTH            5
+#define DDR_CLKSEL_SOFT_OFFSET      40
+#define DDR_CLKSEL_SOFT_MASK        0x1F
 #define DDR_CONFIG_DISABLE_OFFSET   4
 #define ARB_TEMP_L2WINDOW_OFFSET    0x20
 #else
@@ -118,8 +127,13 @@ temparary used in PROBE_DIMM
 #define CHIP_CONFIG_ADDR        0x900000001fd00200
 #define CHIP_CONFIG_BASE_ADDR   0x900000001fd00200
 #define CHIP_SAMPLE_BASE_ADDR   0x900000001fd00210
+#define LS2H_CLOCK_CTRL0_ADDR   0x900000001fd00220
+#define DDR_CLKSEL_EN_OFFSET        25
 #define DDR_CLKSEL_OFFSET           23
-#define DDR_CLKSEL_MASK             0x07
+#define DDR_CLKSEL_MASK             0x3
+#define DDR_CLKSEL_WIDTH            2
+#define DDR_CLKSEL_SOFT_OFFSET      16
+#define DDR_CLKSEL_SOFT_MASK        0xfffa
 #define DDR_CONFIG_DISABLE_OFFSET   13
 #define ARB_TEMP_L2WINDOW_OFFSET    0x38
 #else //default current set as loosong3A3
@@ -129,8 +143,12 @@ temparary used in PROBE_DIMM
 #define CHIP_CONFIG_ADDR        0x900000001fe00180
 #define CHIP_CONFIG_BASE_ADDR   0x900000001fe00180
 #define CHIP_SAMPLE_BASE_ADDR   0x900000001fe00190
+#define DDR_CLKSEL_EN_OFFSET        3
 #define DDR_CLKSEL_OFFSET           37
 #define DDR_CLKSEL_MASK             0x1F
+#define DDR_CLKSEL_WIDTH            5
+#define DDR_CLKSEL_SOFT_OFFSET      24
+#define DDR_CLKSEL_SOFT_MASK        0x1F
 #define DDR_CONFIG_DISABLE_OFFSET   8
 #define ARB_TEMP_L2WINDOW_OFFSET    0x20
 #define NO_L2XBAR_CONFIGURE

pmon/arch/mips/mm/loongson2G_ddr2_config.S

@@ -27,21 +27,7 @@
 0. s1 reset code
 **************************/
 #ifdef  AUTO_ARB_LEVEL
-//store memory system info into s3(include frequency and dimm i2c addr)
+//store memory system info into s3(dimm i2c addr)
-#ifdef  CHECK_ARB_LEVEL_FREQ
-    dli     t0, CHIP_SAMPLE_BASE_ADDR
-    GET_NODE_ID_a0
-    or      t0, t0, a0
-    ld      a0, 0x0(t0)
-    dsrl    a0, a0, DDR_CLKSEL_OFFSET
-    and     a0, a0, DDR_CLKSEL_MASK
-    dsll    a0, a0, 40
-    GET_NODE_ID_a1
-    dsll    a1, a1, 3
-    dsll    a0, a0, a1
-    or      s3, s3, a0
-#endif
-
 #ifdef  CHECK_ARB_LEVEL_DIMM
     //store dimm i2c addr info to s3
     dsrl    a2, s1, 16
@@ -214,25 +200,8 @@ t0,t2 shouldn't be changed to the end of this file.
     or      t2, t2, a0
     or      t0, t0, a0
 
-//init MC1 will damage MC0 s1 info
+//config MC0
-//config MC0 if not define MC1_ONLY
-//-------------------------------------
     dli     t3, 0x0
-#ifndef  DISABLE_DIMM_ECC
-    //Enable MC read buffer for ECC Initial
-    GET_DIMM_ECC
-    beqz    a1, 8f
-    nop
-    TTYDBG("Enable MC read buffer\r\n")
-    lw      a1, 0x4(t2)
-    li      a0, 0x8
-    sll     a0, a0, t3
-    not     a0, a0
-    and     a1, a1, a0
-    sw      a1, 0x4(t2)
-    sync
-8:
-#endif
 
 #ifdef  AUTO_ARB_LEVEL
     bal     SET_AUTO_ARB_LEVEL_MARK
@@ -242,20 +211,6 @@ t0,t2 shouldn't be changed to the end of this file.
     bal     mc_init
     nop
 
-#ifndef  DISABLE_DIMM_ECC
-    //Disable MC read buffer after ECC Initial
-    GET_DIMM_ECC
-    beqz    a1, 8f
-    nop
-    TTYDBG("Disable MC read buffer\r\n")
-    lw      a1, 0x4(t2)
-    li      a0, 0x8
-    sll     a0, a0, t3
-    or      a1, a1, a0
-    sw      a1, 0x4(t2)
-    sync
-8:
-#endif
     PRINTSTR("\r\nMC0 Config DONE\r\n")
 /*****************************
  3. set msize for this NODE(if the memsize is supported)

pmon/arch/mips/mm/loongson3A3_ddr_param.lvled.S

@@ -11,6 +11,8 @@ c0_mc0_dimm0_info:
 c0_mc0_dimm1_info:
 .dword  0xffffffffffffffff
 .dword  0xffffffffffffffff
+c0_mc0_ddr_clksel:
+.dword  0xffffffffffffffff
 ddr2_reg_data_mc0_leveled:
 ddr2_reg_data_leveled:
 N0_Leveled_MC0_CTL_000 : .dword 0x0000010000000100
@@ -312,6 +314,8 @@ c0_mc1_dimm0_info:
 c0_mc1_dimm1_info:
 .dword  0xffffffffffffffff
 .dword  0xffffffffffffffff
+c0_mc1_ddr_clksel:
+.dword  0xffffffffffffffff
 ddr2_reg_data_mc1_leveled:
 n1_ddr2_reg_data_leveled:
 N1_Leveled_MC0_CTL_000 : .dword 0x0000010000000100

pmon/arch/mips/mm/loongson3A3_ddr_param_c1.lvled.S

@@ -11,6 +11,8 @@ c1_mc0_dimm0_info:
 c1_mc0_dimm1_info:
 .dword  0xffffffffffffffff
 .dword  0xffffffffffffffff
+c1_mc0_ddr_clksel:
+.dword  0xffffffffffffffff
 n1_ddr2_reg_data_mc0_leveled:
 n2_ddr2_reg_data_leveled:
 N2_Leveled_MC0_CTL_000 : .dword 0x0000010000000100
@@ -312,6 +314,8 @@ c1_mc1_dimm0_info:
 c1_mc1_dimm1_info:
 .dword  0xffffffffffffffff
 .dword  0xffffffffffffffff
+c1_mc1_ddr_clksel:
+.dword  0xffffffffffffffff
 n1_ddr2_reg_data_mc1_leveled:
 n3_ddr2_reg_data_leveled:
 N3_Leveled_MC0_CTL_000 : .dword 0x0000010000000100

pmon/arch/mips/mm/loongson3B_ddr_config.S

@@ -26,25 +26,7 @@
 0. s1 reset code
 **************************/
 #ifdef  AUTO_ARB_LEVEL
-//store memory system info into s3(include frequency and dimm i2c addr)
+//store memory system info into s3(dimm i2c addr)
-#ifdef  CHECK_ARB_LEVEL_FREQ
-    //note: for ODD node id use EVEN node id for chip sample addr
-    dli     t0, CHIP_SAMPLE_BASE_ADDR
-    GET_NODE_ID_a1
-    and     a1, a1, 0x2
-    dsll    a0, a1, 44
-    or      t0, t0, a0
-    ld      a0, 0x0(t0)
-    dsrl    a0, a0, DDR_CLKSEL_OFFSET
-    and     a0, a0, DDR_CLKSEL_MASK
-    dsll    a0, a0, 40
-    GET_NODE_ID_a1
-    dsrl    a1, a1, 1
-    dsll    a1, a1, 3
-    dsll    a0, a0, a1
-    or      s3, s3, a0
-#endif
-
 #ifdef  CHECK_ARB_LEVEL_DIMM
     //store dimm i2c addr info to s3
     dsrl    a2, s1, 16
@@ -220,36 +202,8 @@ t0,t2 shouldn't be changed to the end of this file.
 
 #if 1   //necessary
     TTYDBG("Disable DDR buffer cpu\r\n")
-    GET_NODE_ID_a1
+    bal     disable_mc_read_buffer
-    and     a1, a1, 0x1 //a1 == 0(even NODE) or 1(odd NODE)
-    dsll    a2, a1, 2   //a2 == 0(even NODE) or 4(odd NODE)
-    daddu   a1, a2, a1  //a1 == 0(even NODE) or 5(odd NODE)
-    lw      a2, 0x0(t2)
-    li      a0, 0x20    //bit[5]--MC0 DDR buffer cpu
-    sll     a0, a0, a1  //sll 0 or 5
-    not     a0, a0
-    and     a2, a2, a0
-    sw      a2, 0x0(t2)
-#endif
-
-#ifndef  DISABLE_DIMM_ECC
-    //Enable MC read buffer for ECC Initial
-    GET_DIMM_ECC
-    beqz    a1, 8f
     nop
-    TTYDBG("Enable MC read buffer\r\n")
-    GET_NODE_ID_a1
-    and     a1, a1, 0x1 //a1 == 0(even NODE) or 1(odd NODE)
-    dsll    a2, a1, 2   //a2 == 0(even NODE) or 4(odd NODE)
-    daddu   a1, a2, a1  //a1 == 0(even NODE) or 5(odd NODE)
-    lw      a2, 0x0(t2)
-    li      a0, 0x40    //bit[6]--MC0_read_buffer_bypass
-    sll     a0, a0, a1  //sll 0 or 5
-    not     a0, a0
-    and     a2, a2, a0
-    sw      a2, 0x0(t2)
-    sync
-8:
 #endif
 
 #ifdef  AUTO_ARB_LEVEL
@@ -260,24 +214,6 @@ t0,t2 shouldn't be changed to the end of this file.
     bal     mc_init
     nop
 
-#ifndef  DISABLE_DIMM_ECC
-    //Disable MC read buffer after ECC Initial
-    GET_DIMM_ECC
-    beqz    a1, 8f
-    nop
-    TTYDBG("Disable MC read buffer\r\n")
-    GET_NODE_ID_a1
-    and     a1, a1, 0x1 //a1 == 0(even NODE) or 1(odd NODE)
-    dsll    a2, a1, 2   //a2 == 0(even NODE) or 4(odd NODE)
-    daddu   a1, a2, a1  //a1 == 0(even NODE) or 5(odd NODE)
-    lw      a2, 0x0(t2)
-    li      a0, 0x40    //bit[6]--MC0_read_buffer_bypass
-    sll     a0, a0, a1  //sll 0 or 5
-    or      a2, a2, a0
-    sw      a2, 0x0(t2)
-    sync
-8:
-#endif
     PRINTSTR("\r\nMC0 Config DONE\r\n")
 /*****************************
  3. set msize for this NODE

pmon/arch/mips/mm/loongson3_ddr2_config.S

@@ -41,21 +41,7 @@
 #endif
 
 #ifdef  AUTO_ARB_LEVEL
-//store memory system info into s3(include frequency and dimm i2c addr)
+//store memory system info into s3(dimm i2c addr)
-#ifdef  CHECK_ARB_LEVEL_FREQ
-    dli     t0, CHIP_SAMPLE_BASE_ADDR
-    GET_NODE_ID_a0
-    or      t0, t0, a0
-    ld      a0, 0x0(t0)
-    dsrl    a0, a0, DDR_CLKSEL_OFFSET
-    and     a0, a0, DDR_CLKSEL_MASK
-    dsll    a0, a0, 40
-    GET_NODE_ID_a1
-    dsll    a1, a1, 3
-    dsll    a0, a0, a1
-    or      s3, s3, a0
-#endif
-
 #ifdef  CHECK_ARB_LEVEL_DIMM
     //store dimm i2c addr info to s3
     dsrl    a2, s1, 16
@@ -307,10 +293,8 @@ t0,t2 shouldn't be changed to the end of this file.
 //This seems better for the spec2000
 //if we enable ECC, this bit will be reset
     PRINTSTR("Disable read buffer\r\n")
-    lw      a1, 0x4(t2)
+    bal     disable_mc_read_buffer
-    li      a0, 0x18
+    nop
-    or      a1, a1, a0
-    sw      a1, 0x4(t2)
 #endif
 
 //init MC1 will damage MC0 s1 info
@@ -322,22 +306,6 @@ t0,t2 shouldn't be changed to the end of this file.
     nop
 
     dli     t3, 0x0
-#ifndef  DISABLE_DIMM_ECC
-    //Enable MC read buffer for ECC Initial
-    GET_DIMM_ECC
-    beqz    a1, 8f
-    nop
-    TTYDBG("Enable MC read buffer\r\n")
-    lw      a1, 0x4(t2)
-    li      a0, 0x8
-    sll     a0, a0, t3
-    not     a0, a0
-    and     a1, a1, a0
-    sw      a1, 0x4(t2)
-    sync
-8:
-#endif
-
 #ifdef  AUTO_ARB_LEVEL
     bal     SET_AUTO_ARB_LEVEL_MARK
     nop
@@ -346,20 +314,6 @@ t0,t2 shouldn't be changed to the end of this file.
     bal     mc_init
     nop
 
-#ifndef  DISABLE_DIMM_ECC
-    //Disable MC read buffer after ECC Initial
-    GET_DIMM_ECC
-    beqz    a1, 8f
-    nop
-    TTYDBG("Disable MC read buffer\r\n")
-    lw      a1, 0x4(t2)
-    li      a0, 0x8
-    sll     a0, a0, t3
-    or      a1, a1, a0
-    sw      a1, 0x4(t2)
-    sync
-8:
-#endif
     PRINTSTR("\r\nMC0 Config DONE\r\n")
 //-------------------------------------
 //config MC1 if not define MC0_ONLY
@@ -378,22 +332,6 @@ t0,t2 shouldn't be changed to the end of this file.
     and     s1, s1, a1
     or      s1, s1, t5
 
-#ifndef  DISABLE_DIMM_ECC
-    //Enable MC read buffer for ECC Initial
-    GET_DIMM_ECC
-    beqz    a1, 8f
-    nop
-    TTYDBG("Enable MC read buffer\r\n")
-    lw      a1, 0x4(t2)
-    li      a0, 0x8
-    sll     a0, a0, t3
-    not     a0, a0
-    and     a1, a1, a0
-    sw      a1, 0x4(t2)
-    sync
-8:
-#endif
-
 #ifdef  AUTO_ARB_LEVEL
     bal     SET_AUTO_ARB_LEVEL_MARK
     nop
@@ -402,20 +340,6 @@ t0,t2 shouldn't be changed to the end of this file.
     bal     mc_init
     nop
 
-#ifndef  DISABLE_DIMM_ECC
-    //Disable MC read buffer after ECC Initial
-    GET_DIMM_ECC
-    beqz    a1, 8f
-    nop
-    TTYDBG("Disable MC read buffer\r\n")
-    lw      a1, 0x4(t2)
-    li      a0, 0x8
-    sll     a0, a0, t3
-    or      a1, a1, a0
-    sw      a1, 0x4(t2)
-    sync
-8:
-#endif
     TTYDBG("\r\nMC1 Config DONE\r\n")
 //-------------------------------------
 12:

pmon/arch/mips/mm/loongson3a2h_ddr_config.S

@@ -39,21 +39,7 @@
 #endif
 
 #ifdef  AUTO_ARB_LEVEL
-//store memory system info into s3(include frequency and dimm i2c addr)
+//store memory system info into s3(dimm i2c addr)
-#ifdef  CHECK_ARB_LEVEL_FREQ
-    dli     t0, CHIP_SAMPLE_BASE_ADDR
-    GET_NODE_ID_a0
-    or      t0, t0, a0
-    ld      a0, 0x0(t0)
-    dsrl    a0, a0, DDR_CLKSEL_OFFSET
-    and     a0, a0, DDR_CLKSEL_MASK
-    dsll    a0, a0, 40
-    GET_NODE_ID_a1
-    dsll    a1, a1, 3
-    dsll    a0, a0, a1
-    or      s3, s3, a0
-#endif
-
 #ifdef  CHECK_ARB_LEVEL_DIMM
     //store dimm i2c addr info to s3
     dsrl    a2, s1, 16
@@ -305,10 +291,8 @@ t0,t2 shouldn't be changed to the end of this file.
 //This seems better for the spec2000
 //if we enable ECC, this bit will be reset
     PRINTSTR("Disable read buffer\r\n")
-    lw      a1, 0x4(t2)
+    bal     disable_mc_read_buffer
-    li      a0, 0x18
+    nop
-    or      a1, a1, a0
-    sw      a1, 0x4(t2)
 #endif
 
 //init MC1 will damage MC0 s1 info
@@ -320,22 +304,6 @@ t0,t2 shouldn't be changed to the end of this file.
     nop
 
     dli     t3, 0x0
-#ifndef  DISABLE_DIMM_ECC
-    //Enable MC read buffer for ECC Initial
-    GET_DIMM_ECC
-    beqz    a1, 8f
-    nop
-    TTYDBG("Enable MC read buffer\r\n")
-    lw      a1, 0x4(t2)
-    li      a0, 0x8
-    sll     a0, a0, t3
-    not     a0, a0
-    and     a1, a1, a0
-    sw      a1, 0x4(t2)
-    sync
-8:
-#endif
-
 #ifdef  AUTO_ARB_LEVEL
     bal     SET_AUTO_ARB_LEVEL_MARK
     nop
@@ -344,20 +312,6 @@ t0,t2 shouldn't be changed to the end of this file.
     bal     mc_init
     nop
 
-#ifndef  DISABLE_DIMM_ECC
-    //Disable MC read buffer after ECC Initial
-    GET_DIMM_ECC
-    beqz    a1, 8f
-    nop
-    TTYDBG("Disable MC read buffer\r\n")
-    lw      a1, 0x4(t2)
-    li      a0, 0x8
-    sll     a0, a0, t3
-    or      a1, a1, a0
-    sw      a1, 0x4(t2)
-    sync
-8:
-#endif
     PRINTSTR("\r\nMC0 Config DONE\r\n")
 //-------------------------------------
 //config MC1 if not define MC0_ONLY
@@ -376,22 +330,6 @@ t0,t2 shouldn't be changed to the end of this file.
     and     s1, s1, a1
     or      s1, s1, t5
 
-#ifndef  DISABLE_DIMM_ECC
-    //Enable MC read buffer for ECC Initial
-    GET_DIMM_ECC
-    beqz    a1, 8f
-    nop
-    TTYDBG("Enable MC read buffer\r\n")
-    lw      a1, 0x4(t2)
-    li      a0, 0x8
-    sll     a0, a0, t3
-    not     a0, a0
-    and     a1, a1, a0
-    sw      a1, 0x4(t2)
-    sync
-8:
-#endif
-
 #ifdef  AUTO_ARB_LEVEL
     bal     SET_AUTO_ARB_LEVEL_MARK
     nop
@@ -400,20 +338,6 @@ t0,t2 shouldn't be changed to the end of this file.
     bal     mc_init
     nop
 
-#ifndef  DISABLE_DIMM_ECC
-    //Disable MC read buffer after ECC Initial
-    GET_DIMM_ECC
-    beqz    a1, 8f
-    nop
-    TTYDBG("Disable MC read buffer\r\n")
-    lw      a1, 0x4(t2)
-    li      a0, 0x8
-    sll     a0, a0, t3
-    or      a1, a1, a0
-    sw      a1, 0x4(t2)
-    sync
-8:
-#endif
     TTYDBG("\r\nMC1 Config DONE\r\n")
 //-------------------------------------
 12:

pmon/arch/mips/mm/store_auto_arb_level_info.S

@@ -3,13 +3,41 @@
 #define DIMM_INFO_ADDR  0x980000000fff0000
 #define DIMM_INFO_TOKEN 0x2013011014413291
 /***************
-store info organize:
+store info organize in memory:
 0x0: token
 0x8: s3
-0x10~0x30: Node 0 MC0, slot 0, slot 1
+DIMM identifier:
-0x30~0x50: Node 0 MC1, slot 0, slot 1
+0x10~0x30: Chip 0 MC0, slot 0, slot 1
-0x50~0x70: Node 1 MC0, slot 0, slot 1
+0x30~0x50: Chip 0 MC1, slot 0, slot 1
-0x70~0x90: Node 1 MC1, slot 0, slot 1
+0x50~0x70: Chip 1 MC0, slot 0, slot 1
+0x70~0x90: Chip 1 MC1, slot 0, slot 1
+MC clksel:
+    0: soft freq config/hardware freq config
+63: 1: configure setting(soft clksel, hard clksel)
+0x90:   Chip 0 MC0
+0x98:   Chip 1 MC1
+0xa0:   Chip 1 MC0
+0xa8:   Chip 1 MC1
+
+s3:
+|[52:48]|                    | 4'bx    | chip 1 ddr clksel |--obselete
+|[44:40]|                    | 4'bx    | chip 0 ddr clksel |--obselete
+|[39:36]|                    | 4'bx    | Reserved          |
+|[35:32]|                    | 4'bx    | level status      |
+|35:    |                                       Chip 1 MC1 |
+|34:    |                                       Chip 1 MC0 |
+|33:    |                                       Chip 0 MC1 |
+|32:    |                                       Chip 0 MC0 |
+Chip 1(3A node 1,3B node 2/3):
+|[31:28]|                    | 4'bx    | MC1_SLOT1 I2C ADDR|
+|[27:24]|                    | 4'bx    | MC1_SLOT0 I2C ADDR|
+|[23:20]|                    | 4'bx    | MC0_SLOT1 I2C ADDR|
+|[19:16]|                    | 4'bx    | MC0_SLOT0 I2C ADDR|
+Chip 0(3A node 0,3B node 0/1):
+|[15:12]|                    | 4'bx    | MC1_SLOT1 I2C ADDR|
+|[11: 8]|                    | 4'bx    | MC1_SLOT0 I2C ADDR|
+|[ 7: 4]|                    | 4'bx    | MC0_SLOT1 I2C ADDR|
+|[ 3: 0]|                    | 4'bx    | MC0_SLOT0 I2C ADDR|
 ***************/
     //set token to detect whether this area info is demaged
     dli     t0, DIMM_INFO_ADDR
@@ -20,9 +48,9 @@ store info organize:
 
 #ifdef  CHECK_ARB_LEVEL_DIMM
     PRINTSTR("\r\nstore DIMM info of NODE0\r\n")
-    dsrl    s1, s3, 32
     //deal N0 MC0
-    and     a0, s1, 0x1
+    dsrl    a0, s3, 32
+    and     a0, a0, 0x1
     beqz    a0, 1f
     nop
     //store N0-MC0 info
@@ -43,11 +71,11 @@ store info organize:
     sd      t5, 0x28(t0)
 1:
     //deal N0 MC1
-    dsrl    s1, s1, 1
+    dsrl    a0, s3, 33
-    and     a0, s1, 0x1
+    and     a0, a0, 0x1
     beqz    a0, 1f
     nop
-    //store N0-MC0 info
+    //store N0-MC1 info
     dsrl    a0, s3, 8
     and     a0, a0, 0xf
     move    a2, $0
@@ -67,8 +95,8 @@ store info organize:
 #if ((loongson3A3 && MULTI_CHIP) || (LS3B && DUAL_3B))
     PRINTSTR("\r\nstore DIMM info of NODE1\r\n")
     //deal N1 MC0
-    dsrl    s1, s1, 1
+    dsrl    a0, s3, 34
-    and     a0, s1, 0x1
+    and     a0, a0, 0x1
     beqz    a0, 1f
     nop
     //store N0-MC0 info
@@ -89,8 +117,8 @@ store info organize:
     sd      t5, 0x68(t0)
 1:
     //deal N1 MC1
-    dsrl    s1, s1, 1
+    dsrl    a0, s3, 35
-    and     a0, s1, 0x1
+    and     a0, a0, 0x1
     beqz    a0, 1f
     nop
     //store N0-MC0 info
@@ -111,11 +139,54 @@ store info organize:
     sd      t5, 0x88(t0)
 1:
 #endif
+#endif
+
+#ifdef  CHECK_ARB_LEVEL_FREQ
+    dsrl    a0, s3, 32
+    and     a0, a0, 0x1
+    beqz    a0, 1f
+    nop
+    move    a1, $0
+    bal     GET_DDR_FREQ_CONFIG
+    nop
+    sd      v0, 0x90(t0)
+1:
+    dsrl    a0, s3, 33
+    and     a0, a0, 0x1
+    beqz    a0, 1f
+    nop
+    move    a1, $0
+    bal     GET_DDR_FREQ_CONFIG
+    nop
+    sd      v0, 0x98(t0)
+1:
+#if ((loongson3A3 && MULTI_CHIP) || (LS3B && DUAL_3B))
+    //deal N1 MC0
+    dsrl    a0, s3, 34
+    and     a0, a0, 0x1
+    beqz    a0, 1f
+    nop
+    add     a1, $0, 1
+    bal     GET_DDR_FREQ_CONFIG
+    nop
+    sd      v0, 0xa0(t0)
+1:
+    dsrl    a0, s3, 35
+    and     a0, a0, 0x1
+    beqz    a0, 1f
+    nop
+    add     a1, $0, 1
+    bal     GET_DDR_FREQ_CONFIG
+    nop
+    sd      v0, 0xa8(t0)
+1:
+#endif
+#endif
 
 #ifdef  DEBUG_AUTO_ARB_LEVEL
     //print stored memory
     dli     t0, DIMM_INFO_ADDR
-    daddu   t3, t0, 0x90
+    daddu   t3, t0, 0xb0
     PRINTSTR("\r\nthe stored info is:\r\n")
 1:
     dsrl    a0, t0, 32
@@ -138,4 +209,3 @@ store info organize:
     blt     t0, t3, 1b
     nop
 #endif
-#endif

pmon/cmds/save_ddrparam.c

@@ -257,13 +257,13 @@ void save_ddrparam(u64 node_id_shift44, u64 *ddr_param_buf, int param_store_addr
     printf("\nnode_id_shift44=0x%016llx\n", node_id_shift44);
 #endif
     // step 1.1 Read out DDR controler register from MC and save them in buffer
-    read_ddr_param(node_id_shift44, mc_selector, &ddr_param_buf[5]);
+    read_ddr_param(node_id_shift44, mc_selector, &ddr_param_buf[6]);
 
     // step 1.2 Program buffers of MC0 register into FLASH
-    tgt_flashprogram((int *)(0xbfc00000+(param_store_addr -(int)&_start)), (DDR_PARAM_NUM + 5) * 8, ddr_param_buf, TRUE);
+    tgt_flashprogram((int *)(0xbfc00000+(param_store_addr -(int)&_start)), (DDR_PARAM_NUM + 6) * 8, ddr_param_buf, TRUE);
 
 #ifdef DEBUG
-    for(i = 0; i < DDR_PARAM_NUM + 5; i++)
+    for(i = 0; i < DDR_PARAM_NUM + 6; i++)
     {
         tmp =  __raw__readq(0x900000001fc00000ull + param_store_addr - (int)&_start + i * 8);
         if(ddr_param_buf[i] != tmp)
@@ -292,34 +292,38 @@ int save_board_ddrparam(int mandatory)
         //MC0
         if( ((flag >> 32) & 0x1) || mandatory ){
             printf("Store MC info of Node %lld MC 0\n", node_id);
-            ddr_param_buf[0] = (((flag >> 40) & 0x1f) << 32) | 0x1;
+            ddr_param_buf[0] = 0x1;
             ddr_param_buf[1] = __raw__readq(DIMM_INFO_ADDR + 0x10);
             ddr_param_buf[2] = __raw__readq(DIMM_INFO_ADDR + 0x18);
             ddr_param_buf[3] = __raw__readq(DIMM_INFO_ADDR + 0x20);
             ddr_param_buf[4] = __raw__readq(DIMM_INFO_ADDR + 0x28);
+            ddr_param_buf[5] = __raw__readq(DIMM_INFO_ADDR + 0x90);
 #ifdef DEBUG
             printf("mc level info is 0x%016llx\n", ddr_param_buf[0]);
-            printf("dimm info is 0x%016llx\n", ddr_param_buf[1]);
+            printf("dimm 0 info is 0x%016llx\n", ddr_param_buf[1]);
-            printf("dimm info is 0x%016llx\n", ddr_param_buf[2]);
+            printf("dimm 0 info is 0x%016llx\n", ddr_param_buf[2]);
-            printf("dimm info is 0x%016llx\n", ddr_param_buf[3]);
+            printf("dimm 1 info is 0x%016llx\n", ddr_param_buf[3]);
-            printf("dimm info is 0x%016llx\n", ddr_param_buf[4]);
+            printf("dimm 1 info is 0x%016llx\n", ddr_param_buf[4]);
+            printf("clksel info is 0x%016llx\n", ddr_param_buf[5]);
 #endif
             save_ddrparam(node_id << 44, &ddr_param_buf, (int)&c0_mc0_level_info, 0);
         }
         //MC1
         if( ((flag >> 33) & 0x1) || mandatory ){
             printf("Store MC info of Node %lld MC 1\n", node_id);
-            ddr_param_buf[0] = (((flag >> 40) & 0x1f) << 32) | 0x1;
+            ddr_param_buf[0] = 0x1;
             ddr_param_buf[1] = __raw__readq(DIMM_INFO_ADDR + 0x30);
             ddr_param_buf[2] = __raw__readq(DIMM_INFO_ADDR + 0x38);
             ddr_param_buf[3] = __raw__readq(DIMM_INFO_ADDR + 0x40);
             ddr_param_buf[4] = __raw__readq(DIMM_INFO_ADDR + 0x48);
+            ddr_param_buf[5] = __raw__readq(DIMM_INFO_ADDR + 0x98);
 #ifdef DEBUG
             printf("mc level info is 0x%016llx\n", ddr_param_buf[0]);
-            printf("dimm info is 0x%016llx\n", ddr_param_buf[1]);
+            printf("dimm 0 info is 0x%016llx\n", ddr_param_buf[1]);
-            printf("dimm info is 0x%016llx\n", ddr_param_buf[2]);
+            printf("dimm 0 info is 0x%016llx\n", ddr_param_buf[2]);
-            printf("dimm info is 0x%016llx\n", ddr_param_buf[3]);
+            printf("dimm 1 info is 0x%016llx\n", ddr_param_buf[3]);
-            printf("dimm info is 0x%016llx\n", ddr_param_buf[4]);
+            printf("dimm 1 info is 0x%016llx\n", ddr_param_buf[4]);
+            printf("clksel info is 0x%016llx\n", ddr_param_buf[5]);
 #endif
             save_ddrparam(node_id << 44, &ddr_param_buf, (int)&c0_mc1_level_info, 1);
         }
@@ -328,34 +332,38 @@ int save_board_ddrparam(int mandatory)
         //MC0
         if( ((flag >> 34) & 0x1) || mandatory ){
             printf("Store MC info of Node %lld MC 0\n", node_id);
-            ddr_param_buf[0] = (((flag >> 48) & 0x1f) << 32) | 0x1;
+            ddr_param_buf[0] = 0x1;
             ddr_param_buf[1] = __raw__readq(DIMM_INFO_ADDR + 0x50);
             ddr_param_buf[2] = __raw__readq(DIMM_INFO_ADDR + 0x58);
             ddr_param_buf[3] = __raw__readq(DIMM_INFO_ADDR + 0x60);
             ddr_param_buf[4] = __raw__readq(DIMM_INFO_ADDR + 0x68);
+            ddr_param_buf[5] = __raw__readq(DIMM_INFO_ADDR + 0xa0);
 #ifdef DEBUG
             printf("mc level info is 0x%016llx\n", ddr_param_buf[0]);
-            printf("dimm info is 0x%016llx\n", ddr_param_buf[1]);
+            printf("dimm 0 info is 0x%016llx\n", ddr_param_buf[1]);
-            printf("dimm info is 0x%016llx\n", ddr_param_buf[2]);
+            printf("dimm 0 info is 0x%016llx\n", ddr_param_buf[2]);
-            printf("dimm info is 0x%016llx\n", ddr_param_buf[3]);
+            printf("dimm 1 info is 0x%016llx\n", ddr_param_buf[3]);
-            printf("dimm info is 0x%016llx\n", ddr_param_buf[4]);
+            printf("dimm 1 info is 0x%016llx\n", ddr_param_buf[4]);
+            printf("clksel info is 0x%016llx\n", ddr_param_buf[5]);
 #endif
             save_ddrparam(node_id << 44, &ddr_param_buf, (int)&c1_mc0_level_info, 0);
         }
         //MC1
         if( ((flag >> 35) & 0x1) || mandatory ){
             printf("Store MC info of Node %lld MC 1\n", node_id);
-            ddr_param_buf[0] = (((flag >> 48) & 0x1f) << 32) | 0x1;
+            ddr_param_buf[0] = 0x1;
             ddr_param_buf[1] = __raw__readq(DIMM_INFO_ADDR + 0x70);
             ddr_param_buf[2] = __raw__readq(DIMM_INFO_ADDR + 0x78);
             ddr_param_buf[3] = __raw__readq(DIMM_INFO_ADDR + 0x80);
             ddr_param_buf[4] = __raw__readq(DIMM_INFO_ADDR + 0x88);
+            ddr_param_buf[5] = __raw__readq(DIMM_INFO_ADDR + 0xa8);
 #ifdef DEBUG
             printf("mc level info is 0x%016llx\n", ddr_param_buf[0]);
-            printf("dimm info is 0x%016llx\n", ddr_param_buf[1]);
+            printf("dimm 0 info is 0x%016llx\n", ddr_param_buf[1]);
-            printf("dimm info is 0x%016llx\n", ddr_param_buf[2]);
+            printf("dimm 0 info is 0x%016llx\n", ddr_param_buf[2]);
-            printf("dimm info is 0x%016llx\n", ddr_param_buf[3]);
+            printf("dimm 1 info is 0x%016llx\n", ddr_param_buf[3]);
-            printf("dimm info is 0x%016llx\n", ddr_param_buf[4]);
+            printf("dimm 1 info is 0x%016llx\n", ddr_param_buf[4]);
+            printf("clksel info is 0x%016llx\n", ddr_param_buf[5]);
 #endif
             save_ddrparam(node_id << 44, &ddr_param_buf, (int)&c1_mc1_level_info, 1);
         }
@@ -383,17 +391,19 @@ int save_board_ddrparam(int mandatory)
         node_id = 0;
         if( ((flag >> 32) & 0x1) || mandatory ){
             printf("Store MC info of Node %d\n", node_id);
-            ddr_param_buf[0] = (((flag >> 40) & 0x1f) << 32) | 0x1;
+            ddr_param_buf[0] = 0x1;
             ddr_param_buf[1] = __raw__readq(DIMM_INFO_ADDR + 0x10);
             ddr_param_buf[2] = __raw__readq(DIMM_INFO_ADDR + 0x18);
             ddr_param_buf[3] = __raw__readq(DIMM_INFO_ADDR + 0x20);
             ddr_param_buf[4] = __raw__readq(DIMM_INFO_ADDR + 0x28);
+            ddr_param_buf[5] = __raw__readq(DIMM_INFO_ADDR + 0x90);
 #ifdef DEBUG
             printf("mc level info is 0x%016llx\n", ddr_param_buf[0]);
-            printf("dimm info is 0x%016llx\n", ddr_param_buf[1]);
+            printf("dimm 0 info is 0x%016llx\n", ddr_param_buf[1]);
-            printf("dimm info is 0x%016llx\n", ddr_param_buf[2]);
+            printf("dimm 0 info is 0x%016llx\n", ddr_param_buf[2]);
-            printf("dimm info is 0x%016llx\n", ddr_param_buf[3]);
+            printf("dimm 1 info is 0x%016llx\n", ddr_param_buf[3]);
-            printf("dimm info is 0x%016llx\n", ddr_param_buf[4]);
+            printf("dimm 1 info is 0x%016llx\n", ddr_param_buf[4]);
+            printf("clksel info is 0x%016llx\n", ddr_param_buf[5]);
 #endif
             save_ddrparam(node_id << 44, &ddr_param_buf, (int)&c0_mc0_level_info, 0);
         }
@@ -403,17 +413,19 @@ int save_board_ddrparam(int mandatory)
         node_id = 1;
         if( ((flag >> 33) & 0x1) || mandatory ){
             printf("Store MC info of Node %d\n", node_id);
-            ddr_param_buf[0] = (((flag >> 40) & 0x1f) << 32) | 0x1;
+            ddr_param_buf[0] = 0x1;
             ddr_param_buf[1] = __raw__readq(DIMM_INFO_ADDR + 0x30);
             ddr_param_buf[2] = __raw__readq(DIMM_INFO_ADDR + 0x38);
             ddr_param_buf[3] = __raw__readq(DIMM_INFO_ADDR + 0x40);
             ddr_param_buf[4] = __raw__readq(DIMM_INFO_ADDR + 0x48);
+            ddr_param_buf[5] = __raw__readq(DIMM_INFO_ADDR + 0x98);
 #ifdef DEBUG
             printf("mc level info is 0x%016llx\n", ddr_param_buf[0]);
-            printf("dimm info is 0x%016llx\n", ddr_param_buf[1]);
+            printf("dimm 0 info is 0x%016llx\n", ddr_param_buf[1]);
-            printf("dimm info is 0x%016llx\n", ddr_param_buf[2]);
+            printf("dimm 0 info is 0x%016llx\n", ddr_param_buf[2]);
-            printf("dimm info is 0x%016llx\n", ddr_param_buf[3]);
+            printf("dimm 1 info is 0x%016llx\n", ddr_param_buf[3]);
-            printf("dimm info is 0x%016llx\n", ddr_param_buf[4]);
+            printf("dimm 1 info is 0x%016llx\n", ddr_param_buf[4]);
+            printf("clksel info is 0x%016llx\n", ddr_param_buf[5]);
 #endif
             save_ddrparam(node_id << 44, &ddr_param_buf, (int)&c0_mc1_level_info, 0);
         }
@@ -423,17 +435,19 @@ int save_board_ddrparam(int mandatory)
         node_id = 2;
         if( ((flag >> 34) & 0x1) || mandatory ){
             printf("Store MC info of Node %d\n", node_id);
-            ddr_param_buf[0] = (((flag >> 48) & 0x1f) << 32) | 0x1;
+            ddr_param_buf[0] = 0x1;
             ddr_param_buf[1] = __raw__readq(DIMM_INFO_ADDR + 0x50);
             ddr_param_buf[2] = __raw__readq(DIMM_INFO_ADDR + 0x58);
             ddr_param_buf[3] = __raw__readq(DIMM_INFO_ADDR + 0x60);
             ddr_param_buf[4] = __raw__readq(DIMM_INFO_ADDR + 0x68);
+            ddr_param_buf[5] = __raw__readq(DIMM_INFO_ADDR + 0xa0);
 #ifdef DEBUG
             printf("mc level info is 0x%016llx\n", ddr_param_buf[0]);
-            printf("dimm info is 0x%016llx\n", ddr_param_buf[1]);
+            printf("dimm 0 info is 0x%016llx\n", ddr_param_buf[1]);
-            printf("dimm info is 0x%016llx\n", ddr_param_buf[2]);
+            printf("dimm 0 info is 0x%016llx\n", ddr_param_buf[2]);
-            printf("dimm info is 0x%016llx\n", ddr_param_buf[3]);
+            printf("dimm 1 info is 0x%016llx\n", ddr_param_buf[3]);
-            printf("dimm info is 0x%016llx\n", ddr_param_buf[4]);
+            printf("dimm 1 info is 0x%016llx\n", ddr_param_buf[4]);
+            printf("clksel info is 0x%016llx\n", ddr_param_buf[5]);
 #endif
             save_ddrparam(node_id << 44, &ddr_param_buf, (int)&c1_mc0_level_info, 0);
         }
@@ -441,17 +455,19 @@ int save_board_ddrparam(int mandatory)
         node_id = 3;
         if( ((flag >> 35) & 0x1) || mandatory ){
             printf("Store MC info of Node %d\n", node_id);
-            ddr_param_buf[0] = (((flag >> 48) & 0x1f) << 32) | 0x1;
+            ddr_param_buf[0] = 0x1;
             ddr_param_buf[1] = __raw__readq(DIMM_INFO_ADDR + 0x70);
             ddr_param_buf[2] = __raw__readq(DIMM_INFO_ADDR + 0x78);
             ddr_param_buf[3] = __raw__readq(DIMM_INFO_ADDR + 0x80);
             ddr_param_buf[4] = __raw__readq(DIMM_INFO_ADDR + 0x88);
+            ddr_param_buf[5] = __raw__readq(DIMM_INFO_ADDR + 0xa8);
 #ifdef DEBUG
             printf("mc level info is 0x%016llx\n", ddr_param_buf[0]);
-            printf("dimm info is 0x%016llx\n", ddr_param_buf[1]);
+            printf("dimm 0 info is 0x%016llx\n", ddr_param_buf[1]);
-            printf("dimm info is 0x%016llx\n", ddr_param_buf[2]);
+            printf("dimm 0 info is 0x%016llx\n", ddr_param_buf[2]);
-            printf("dimm info is 0x%016llx\n", ddr_param_buf[3]);
+            printf("dimm 1 info is 0x%016llx\n", ddr_param_buf[3]);
-            printf("dimm info is 0x%016llx\n", ddr_param_buf[4]);
+            printf("dimm 1 info is 0x%016llx\n", ddr_param_buf[4]);
+            printf("clksel info is 0x%016llx\n", ddr_param_buf[5]);
 #endif
             save_ddrparam(node_id << 44, &ddr_param_buf, (int)&c1_mc1_level_info, 0);
         }