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Merge "3a3000 tRFC reconfig and other leveling modified"

master
张宝祺 6 years ago
committed by Gerrit Code Review
parent
767729d8c5 2dec78933f
commit
e72d9bc154
7 changed files with 177 additions and 32 deletions
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  1. 4
      Targets/Bonito3a3000_7a/Bonito/loongson3a8_clk.S
  2. 16
      Targets/Bonito3a3000_7a/Bonito/loongson_mc2_param.S
  3. 1
      Targets/Bonito3a3000_7a/Bonito/start.S
  4. 17
      pmon/arch/mips/mm/ddr_config_define.h
  5. 41
      pmon/arch/mips/mm/loongson3C_ddr3_leveling.S
  6. 39
      pmon/arch/mips/mm/ls3A8_ddr_config.S
  7. 91
      pmon/arch/mips/mm/lsmc_config_param.S

4
Targets/Bonito3a3000_7a/Bonito/loongson3a8_clk.S
View File

@ -8,13 +8,13 @@
//#define DDR_LOOPC 96 //400MHz
//#define DDR_LOOPC 28 //466MHz
//#define DDR_LOOPC 60 //500MHz
#define DDR_LOOPC 64 //533MHz
#define DDR_LOOPC 80 //533MHz
//#define DDR_LOOPC 34 //566MHz
//#define DDR_LOOPC 72 //600MHz
//#define DDR_LOOPC 76 //633MHz
//#define DDR_LOOPC 80 //667MHz
#define DDR_REFC 1
#define DDR_DIV 4
#define DDR_DIV 5
// L1_* define both CPU and Node freq simutanleously
//#define L1_LOOPC 80//1000@25MHz

16
Targets/Bonito3a3000_7a/Bonito/loongson_mc2_param.S
View File

@ -257,11 +257,15 @@ MC0_DDR3_RDIMM_CTRL_0x008: .dword 0x0000000000000000
//XXXX pm_dll_value_4(RD) XXXX pm_dll_value_3 (RD) XXXX pm_dll_value_2(RD) XXXX pm_dll_value_1(RD)
MC0_DDR3_RDIMM_CTRL_0x010: .dword 0x0000000000000000
//XXXX pm_dll_value_8(RD) XXXX pm_dll_value_7 (RD) XXXX pm_dll_value_6(RD) XXXX pm_dll_value_5(RD)
#ifdef MULTI_CHIP
MC0_DDR3_RDIMM_CTRL_0x018: .dword 0x3737373716100000
#else
//MC0_DDR3_RDIMM_CTRL_0x018: .dword 0x5252525216100000
//MC0_DDR3_RDIMM_CTRL_0x018: .dword 0x4040404016100000
//MC0_DDR3_RDIMM_CTRL_0x018: .dword 0x3030303016100000
MC0_DDR3_RDIMM_CTRL_0x018: .dword 0x4343434316100000
MC0_DDR3_RDIMM_CTRL_0x018: .dword 0x5050505016100000
//MC0_DDR3_RDIMM_CTRL_0x018: .dword 0x2525252516100000
#endif
//_00000000 pm_dll_ck_3 _00000000 pm_dll_ck_2 _00000000 pm_dll_ck_1 _00000000 pm_dll_ck_0 _00000000 pm_dll_increment _00000000 pm_dll_start_point _0000000_0 pm_dll_bypass _0000000_0 pm_init_start
MC0_DDR3_RDIMM_CTRL_0x020: .dword 0x0201000201000000
//0000_0000 pm_dq_oe_end_0 0000_0000 pm_dq_oe_begin_0 000000_00 pm_dq_stop_edge_0 000000_00 pm_dq_start_edge_0 0000000_0 pm_rddata_delay_0 0000000_0 pm_rddqs_lt_half_0 0000000_0 pm_wrdqs_lt_half_0 0000000_0 pm_wrdq_lt_half_0
@ -497,11 +501,15 @@ MC1_DDR3_RDIMM_CTRL_0x008: .dword 0x0000000000000000
//XXXX pm_dll_value_4(RD) XXXX pm_dll_value_3 (RD) XXXX pm_dll_value_2(RD) XXXX pm_dll_value_1(RD)
MC1_DDR3_RDIMM_CTRL_0x010: .dword 0x0000000000000000
//XXXX pm_dll_value_8(RD) XXXX pm_dll_value_7 (RD) XXXX pm_dll_value_6(RD) XXXX pm_dll_value_5(RD)
#ifdef MULTI_CHIP
MC1_DDR3_RDIMM_CTRL_0x018: .dword 0x4a4a4a4a16100000
#else
//MC1_DDR3_RDIMM_CTRL_0x018: .dword 0x5252525216100000
//MC1_DDR3_RDIMM_CTRL_0x018: .dword 0x4040404016100000
//MC1_DDR3_RDIMM_CTRL_0x018: .dword 0x3030303016100000
MC1_DDR3_RDIMM_CTRL_0x018: .dword 0x4a4a4a4a16100000
MC1_DDR3_RDIMM_CTRL_0x018: .dword 0x5050505016100000
//MC1_DDR3_RDIMM_CTRL_0x018: .dword 0x2525252516100000
#endif
//_00000000 pm_dll_ck_3 _00000000 pm_dll_ck_2 _00000000 pm_dll_ck_1 _00000000 pm_dll_ck_0 _00000000 pm_dll_increment _00000000 pm_dll_start_point _0000000_0 pm_dll_bypass _0000000_0 pm_init_start
MC1_DDR3_RDIMM_CTRL_0x020: .dword 0x0201000201000000
//0000_0000 pm_dq_oe_end_0 0000_0000 pm_dq_oe_begin_0 000000_00 pm_dq_stop_edge_0 000000_00 pm_dq_start_edge_0 0000000_0 pm_rddata_delay_0 0000000_0 pm_rddqs_lt_half_0 0000000_0 pm_wrdqs_lt_half_0 0000000_0 pm_wrdq_lt_half_0
@ -740,7 +748,7 @@ MC2_DDR3_RDIMM_CTRL_0x010: .dword 0x0000000000000000
//MC2_DDR3_RDIMM_CTRL_0x018: .dword 0x5252525216100000
//MC2_DDR3_RDIMM_CTRL_0x018: .dword 0x4040404016100000
//MC2_DDR3_RDIMM_CTRL_0x018: .dword 0x3030303016100000
MC2_DDR3_RDIMM_CTRL_0x018: .dword 0x3d3d3d3d16100000
MC2_DDR3_RDIMM_CTRL_0x018: .dword 0x3030303016100000
//MC2_DDR3_RDIMM_CTRL_0x018: .dword 0x2525252516100000
//_00000000 pm_dll_ck_3 _00000000 pm_dll_ck_2 _00000000 pm_dll_ck_1 _00000000 pm_dll_ck_0 _00000000 pm_dll_increment _00000000 pm_dll_start_point _0000000_0 pm_dll_bypass _0000000_0 pm_init_start
MC2_DDR3_RDIMM_CTRL_0x020: .dword 0x0201000201000000
@ -980,7 +988,7 @@ MC3_DDR3_RDIMM_CTRL_0x010: .dword 0x0000000000000000
//MC3_DDR3_RDIMM_CTRL_0x018: .dword 0x5252525216100000
//MC3_DDR3_RDIMM_CTRL_0x018: .dword 0x4040404016100000
//MC3_DDR3_RDIMM_CTRL_0x018: .dword 0x3030303016100000
MC3_DDR3_RDIMM_CTRL_0x018: .dword 0x4b4b4b4b16100000
MC3_DDR3_RDIMM_CTRL_0x018: .dword 0x4a4a4a4a16100000
//MC3_DDR3_RDIMM_CTRL_0x018: .dword 0x2525252516100000
//_00000000 pm_dll_ck_3 _00000000 pm_dll_ck_2 _00000000 pm_dll_ck_1 _00000000 pm_dll_ck_0 _00000000 pm_dll_increment _00000000 pm_dll_start_point _0000000_0 pm_dll_bypass _0000000_0 pm_init_start
MC3_DDR3_RDIMM_CTRL_0x020: .dword 0x0201000201000000

1
Targets/Bonito3a3000_7a/Bonito/start.S
View File

@ -674,6 +674,7 @@ no_reboot:
//#define DLL_DELAY_LOOP
//#define PRINT_DDR_LEVELING
//#define DLL_CK_DELAY_DEBUG
//#define NO_AUTO_TRFC //adjust TRFC param manually if defined
TTYDBG("\r\nStart Init Memory, wait a while......\r\n")
####################################

17
pmon/arch/mips/mm/ddr_config_define.h
View File

@ -1,7 +1,7 @@
/***********************************************************
* Author: Chen Xinke
***********************************************************/
/***********************************************************
/***********************************************************
msize map
[ 7: 0]: Node 0 memorysize
[15: 8]: Node 1 memorysize
@ -67,7 +67,7 @@ DIMM infor:
|[15:15]| SDRAM_WIDTH | 1'b1 | x16 |
| | | 1'b0 | x8 |
------------------------------------------------------------
|[63:47]| MC1--like s1[31:16] for MC0
|[63:48]| MC1--like s1[31:16] for MC0
temparary used in PROBE_DIMM
|[38:32]| DIMM_MEMSIZE | 7'b0000 | 0M |
| | | 7'b0001 | 512M |
@ -292,7 +292,9 @@ temparary used in PROBE_DIMM
#define ADDR_MIRROR_OFFSET 22
#define COL_SIZE_OFFSET 20
#define MC_CS_MAP_OFFSET 16
#define MC1_CS_MAP_OFFSET 48
#define SDRAM_WIDTH_OFFSET 15
#define MC1_SDRAM_WIDTH_OFFSET 47
#define MC_CS_MAP_MASK (0xf)
#define MC1_MEMSIZE_OFFSET 40
#define MC0_MEMSIZE_OFFSET 8
@ -310,6 +312,11 @@ dli a1, 0x1;\
dsll a1, a1, SDRAM_WIDTH_OFFSET;\
and a1, s1, a1;\
dsrl a1, a1, SDRAM_WIDTH_OFFSET;
#define GET_MC1_SDRAM_WIDTH \
dli a1, 0x1;\
dsll a1, a1, MC1_SDRAM_WIDTH_OFFSET;\
and a1, s1, a1;\
dsrl a1, a1, MC1_SDRAM_WIDTH_OFFSET;
#define GET_DIMM_ECC \
dli a1, 0x1;\
dsll a1, a1, DIMM_ECC_OFFSET;\
@ -350,6 +357,11 @@ dli a1, MC_CS_MAP_MASK;\
dsll a1, a1, MC_CS_MAP_OFFSET;\
and a1, s1, a1;\
dsrl a1, a1, MC_CS_MAP_OFFSET;
#define GET_MC1_CS_MAP \
dli a1, MC_CS_MAP_MASK;\
dsll a1, a1, MC1_CS_MAP_OFFSET;\
and a1, s1, a1;\
dsrl a1, a1, MC1_CS_MAP_OFFSET;
#define GET_DIMM_MEMSIZE \
dli a1, DIMM_MEMSIZE_MASK;\
dsll a1, a1, DIMM_MEMSIZE_OFFSET;\
@ -366,4 +378,3 @@ dsll a1, a1, MC0_MEMSIZE_OFFSET;\
and a1, s1, a1;\
dsrl a1, a1, MC0_MEMSIZE_OFFSET;
#endif

41
pmon/arch/mips/mm/loongson3C_ddr3_leveling.S
View File

@ -291,10 +291,21 @@ dll_wrdqs_add0:
sb t4, OFFSET_WRDQ_LTHF(t1) //set wrdq_lt_half
2:
#endif
bgt t6, MDL_CNT, leveling_failed
blt t6, MDL_CNT, 1f
nop
daddu t6, t6, 0x1
b lvl_req_set0
#ifdef DLL_DELAY_LOOP
PRINTSTR("\r\n sample 0 is time out \r\n")
b leveling_failed
nop
#else
2:
PRINTSTR("\r\n sample 0 is time out \r\n")
b 2b
nop
#endif
1:
daddu t6, t6, 0x1
b lvl_req_set0
nop
resp_set0_done:
@ -429,10 +440,21 @@ dll_wrdqs_add1:
sb t4, OFFSET_WRDQ_LTHF(t1) //set wrdq_lt_half
2:
#endif
bgt t6, MDL_CNT, leveling_failed
blt t6, MDL_CNT, 1f
nop
daddu t6, t6, 0x1
b lvl_req_set1
#ifdef DLL_DELAY_LOOP
PRINTSTR("\r\n sample 1 is time out \r\n")
b leveling_failed
nop
#else
2:
PRINTSTR("\r\n sample 1 is time out \r\n")
b 2b
nop
#endif
1:
daddu t6, t6, 0x1
b lvl_req_set1
nop
resp_set1_done:
@ -617,7 +639,7 @@ wrdq_lt_half_test_loop:
dli t4, 0x20
mulou t1, a0, t4
or t1, t1, t8
#if 1
#if 0
bal hexserial
nop
#endif
@ -638,7 +660,7 @@ wrdq_lt_half_test_loop:
dli t4, 0x20
mulou t1, a0, t4
or t1, t1, t8
#if 1
#if 0
bal hexserial
nop
#endif
@ -651,9 +673,6 @@ wrdq_lt_half_test_loop:
record_slice_num:
move t3, t2 //the slice number save in t3
move a0, t3
bal hexserial
nop
beq t3, 0x8, first_slice_wrdq_lt_half_test
nop

39
pmon/arch/mips/mm/ls3A8_ddr_config.S
View File

@ -153,7 +153,7 @@ mc_init:
nop
dla a2, ddr3_RDIMM_reg_data_mc1
21:
#ifdef MULTI_NODE_DDR_PARAM
#if 1//def MULTI_NODE_DDR_PARAM
GET_NODE_ID_a1
beqz a1, 4f
nop
@ -295,6 +295,16 @@ mc_init:
#endif
loop_test_leveling:
GET_DIMM_TYPE
bnez a1, 21f
nop
dla a2, ddr3_reg_data
beqz k0, mc0
nop
dla a2, ddr3_reg_data_mc1
b mc0
nop
21:
dla a2, ddr3_RDIMM_reg_data
beqz k0, mc0
nop
@ -387,6 +397,7 @@ wait_dram_init_done1:
#endif
#ifdef DLL_DELAY_LOOP
move t3, k0
/* test memory */
// li t0, 0xbfe10424
// lb a0, 0x1(t0)
@ -602,6 +613,16 @@ testok:
nop
PRINTSTR("\r\n")
GET_DIMM_TYPE
bnez a1, 21f
nop
dla a2, ddr3_reg_data
beqz k0, mc0_1
nop
dla a2, ddr3_reg_data_mc1
b mc0_1
nop
21:
dla a2, ddr3_RDIMM_reg_data
beqz k0, mc0_1
nop
@ -856,7 +877,10 @@ finish:
bal hexserial
nop
PRINTSTR("\r\nPlease write the dll_clk param to corresponding place in loongson_mc2_param.S ,off set is 0x018!!!\r\n")
PRINTSTR("\r\nPlease write the dll_clk param to corresponding place in loongson_mc2_param.S ,the offset is 0x018!!!\r\n")
PRINTSTR("\r\nPress enter to continue: ");
bal inputaddress
nop
/*init start*/
dli t6, 0x1
ld t1, START_ADDR(t8)
@ -881,14 +905,6 @@ wait_dram_init_done2:
nop
move s2, k1
#if 1
ddlp:
dli a0, 0x0
b ddlp
nop
#endif
#endif
move t3, k0
@ -900,8 +916,7 @@ ddlp:
or t2, t2, a0
or t0, t0, a0
//#ifdef PRINT_DDR_LEVELING //print registers
#if 1
#if 1 //def PRINT_DDR_LEVELING //print registers
PRINTSTR("The MC param after leveling is:\r\n")
dli t1, DDR_PARAM_NUM
GET_NODE_ID_a0

91
pmon/arch/mips/mm/lsmc_config_param.S
View File

@ -299,6 +299,97 @@ set_tRTP:
sb t4, 0x10(t1)
sb t4, 0x18(t1)
*/
#endif
set_tREFI:
dli t1, DDR_FREQ
divu t1, t1, 10
dli a2, 78
dmulou a2, a2, t1
#ifndef TEMP_EXTREME
dsrl a2, a2, 8
#else
dsrl a2, a2, 9
#endif
// daddu a2, a2, 1
dli t1, 0x1c8
or t1, t1, t8
sb a2, 0x3(t1)
#ifndef NO_AUTO_TRFC
set_tRFC:
GET_MC0_MEMSIZE
beqz t3, 1f
nop
GET_MC1_MEMSIZE
1:
move t1, a1
GET_MC_CS_MAP
beqz t3, 1f
nop
GET_MC1_CS_MAP
1:
dli t5, 0x4
dli a2, 0x0
cal_memsize:
dsubu t5, t5, 1
beqz t5, 1f
nop
and t4, a1, 0x1
dsrl a1, a1, 0x1
beqz t4, cal_memsize
nop
daddu a2, a2, 1
b cal_memsize
nop
1:
divu a2, t1, a2
GET_SDRAM_WIDTH
beqz t3, 1f
nop
GET_MC1_SDRAM_WIDTH
1:
dli t5, 0x2
beqz a1, x8
nop
dli t5, 0x1
x8:
divu a2, a2, t5
dli t1, 0x1
blt a2, t1, 21f
dli t5, 0x9
dli t1, 0x2
blt a2, t1, 21f
dli t5, 0xb
dli t1, 0x4
blt a2, t1, 21f
dli t5, 0x10
dli t1, 0x8
blt a2, t1, 21f
dli t5, 0x1a
dli t1, 0x10
blt a2, t1, 21f
dli t5, 0x23
PRINTSTR("\r\n memsize wrong \r\n")
b 2f
nop
21:
dli t1, DDR_FREQ
dmulou t5, t5, t1
divu t5, t5, 100
dli t1, 0x1c8
or t1, t1, t8
sb t5, 0x2(t1)
2:
#endif
//for UDIMM 4cs,open 2T mode

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