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Fix problems for LS3A3000-7A 2way and change config to 2way. 

Change-Id: I626ff5fc19906c04dc828ac2488c2c35ebb7ae37
master
Chen Xinke 7 years ago
committed by zhangbaoqi
parent
0899c558ad
commit
e84dd74ac2
8 changed files with 334 additions and 99 deletions
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  1. 44
      Targets/Bonito3a3000_7a/Bonito/loongson3_ht1_32addr_trans.S
  2. 46
      Targets/Bonito3a3000_7a/Bonito/start.S
  3. 10
      Targets/Bonito3a3000_7a/Bonito/tgt_machdep.c
  4. 11
      Targets/Bonito3a3000_7a/conf/Bonito.3a3000_7a
  5. 2
      pmon/arch/mips/ls7a/ls3a7a_ht_init.S
  6. 262
      pmon/arch/mips/ls7a/ls3a7a_setup_ht_link.S
  7. 14
      pmon/arch/mips/ls7a/ls7a_config.S
  8. 44
      pmon/arch/mips/ls7a/ls7a_init.S

44
Targets/Bonito3a3000_7a/Bonito/loongson3_ht1_32addr_trans.S
View File

@ -34,3 +34,47 @@
bne t0, t2, 1b
nop
#ifdef LS7A_2WAY_CONNECT
dli t0, 0x900010003ff02000
daddu t2, t0, 0x800
1:
//map HT: PCI IO : 0x90000efd_fc000000 <-- 0x18000000
//map 0x90000efd_fd000000 <-- 0x19000000
//map HT: PCI CFG: 0x90000efd_fe000000 <-- 0x1a000000
//map HT: PCI CFG: 0x90000efd_ff000000 <-- 0x1b000000
dli t1, 0x0000000018000000
sd t1, 0x0(t0)
dli t1, 0xfffffffffc000000
sd t1, 0x40(t0)
dli t1, 0x00001efdfc0000f7
sd t1, 0x80(t0)
//map HT: PCI MEM : 0x90000e00_10000000 <-- 0x10000000 ~ 0x10ffffff
dli t1, 0x0000000010000000
sd t1, 0x8(t0)
dli t1, 0xffffffffff000000
sd t1, 0x48(t0)
dli t1, 0x00001e00100000f7
sd t1, 0x88(t0)
//map HT: PCI MEM : 0x90000e00_40000000 <-- 0x40000000 ~ 0x7fffffff
dli t1, 0x0000000040000000
sd t1, 0x10(t0)
dli t1, 0xffffffffc0000000
sd t1, 0x50(t0)
dli t1, 0x00001e00400000f7
sd t1, 0x90(t0)
//map HT: PCI MEM : 0x90001e00_00000000 <-- 0x90000e00_00000000 ~ 0x
dli t1, 0x00000e0000000000
sd t1, 0x18(t0)
dli t1, 0xffffff0000000000
sd t1, 0x58(t0)
dli t1, 0x00001e00000000f7
sd t1, 0x98(t0)
daddiu t0, t0, 0x100
bne t0, t2, 1b
nop
#endif

46
Targets/Bonito3a3000_7a/Bonito/start.S
View File

@ -461,7 +461,7 @@ bsp_start:
bal beep_off
nop
//setup 3A and 7A HT link here
//setup LS3A - 7A HT link start...
//check 3A clksel setting
li t0, 0xbfe00190
lw a0, 0x4(t0)
@ -470,7 +470,7 @@ bsp_start:
nop
#ifdef CHECK_HT_PLL_MODE
TTYDBG("Warning: 3A HT in hard freq mode, please modify clksel[7].\r\n")
dli a0, 0x40000000
dli a0, 0x4000000
1:
dsub a0, a0, 1
bnez a0, 1b
@ -489,7 +489,7 @@ bsp_start:
nop
#ifdef CHECK_HT_PLL_MODE
TTYDBG("Warning: 7A HT in hard freq mode, please modify clksel[7].\r\n")
dli a0, 0x40000000
dli a0, 0x4000000
1:
dsub a0, a0, 1
bnez a0, 1b
@ -582,44 +582,22 @@ bsp_start:
dli a0, 0x90000e0000000000
move a1, t2
move a2, t3
bal setup_ht_link
bal config_ht_link
nop
beqz v0, 8f
nop
move t8, v0
TTYDBG("!!!!!Node 0 LS3A-7A link fail. fail status: ")
move a0, t8
bal hexserial
nop
TTYDBG("\r\nfrequency @ ")
dsrl a0, t3, 32
bal hexserial
nop
move a0, t3
bal hexserial
nop
1:
b 1b
nop
8:
TTYDBG("========Node 0 LS3A-7A linkup @")
dsrl a0, t3, 32
bal hexserial
nop
move a0, t3
bal hexserial
nop
#ifdef LS7A_2WAY_CONNECT
dli a0, 0x90001e0000000000
move a1, t2
move a2, t3
bal setup_ht_link
bal config_ht_link
nop
#endif
bal reset_ht_link
nop
beqz v0, 8f
nop
move t8, v0
TTYDBG("!!!!!Node 1 LS3A-7A link fail. fail status: ")
TTYDBG("!!!LS3A-7A link fail. fail status: ")
move a0, t8
bal hexserial
nop
@ -627,8 +605,8 @@ bsp_start:
b 1b
nop
8:
TTYDBG("========Node 1 LS3A-7A linkup.\r\n")
#endif
TTYDBG("LS3A-7A linkup.")
//setup LS3A - 7A HT link done.
//#define TEST_REBOOT
#ifdef TEST_REBOOT

10
Targets/Bonito3a3000_7a/Bonito/tgt_machdep.c
View File

@ -261,12 +261,12 @@ void tgt_devconfig()
fb_init(fbaddress, ioaddress);
printf("fb_init done\n");
#ifndef MULTI_CHIP
/* For dvo1 */
gpioi2c_config_ch7034();
/* For dvo0 */
gpioi2c_config_sii9022a();
#endif
} else {
printf("vga bios init failed, rc=%d\n",rc);
}
@ -1374,7 +1374,11 @@ struct board_devices *board_devices_info()
struct board_devices *bd = &g_board;
strcpy(bd->name,"Loongson-3A3000-7A");
#ifdef MULTI_CHIP
strcpy(bd->name,"Loongson-3A3000-7A-Dev-2way");
#else
strcpy(bd->name,"Loongson-3A3000-7A-Dev-1way");
#endif
bd->num_resources = 10;
return bd;

11
Targets/Bonito3a3000_7a/conf/Bonito.3a3000_7a
View File

@ -38,18 +38,17 @@ option LS3_HT # Enable the IO cache coherent of HT
#option MCP68_IDE # Enable the MCP68 IDE 0 channel
#option USE_LPC_UART
#option USE_SB700_LPC_UART
#option MULTI_CHIP
option MULTI_CHIP
option BOOTCORE_ID=0
#option RESERVED_COREMASK=0xff00 #for 3a3000_2w_7a
option RESERVED_COREMASK=0xfff0 #for 3a3000_7a
option RESERVED_COREMASK=0xff00 #for 3a3000_2w_7a
#option RESERVED_COREMASK=0xfff0 #for 3a3000_7a
option SHUTDOWN_MASK=0x0000
option LOONGSON_3ASINGLE
#option LOONGSON_3ASINGLE
option LOONGSON_3ASERVER
#option LOONGSON_3A92W
option BONITO_33M
option BOOT_PARAM
#option LOONGSON_3ASERVER
#option LOONGSON_3A7A_2WAY
option LS7A #for 7A
#select amd_780e

2
pmon/arch/mips/ls7a/ls3a7a_ht_init.S
View File

@ -88,7 +88,7 @@ ls3a7a_ht_init:
sw a0, (LS3A_HT_RX_CACHE_WIN0_OFFSET+0)(t0)
//open RX window: 0x0 ~ 0x7f_ffff_ffff
li a0, 0x00008000
li a0, 0x0000e000
sw a0, (LS3A_HT_RX_CACHE_WIN1_OFFSET+4)(t0)
li a0, 0x80000000
sw a0, (LS3A_HT_RX_CACHE_WIN1_OFFSET+0)(t0)

262
pmon/arch/mips/ls7a/ls3a7a_setup_ht_link.S
View File

@ -1,24 +1,18 @@
//************************************
// setup_ht_link
// author: chenxk
// date: 2017.11.05
// set up the link between CPU and PCH.
// date: 2017.11.14
// set up the link between CPU and PCH include two steps:
// 1. config_ht_link(set link parameters)
// 2. reset_ht_link(reset to make new configure effect)
//
// for CPU: LS3A2000/LS3A3000
// for PCH: LS7A1000
// reset when linkup fail seems useless.
//************************************
#include "ht.h"
#define HT1_LINKUP_FAIL_OFFSET 0
#define HT1_LINKDOWN_FAIL_OFFSET 1
#define HT1_CPU_CRC_FAIL_OFFSET 4
#define HT1_CPU_CRC_ERR_OFFSET 5
#define HT1_SB_CRC_FAIL_OFFSET 6
#define HT1_SB_CRC_ERR_OFFSET 7
######################################################
.global setup_ht_link
.ent setup_ht_link
.global config_ht_link
.ent config_ht_link
.set noreorder
.set mips3
//input:
@ -33,21 +27,15 @@
//[63:32]: 7A side ht_pllcfg[31:0]
//[31: 0]: 3A side ht_pllcfg[31:0]
//output:
//v0: setup_link status:
//0: success
//!0: fail
//register usage:
//t0: 3A HT cntl register base address
//t1: 7A HT cntl register base address
//t5, t6: tmp variable
//t2: store a1
//t3: store a2
//t8: store return value
//s1: store ra
setup_ht_link:
config_ht_link:
move s1, ra
@ -57,7 +45,6 @@ setup_ht_link:
daddu t1, t1, a0
move t2, a1
move t3, a2
move t8, $0
#ifdef PRINT_HT1_REG //Print all HT registers
TTYDBG("LS3A HT registers are:\r\n")
@ -125,20 +112,6 @@ setup_ht_link:
and a0, t2, 0x1
beqz a0, 8f
nop
//set 7A side HT
//TTYDBG("Set HT to 1.0 mode\r\n")
//lw a0, 0x4c(t1)
//li a1, (0xff<<0)
//not a1, a1
//and a0, a0, a1
//li a1, (0x20<<0)
//or a0, a0, a1
//sw a0, 0x4c(t1)
//lw a0, 0x4c(t1)
//bal hexserial
//nop
//TTYDBG("\r\n")
TTYDBG("Set 7A HT width\r\n")
lw a0, 0x44(t1)
@ -296,8 +269,101 @@ setup_ht_link:
nop
TTYDBG("\r\n")
4:
8:
#endif
move ra, s1
jr ra
nop
.end config_ht_link
######################################################
#define HT1_LINKUP_FAIL_OFFSET 0
#define HT1_LINKDOWN_FAIL_OFFSET 1
#define HT1_CPU_CRC_FAIL_OFFSET 4
#define HT1_CPU_CRC_ERR_OFFSET 5
#define HT1_SB_CRC_FAIL_OFFSET 6
#define HT1_SB_CRC_ERR_OFFSET 7
#define N1_OFFSET 8
.global reset_ht_link
.ent reset_ht_link
.set noreorder
.set mips3
// support 1 way and 2 way connection.
// Because of the stupid bug, we have to keep all HT1 link reset together.
//
// reset multi-times seems useless when linkup fail.
//output:
//v0: setup_link status:
//0: success
//!0: fail
//register usage:
//t0: Node 0 LS3A HT1 cntl register base address
//t1: Node 0 LS7A HT1 cntl register base address
//t2: Node 1 LS3A HT1 cntl register base address
//t3: Node 1 LS7A HT1 cntl register base address
//t5, t6: tmp variable
//t8: store return value
//s1: store ra
reset_ht_link:
move s1, ra
dli t0, 0x90000efdfb000000
dli t1, 0x90000efdfe000000
dli t2, 0x90001efdfb000000
dli t3, 0x90001efdfe000000
move t8, $0
#ifdef LS7A_2WAY_CONNECT
TTYDBG("Reset Node 1 HT1 bus\r\n")
lb a0, 0x3e(t2)
li a1, 0x40
or a0, a0, a1
sb a0, 0x3e(t2)
lw a0, 0x3c(t2)
bal hexserial
nop
TTYDBG("\r\n")
//wait until HT link down
TTYDBG("Wait HT bus down.")
li t5, 0x1f
1:
TTYDBG(">")
addi t5, t5, -1
bnez t5, 2f
nop
TTYDBG("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b=")
TTYDBG("Wait HT bus down fail!\r\n")
//failed more than given time, set fail mark and break
or t8, t8, (0x1 << HT1_LINKDOWN_FAIL_OFFSET + N1_OFFSET)
b 88f
nop
2:
lw a0, 0x44(t2)
li a1, 0x20
and a0, a0, a1
bnez a0, 1b
nop
TTYDBG("\r\n")
lw a0, 0x44(t2)
bal hexserial
nop
TTYDBG("\r\n")
#endif
TTYDBG("Reset HT bus\r\n")
TTYDBG("Reset Node 0 HT1 bus\r\n")
lb a0, 0x3e(t0)
li a1, 0x40
or a0, a0, a1
@ -334,7 +400,7 @@ setup_ht_link:
nop
TTYDBG("\r\n")
TTYDBG("Dereset HT bus\r\n")
TTYDBG("Dereset Node 0 HT1 bus\r\n")
lb a0, 0x3e(t0)
li a1, 0x40
not a1, a1
@ -370,11 +436,48 @@ setup_ht_link:
bal hexserial
nop
TTYDBG("\r\n")
8:
#ifdef LS7A_2WAY_CONNECT
TTYDBG("Dereset Node 1 HT1 bus\r\n")
lb a0, 0x3e(t2)
li a1, 0x40
not a1, a1
and a0, a0, a1
sb a0, 0x3e(t2)
lw a0, 0x3c(t2)
bal hexserial
nop
TTYDBG("\r\n")
//wait until HT link up
TTYDBG("Wait HT bus up.")
li t5, 0x1f
1:
TTYDBG(">")
addi t5, t5, -1
bnez t5, 2f
nop
TTYDBG("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b=")
TTYDBG("Wait HT bus up fail!\r\n")
or t8, t8, (0x1 << HT1_LINKUP_FAIL_OFFSET + N1_OFFSET)
b 88f
nop
2:
lw a0, 0x44(t2)
li a1, 0x20
and a0, a0, a1
beqz a0, 1b
nop
TTYDBG("\r\n")
lw a0, 0x44(t2)
bal hexserial
nop
TTYDBG("\r\n")
#endif
#ifdef PRINT_HT1_REG //Print all HT registers
TTYDBG("LS3A HT registers are:\r\n")
TTYDBG("LS3A Node 0 HT1 registers are:\r\n")
move t5, t0
daddu t6, t5, (LS3A_HT_REG_NUM * 4)
1:
@ -412,7 +515,7 @@ setup_ht_link:
#endif
#if 1//Check if CRC error bit set and reset it
TTYDBG("Checking CPU HT CRC error.\r\n")
TTYDBG("Checking Node 0 HT1 CRC error.\r\n")
li t5, 0x1f
1:
TTYDBG(">")
@ -472,35 +575,98 @@ setup_ht_link:
b 1b
nop
3:
#ifdef LS7A_2WAY_CONNECT
TTYDBG("Checking Node 1 HT1 CRC error.\r\n")
li t5, 0x1f
1:
TTYDBG(">")
addi t5, t5, -1
bnez t5, 2f
nop
TTYDBG("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b=")
or t8, t8, (0x1 << HT1_CPU_CRC_FAIL_OFFSET + N1_OFFSET)
b 88f
nop
2:
lw a0, 0x44(t2)
li a1, 0x300
and a0, a0, a1
beqz a0, 3f
nop
or t8, t8, (0x1 << HT1_CPU_CRC_ERR_OFFSET + N1_OFFSET)
TTYDBG("\r\nCRC error found\r\n")
lw a0, 0x44(t2)
bal hexserial
nop
lw a0, 0x44(t2)
li a1, 0xfffffcff
and a0, a0, a1
sw a0, 0x44(t2)
b 1b
nop
3:
TTYDBG("Checking Bridge HT CRC error bit.\r\n")
li t5, 0x1f
1:
TTYDBG(">")
addi t5, t5, -1
bnez t5, 2f
nop
TTYDBG("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b=")
or t8, t8, (0x1 << HT1_SB_CRC_FAIL_OFFSET + N1_OFFSET)
b 88f
nop
2:
lw a0, 0x44(t3)
li a1, 0x300
and a0, a0, a1
beqz a0, 3f
nop
or t8, t8, (0x1 << HT1_SB_CRC_ERR_OFFSET + N1_OFFSET)
TTYDBG("\r\nCRC error found\r\n")
lw a0, 0x44(t3)
bal hexserial
nop
lw a0, 0x44(t3)
li a1, 0xfffffcff
and a0, a0, a1
sw a0, 0x44(t3)
b 1b
nop
3:
#endif
#endif
88:
#ifdef DEBUG_HT1
TTYDBG("\r\nCPU HT reg: 0x44: ")
TTYDBG("\r\nNode 0 HT1 reg: 0x44: ")
lw a0, 0x44(t0)
bal hexserial
nop
TTYDBG("\r\nCPU HT reg: 0x54: ")
TTYDBG("\r\nNode 0 HT1 reg: 0x54: ")
lw a0, 0x54(t0)
bal hexserial
nop
TTYDBG("\r\nCPU HT reg: 0x120: ")
TTYDBG("\r\nNode 0 HT1 reg: 0x120: ")
lw a0, 0x120(t0)
bal hexserial
nop
TTYDBG("\r\nCPU HT reg: 0x128: ")
TTYDBG("\r\nNode 0 HT1 reg: 0x128: ")
lw a0, 0x128(t0)
bal hexserial
nop
TTYDBG("\r\nCPU HT reg: 0x188: ")
TTYDBG("\r\nNode 0 HT1 reg: 0x188: ")
lw a0, 0x188(t0)
bal hexserial
nop
TTYDBG("\r\nCPU HT reg: 0x18c: ")
TTYDBG("\r\nNode 0 HT1 reg: 0x18c: ")
lw a0, 0x18c(t0)
bal hexserial
nop
TTYDBG("\r\nCPU HT reg: 0x190: ")
TTYDBG("\r\nNode 0 HT1 reg: 0x190: ")
lw a0, 0x190(t0)
bal hexserial
nop
@ -511,4 +677,4 @@ setup_ht_link:
move ra, s1
jr ra
nop
.end setup_ht_link
.end reset_ht_link

14
pmon/arch/mips/ls7a/ls7a_config.S
View File

@ -8,9 +8,13 @@
.set noreorder
.set mips3
ls7a_config_one_pll:
//input parameters:
//a0: pll address
//a1: pll value
//a2: div_refc
//output value:
//v0: 0: success; 1: fail.
move t7, ra
@ -65,10 +69,15 @@ ls7a_config_one_pll:
sw t1, 0x4(a0)
//poll lock signal
li v1, 0x1000
move v0, $0
li t2, (0x1 << LS7A_PLL_LOCK_OFFSET)
1:
lw t1, 0x4(a0)
and t1, t1, t2
subu v1, v1, 1
beqz v1, 1f
nop
beqz t1, 1b
nop
@ -77,7 +86,12 @@ ls7a_config_one_pll:
li t2, (0x7 << LS7A_PLL_SEL0_OFFSET)
or t1, t1, t2
sw t1, 0x4(a0)
b 2f
nop
1: //PLL lock fail
ori v0, v0, 1
2:
move ra, t7
jr ra
nop

44
pmon/arch/mips/ls7a/ls7a_init.S
View File

@ -92,13 +92,20 @@
#if 1
//configure 7A pll
//LS7A_PLL_VALUE: (LOOPC, DIV2, DIV1, DIV0)
//pcie, gmac, sata/usb
daddu a0, t0, CONF_PLL0_OFFSET
li a2, 0x4
li a1, LS7A_PLL_VALUE(80, 8, 16, 16)
bal ls7a_config_one_pll
nop
TTYDBG("LS7A PLL0 soft configure done.\r\n")
beqz v0, 1f
nop
TTYDBG("!!!LS7A PLL0 soft configure fail.\r\n")
2:
b 2b
nop
1:
//gpu, gmem, dc
daddu a0, t0, CONF_PLL1_OFFSET
@ -106,7 +113,13 @@
li a1, LS7A_PLL_VALUE(100, 5, 4, 10)
bal ls7a_config_one_pll
nop
TTYDBG("LS7A PLL1 soft configure done.\r\n")
beqz v0, 1f
nop
TTYDBG("!!!LS7A PLL1 soft configure fail.\r\n")
2:
b 2b
nop
1:
//flex, node, hda bitclk
daddu a0, t0, CONF_PLL2_OFFSET
@ -114,21 +127,39 @@
li a1, LS7A_PLL_VALUE(96, 72, 6, 100)
bal ls7a_config_one_pll
nop
TTYDBG("LS7A PLL2 soft configure done.\r\n")
beqz v0, 1f
nop
TTYDBG("!!!LS7A PLL2 soft configure fail.\r\n")
2:
b 2b
nop
1:
daddu a0, t0, CONF_PLL3_OFFSET
li a2, 0x5
li a1, LS7A_PLL_VALUE(57, 30, 30, 30)
bal ls7a_config_one_pll
nop
TTYDBG("LS7A PLL3 soft configure done.\r\n")
beqz v0, 1f
nop
TTYDBG("!!!LS7A PLL3 soft configure fail.\r\n")
2:
b 2b
nop
1:
daddu a0, t0, CONF_PLL4_OFFSET
li a2, 0x5
li a1, LS7A_PLL_VALUE(57, 30, 30, 30)
bal ls7a_config_one_pll
nop
TTYDBG("LS7A PLL4 soft configure done.\r\n")
beqz v0, 1f
nop
TTYDBG("!!!LS7A PLL4 soft configure fail.\r\n")
2:
b 2b
nop
1:
TTYDBG("LS7A pll configure done.\r\n")
#endif
@ -146,8 +177,7 @@
#endif
//init 7a hardware
#if 1
//configure to obey strict HT order
#if 1 //configure to obey strict HT order
lw t1, 0x414(t0)
li t2, (0x7ffff << 0)
or t1, t1, t2

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