From ed090ea5ce1362d32c8e74b4b5b7c9fac7af265d Mon Sep 17 00:00:00 2001
From: wusheng <wusheng@loongson.cn>
Date: Tue, 26 Feb 2019 14:58:58 +0800
Subject: [PATCH] Fix bug caused by commit
 2dec78933f7152e0a25e8b8a1e15edae587db9b6 3a3000 tRFC reconfig and other
 leveling modified

Change-Id: Ia91782cb5f3d81f21d7595be479c9f320db89b64
---
 Targets/Bonito3a82h/Bonito/start.S            | 21 +++++++------------
 Targets/Bonito3a82w/Bonito/start.S            | 20 +++++++-----------
 .../Bonito3a84w/Bonito/loongson3_clksetting.S | 18 +++++++---------
 Targets/Bonito3a8780e/Bonito/start.S          | 12 +++++------
 Targets/Bonito3a92h/Bonito/start.S            |  6 ++++++
 .../Bonito3a92w/Bonito/loongson3_clksetting.S |  5 +++++
 .../Bonito3a94w/Bonito/loongson3_clksetting.S |  6 ++++++
 Targets/Bonito3a9780e/Bonito/start.S          |  7 +++++++
 pmon/arch/mips/mm/ls3A8_ddr_config.S          |  2 +-
 9 files changed, 55 insertions(+), 42 deletions(-)

diff --git a/Targets/Bonito3a82h/Bonito/start.S b/Targets/Bonito3a82h/Bonito/start.S
index 4e5303c6..57fb1c32 100644
--- a/Targets/Bonito3a82h/Bonito/start.S
+++ b/Targets/Bonito3a82h/Bonito/start.S
@@ -359,19 +359,14 @@ gs_2f_v3_ddr2_cfg:
 #define SOFT_CLKSEL
 #ifdef SOFT_CLKSEL
 
-//#define DDR_LOOPC    64 //264MHz
-//#define DDR_LOOPC    72 //300MHz
-//#define DDR_LOOPC    80 //330MHz
-//#define DDR_LOOPC  48 //400MHz
-//#define DDR_LOOPC  28 //466MHz
-//#define DDR_LOOPC  60 //500MHz
-#define DDR_LOOPC  64 //533MHz
-//#define DDR_LOOPC  34 //566MHz
-//#define DDR_LOOPC  72 //600MHz
-//#define DDR_LOOPC  38 //633MHz
-#define DDR_REFC   1
-//#define DDR_DIV    8
-#define DDR_DIV    4
+#define DDR_FREQ    528
+#define DDR_REFC    1   //do not modify
+#if (DDR_FREQ < 400)
+#define DDR_DIV     8
+#else
+#define DDR_DIV     4
+#endif
+#define DDR_LOOPC  (DDR_FREQ*DDR_DIV/33)   //48 //396MHz
 
 //#define L1_LOOPC    68//850
 #define L1_LOOPC    64//800
diff --git a/Targets/Bonito3a82w/Bonito/start.S b/Targets/Bonito3a82w/Bonito/start.S
index 6cb36eef..69e3e7a5 100644
--- a/Targets/Bonito3a82w/Bonito/start.S
+++ b/Targets/Bonito3a82w/Bonito/start.S
@@ -388,18 +388,14 @@ gs_2f_v3_ddr2_cfg:
 #define SOFT_CLKSEL
 #ifdef SOFT_CLKSEL
 
-//#define DDR_LOOPC	 48//200MHz
-//#define DDR_LOOPC	 72//300MHz
-//#define DDR_LOOPC  96 //400MHz
-//#define DDR_LOOPC  28 //466MHz
-//#define DDR_LOOPC  60 //500MHz
-#define DDR_LOOPC  64 //533MHz
-//#define DDR_LOOPC  34 //566MHz
-//#define DDR_LOOPC  72 //600MHz
-//#define DDR_LOOPC  76 //633MHz
-//#define DDR_LOOPC  80 //667MHz
-#define DDR_REFC   1
-#define DDR_DIV    4
+#define DDR_FREQ    528
+#define DDR_REFC    1   //do not modify
+#if (DDR_FREQ < 400)
+#define DDR_DIV     8
+#else
+#define DDR_DIV     4
+#endif
+#define DDR_LOOPC  (DDR_FREQ*DDR_DIV/33)   //48 //396MHz
 
 // L1_* define both CPU and Node freq simutanleously
 #define L1_LOOPC    80//1000@25MHz
diff --git a/Targets/Bonito3a84w/Bonito/loongson3_clksetting.S b/Targets/Bonito3a84w/Bonito/loongson3_clksetting.S
index 138f4283..4d87eb6d 100644
--- a/Targets/Bonito3a84w/Bonito/loongson3_clksetting.S
+++ b/Targets/Bonito3a84w/Bonito/loongson3_clksetting.S
@@ -10,16 +10,14 @@ ATTENTION:
 
 #ifdef SOFT_CLKSEL
 
-//#define DDR_LOOPC  48 //400MHz
-//#define DDR_LOOPC  56 //466MHz
-//#define DDR_LOOPC  60 //500MHz
-#define DDR_LOOPC  64 //533MHz
-//#define DDR_LOOPC  68 //566MHz
-//#define DDR_LOOPC  72 //600MHz
-//#define DDR_LOOPC  76 //633MHz
-//#define DDR_LOOPC  80 //667MHz
-#define DDR_REFC   1
-#define DDR_DIV    4
+#define DDR_FREQ    528
+#define DDR_REFC    1   //do not modify
+#if (DDR_FREQ < 400)
+#define DDR_DIV     8
+#else
+#define DDR_DIV     4
+#endif
+#define DDR_LOOPC  (DDR_FREQ*DDR_DIV/33)   //48 //396MHz
 
 // L1_* define both CPU and Node freq simutanleously
 //#define L1_LOOPC    80//1000@25MHz
diff --git a/Targets/Bonito3a8780e/Bonito/start.S b/Targets/Bonito3a8780e/Bonito/start.S
index 77eb3321..02a4e957 100644
--- a/Targets/Bonito3a8780e/Bonito/start.S
+++ b/Targets/Bonito3a8780e/Bonito/start.S
@@ -367,12 +367,12 @@ gs_2f_v3_ddr2_cfg:
 #define SOFT_CLKSEL
 #ifdef SOFT_CLKSEL
 
-//#define DDR_LOOPC  80 //667Mhz
-//#define DDR_LOOPC  72 //600
-//#define DDR_LOOPC  60 //500MHz
-#define DDR_LOOPC  48 //400MHz
-#define DDR_REFC   1
-#define DDR_DIV    4
+#define DDR_FREQ    396
+//#define DDR_FREQ    495
+//#define DDR_FREQ    594
+#define DDR_REFC    1   //do not modify
+#define DDR_DIV     4
+#define DDR_LOOPC  (DDR_FREQ*DDR_DIV/33)   //48 //396MHz
 
 // L1_* define both CPU and Node freq simutanleously
 //#define L1_LOOPC    80//1000
diff --git a/Targets/Bonito3a92h/Bonito/start.S b/Targets/Bonito3a92h/Bonito/start.S
index 4369f37e..09ca3c41 100644
--- a/Targets/Bonito3a92h/Bonito/start.S
+++ b/Targets/Bonito3a92h/Bonito/start.S
@@ -455,6 +455,12 @@ gs_2f_v3_ddr2_cfg:
 #define L1_REFC   1
 #endif
 
+#ifdef DDR_SEL_ST 
+#define DDR_FREQ (L1_LOOPC/DDR_REFC)
+#else
+#define DDR_FREQ  (DDR_LOOPC*33/DDR_DIV/DDR_REFC)  
+#endif
+
 #define BYPASS_CORE 0x0
 #define BYPASS_NODE 0x0
 #define BYPASS_L1   0x0
diff --git a/Targets/Bonito3a92w/Bonito/loongson3_clksetting.S b/Targets/Bonito3a92w/Bonito/loongson3_clksetting.S
index ae58bcc4..84a09288 100644
--- a/Targets/Bonito3a92w/Bonito/loongson3_clksetting.S
+++ b/Targets/Bonito3a92w/Bonito/loongson3_clksetting.S
@@ -80,6 +80,11 @@ ATTENTION:
 #endif
 #endif
 
+#ifdef DDR_SEL_ST 
+#define DDR_FREQ (L1_LOOPC/DDR_REFC)
+#else
+#define DDR_FREQ  (DDR_LOOPC*33/DDR_DIV/DDR_REFC)  
+#endif
 #define BYPASS_CORE 0x0
 #define BYPASS_NODE 0x0
 #define BYPASS_L1   0x0
diff --git a/Targets/Bonito3a94w/Bonito/loongson3_clksetting.S b/Targets/Bonito3a94w/Bonito/loongson3_clksetting.S
index b7dbe115..12bbc314 100644
--- a/Targets/Bonito3a94w/Bonito/loongson3_clksetting.S
+++ b/Targets/Bonito3a94w/Bonito/loongson3_clksetting.S
@@ -79,6 +79,12 @@ ATTENTION:
 #endif
 #endif
 
+#ifdef DDR_SEL_ST 
+#define DDR_FREQ (L1_LOOPC/DDR_REFC)
+#else
+#define DDR_FREQ  (DDR_LOOPC*33/DDR_DIV/DDR_REFC)  
+#endif
+
 #define BYPASS_CORE 0x0
 #define BYPASS_NODE 0x0
 #define BYPASS_L1   0x0
diff --git a/Targets/Bonito3a9780e/Bonito/start.S b/Targets/Bonito3a9780e/Bonito/start.S
index 4632cabc..b6d123f2 100644
--- a/Targets/Bonito3a9780e/Bonito/start.S
+++ b/Targets/Bonito3a9780e/Bonito/start.S
@@ -409,6 +409,7 @@ gs_2f_v3_ddr2_cfg:
 #define PLL_L1_LOCKED ((ST_PLL << 17) | (LS_PLL << 16))
 
 #define DDR_SEL_ST 1
+
 //#define REF_33M
 //#define REF_100M
 #ifdef REF_100M
@@ -456,6 +457,12 @@ gs_2f_v3_ddr2_cfg:
 #endif
 #define 	FREQ 1200
 
+#ifdef DDR_SEL_ST 
+#define DDR_FREQ (L1_LOOPC/DDR_REFC)
+#else
+#define DDR_FREQ  (DDR_LOOPC*33/DDR_DIV/DDR_REFC)  
+#endif
+
 #define BYPASS_CORE 0x0
 #define BYPASS_NODE 0x0
 #define BYPASS_L1   0x0
diff --git a/pmon/arch/mips/mm/ls3A8_ddr_config.S b/pmon/arch/mips/mm/ls3A8_ddr_config.S
index 25ecba79..93fe7380 100644
--- a/pmon/arch/mips/mm/ls3A8_ddr_config.S
+++ b/pmon/arch/mips/mm/ls3A8_ddr_config.S
@@ -153,7 +153,7 @@ mc_init:
     nop
     dla     a2, ddr3_RDIMM_reg_data_mc1
 21:
-#if 1//def  MULTI_NODE_DDR_PARAM
+#ifdef  MULTI_NODE_DDR_PARAM
     GET_NODE_ID_a1
     beqz    a1, 4f
     nop