Merge "Fix bug caused by commit 2dec78933f 3a3000 tRFC reconfig and other leveling modified"

Targets/Bonito3a82h/Bonito/start.S

@@ -359,19 +359,14 @@ gs_2f_v3_ddr2_cfg:
 #define SOFT_CLKSEL
 #ifdef SOFT_CLKSEL
 
-//#define DDR_LOOPC    64 //264MHz
+#define DDR_FREQ    528
-//#define DDR_LOOPC    72 //300MHz
+#define DDR_REFC    1   //do not modify
-//#define DDR_LOOPC    80 //330MHz
+#if (DDR_FREQ < 400)
-//#define DDR_LOOPC  48 //400MHz
+#define DDR_DIV     8
-//#define DDR_LOOPC  28 //466MHz
+#else
-//#define DDR_LOOPC  60 //500MHz
+#define DDR_DIV     4
-#define DDR_LOOPC  64 //533MHz
+#endif
-//#define DDR_LOOPC  34 //566MHz
+#define DDR_LOOPC  (DDR_FREQ*DDR_DIV/33)   //48 //396MHz
-//#define DDR_LOOPC  72 //600MHz
-//#define DDR_LOOPC  38 //633MHz
-#define DDR_REFC   1
-//#define DDR_DIV    8
-#define DDR_DIV    4
 
 //#define L1_LOOPC    68//850
 #define L1_LOOPC    64//800

Targets/Bonito3a82w/Bonito/start.S

@@ -388,18 +388,14 @@ gs_2f_v3_ddr2_cfg:
 #define SOFT_CLKSEL
 #ifdef SOFT_CLKSEL
 
-//#define DDR_LOOPC	 48//200MHz
+#define DDR_FREQ    528
-//#define DDR_LOOPC	 72//300MHz
+#define DDR_REFC    1   //do not modify
-//#define DDR_LOOPC  96 //400MHz
+#if (DDR_FREQ < 400)
-//#define DDR_LOOPC  28 //466MHz
+#define DDR_DIV     8
-//#define DDR_LOOPC  60 //500MHz
+#else
-#define DDR_LOOPC  64 //533MHz
+#define DDR_DIV     4
-//#define DDR_LOOPC  34 //566MHz
+#endif
-//#define DDR_LOOPC  72 //600MHz
+#define DDR_LOOPC  (DDR_FREQ*DDR_DIV/33)   //48 //396MHz
-//#define DDR_LOOPC  76 //633MHz
-//#define DDR_LOOPC  80 //667MHz
-#define DDR_REFC   1
-#define DDR_DIV    4
 
 // L1_* define both CPU and Node freq simutanleously
 #define L1_LOOPC    80//1000@25MHz

Targets/Bonito3a84w/Bonito/loongson3_clksetting.S

@@ -10,16 +10,14 @@ ATTENTION:
 
 #ifdef SOFT_CLKSEL
 
-//#define DDR_LOOPC  48 //400MHz
+#define DDR_FREQ    528
-//#define DDR_LOOPC  56 //466MHz
+#define DDR_REFC    1   //do not modify
-//#define DDR_LOOPC  60 //500MHz
+#if (DDR_FREQ < 400)
-#define DDR_LOOPC  64 //533MHz
+#define DDR_DIV     8
-//#define DDR_LOOPC  68 //566MHz
+#else
-//#define DDR_LOOPC  72 //600MHz
+#define DDR_DIV     4
-//#define DDR_LOOPC  76 //633MHz
+#endif
-//#define DDR_LOOPC  80 //667MHz
+#define DDR_LOOPC  (DDR_FREQ*DDR_DIV/33)   //48 //396MHz
-#define DDR_REFC   1
-#define DDR_DIV    4
 
 // L1_* define both CPU and Node freq simutanleously
 //#define L1_LOOPC    80//1000@25MHz

Targets/Bonito3a8780e/Bonito/start.S

@@ -367,12 +367,12 @@ gs_2f_v3_ddr2_cfg:
 #define SOFT_CLKSEL
 #ifdef SOFT_CLKSEL
 
-//#define DDR_LOOPC  80 //667Mhz
+#define DDR_FREQ    396
-//#define DDR_LOOPC  72 //600
+//#define DDR_FREQ    495
-//#define DDR_LOOPC  60 //500MHz
+//#define DDR_FREQ    594
-#define DDR_LOOPC  48 //400MHz
+#define DDR_REFC    1   //do not modify
-#define DDR_REFC   1
+#define DDR_DIV     4
-#define DDR_DIV    4
+#define DDR_LOOPC  (DDR_FREQ*DDR_DIV/33)   //48 //396MHz
 
 // L1_* define both CPU and Node freq simutanleously
 //#define L1_LOOPC    80//1000

Targets/Bonito3a92h/Bonito/start.S

@@ -455,6 +455,12 @@ gs_2f_v3_ddr2_cfg:
 #define L1_REFC   1
 #endif
 
+#ifdef DDR_SEL_ST 
+#define DDR_FREQ (L1_LOOPC/DDR_REFC)
+#else
+#define DDR_FREQ  (DDR_LOOPC*33/DDR_DIV/DDR_REFC)  
+#endif
+
 #define BYPASS_CORE 0x0
 #define BYPASS_NODE 0x0
 #define BYPASS_L1   0x0

Targets/Bonito3a92w/Bonito/loongson3_clksetting.S

@@ -80,6 +80,11 @@ ATTENTION:
 #endif
 #endif
 
+#ifdef DDR_SEL_ST 
+#define DDR_FREQ (L1_LOOPC/DDR_REFC)
+#else
+#define DDR_FREQ  (DDR_LOOPC*33/DDR_DIV/DDR_REFC)  
+#endif
 #define BYPASS_CORE 0x0
 #define BYPASS_NODE 0x0
 #define BYPASS_L1   0x0

Targets/Bonito3a94w/Bonito/loongson3_clksetting.S

@@ -79,6 +79,12 @@ ATTENTION:
 #endif
 #endif
 
+#ifdef DDR_SEL_ST 
+#define DDR_FREQ (L1_LOOPC/DDR_REFC)
+#else
+#define DDR_FREQ  (DDR_LOOPC*33/DDR_DIV/DDR_REFC)  
+#endif
+
 #define BYPASS_CORE 0x0
 #define BYPASS_NODE 0x0
 #define BYPASS_L1   0x0

Targets/Bonito3a9780e/Bonito/start.S

@@ -409,6 +409,7 @@ gs_2f_v3_ddr2_cfg:
 #define PLL_L1_LOCKED ((ST_PLL << 17) | (LS_PLL << 16))
 
 #define DDR_SEL_ST 1
+
 //#define REF_33M
 //#define REF_100M
 #ifdef REF_100M
@@ -456,6 +457,12 @@ gs_2f_v3_ddr2_cfg:
 #endif
 #define 	FREQ 1200
 
+#ifdef DDR_SEL_ST 
+#define DDR_FREQ (L1_LOOPC/DDR_REFC)
+#else
+#define DDR_FREQ  (DDR_LOOPC*33/DDR_DIV/DDR_REFC)  
+#endif
+
 #define BYPASS_CORE 0x0
 #define BYPASS_NODE 0x0
 #define BYPASS_L1   0x0

pmon/arch/mips/mm/ls3A8_ddr_config.S

@@ -153,7 +153,7 @@ mc_init:
     nop
     dla     a2, ddr3_RDIMM_reg_data_mc1
 21:
-#if 1//def  MULTI_NODE_DDR_PARAM
+#ifdef  MULTI_NODE_DDR_PARAM
     GET_NODE_ID_a1
     beqz    a1, 4f
     nop