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13 Commits (086efdff8d85ec7c708af05465811a9cf9ad49ec)

Author SHA1 Message Date
wusheng c409911a49 Fixed some grammatical errors
4 years ago
wusheng 22dd2d1001 Add config of CORE_FREQ
6 years ago
wusheng fbd695c9c6 Change calculation of DDR_FREQ
6 years ago
wusheng ed090ea5ce Fix bug caused by commit 2dec78933f
6 years ago
xuwenrui 21460b17a0 Set HT-access cache/uncache before goto kernel
6 years ago
zhangbaoqi 81dd6a0497 enlarge ddr parameter number to 116 for 3a3000
7 years ago
liuzhijia 441da71a2a fix ddr pll config method for 3a9
7 years ago
Huang Shuai 3030990631 fix ddr pll config method for 3a9
7 years ago
Huang Shuai 11478f5582 unify DISABLE_DDR_A15 for 3A2000 and 3A3000
7 years ago
zhouxuezhi f32d90baab the 0xfdf8000000 address routing fixup.(node0/node1)
8 years ago
zhangbaoqi a6c96464f9 Add the ddr leveling for 3A3000 and 3A2000
8 years ago
zhangbaoqi 984de8613a Update the 3A3000 BBGEN configuration.
8 years ago
zhangbaoqi ad440a44a6 Add 3A3000 2 way support.
8 years ago