2.Modify 'cpu_type' according to the interface spec;
3.Initialize the member of DoSuspend(for 3A_SINGLE);
4.Add the spec version macro 'SPEC_VERS';
Change-Id: Ideb212d0c5e6f67506954a428642e21d53ccd0ce
relevancy:all branch.
1.
Targets/Bonito3a2h/Bonito/loongson3_HT_init_2h.S
Targets/Bonito3a82h/Bonito/loongson3_HT_init_2h.S
use window 5(no use before) for pcie graphic card in this patch
2.
pmon/cmds/pcicmds.c
sys/dev/pci/pciconf.c
sys/dev/pci/pcireg.h
sys/kern/subr_autoconf.c
sys/linux/io.h
x86emu/int10/generic.c
x86emu/int10/helper_exec.c
x86emu/int10/xf86int10.c
these file are basic code that modified in this path
3.
Targets/Bonito3a2h/Bonito/loongson3_HT_init_2h.S
Targets/Bonito3a2h/Bonito/tgt_machdep.c
Targets/Bonito3a2h/conf/Bonito.3a2h
Targets/Bonito3a2h/pci/ls2h_pci.c
Targets/Bonito3a2h/pci/pci_machdep.c
Targets/Bonito3a82h/Bonito/loongson3_HT_init_2h.S
Targets/Bonito3a82h/Bonito/tgt_machdep.c
Targets/Bonito3a82h/conf/Bonito.3a82h
Targets/Bonito3a82h/pci/ls2h_pci.c
Targets/Bonito3a82h/pci/pci_machdep.c
these files have only relate to 3a2h and 3a82h
Change-Id: I4a182bcbb8ca83f3fd34028145d362e7d2e683f0
Now ls3c2h platform support added, SPI flash/AHCI sata/Gmac/LPC/DC
are all OK, however there are still some work to do:
1.The command "ifaddr eth0" can't work, but "ifaddr syn0" works;
2.It hasn't been test with Dimms on con5 and con7;
3.CPU Frequency aren't calculated by RTC, it's fixed by program.
4.It cost ls3c a long time to wait Vide Ram intilized by ls2h, the
time should be shrunken largely.
Target: Bonito3c2h
Original code use 0xb8000000 as pci io base address, now use lpc io
base address as system io space. Besides, map 0xc0000000 to 0x40000000
to access video buffer on ls2h memory. Both pass test, but lpc kbd
work a little slow, it still need to be fixed.
NOTICE: if usb keyboard is used, the system pci io base need to be
changed as super io register base of south bridge.
Target:Bonito3a2h
1. Porting the 3A+690E x86emu module to 2G+690e platform and it works
correctly.
2. The HT frequency is adjusted to 800MHz.
3. The start address of PCI IO and memory space are adjusted according
to the 3A+690E platform.
4. The framebuffer address(0xb0000000) doesn't map through TLB. The
pcitlb.c is added in start.S, but it doesn't work.
5. Fix the IO-read/write base from 0xa000_0000 to 0x0000_0000 in
sys/linux/io.h.
Chong Qiao
zhouxuezhi
Zhigang Liang
Chenming
xiaqichao@ict.ac.cn
LI Wengang
CAI Wanwei
LIU Qi
CAI Wanwei
wanghuandong
root
cpu
root