All cores race spi bus when pmon bootup. In the case core0 fetch scache initialization instruction is very slowly.
Change-Id: I511aaa5ba5dc5337fbb8ef9c7396311814670f49
Target:3c780e
previous patch enable uncached accelerated when initializing
ecc ram, which reducing the pmon startup time, enable ecc by default
Change-Id: I64a1b4c3370024c81ec35164904ae30a24c63f89
3cserver, 3c780 and 3aserver
*. pcitlb.S mapped 33 instead of 32 tlb entry, the 33th of which mapped
cpu address 0x0 ~ 0x2000000 to physical address 0x8000 0000 ~ 0x8200 0000.
This COVERS NULL reference
*. ehci device was not enabled, so did not get bar initialized
during PCI bus enumeration
*. value in BAR0 is PCI address space, when need CPU address
tranformation
Change-Id: I576534bf61c7cd374dc2917454b8818e793851a6
*. use a read only regitser on 3b7 (read-write on 3b5) to
separate 3b5 from 3b7, and register k0 to 0 to indicate 3b7, not 0
to indication 3b5
*. pmon built for 3b7 can run on 3b5 board with bootcore
id to 1, while the same pmon binary runs on 3b7 board with bootcore
id to 0 with coresponding reserve core mask changed;
*. restore bootcore_id and reserved core mask to be compatible
with 3b5
*. power down all pll for 3b6 and 3b7
*. fix reboot and poweroff
*. fix glitch of ddr by define DDR_DLL_BYPASS
*. add CHANGE_VOLT to modify cpu core volt, not enabled by default
Change-Id: I97f087d4c31e8d694d4de1fa1f7d3b11f96166a6
1. put the Memory controller/chip-specific code into separate files.
2. Clean up the Bonito directory of some branch.
Change-Id: Idf6a4cab4fa1b9af3b819756d69da036f7cfac4a
*. 3a780e, 3aserver, 3c780e and 3cserver all use core 0 as BP
and boot all other core, this is compatiable to previous version;
*. When changing the BOOTCORE_ID and/or RESERVED_COREMASK, you
NEED "make cfg", to let it take effect
Change-Id: I8d6485407408baa969fce4f5473cabc4c2ee40af
the cause is the DMA request from 0xfe000000 ~ 0xff000000 is intercepted
and mistaken as MSI interrupt by the RS780E HT/PCI controller. Now exclude
this area for dma;
Change-Id: Ie8a61ee28d0b1d0ed23b2cfa5fa34fe820bbd56d
It displays in three plays:pmon bios, before pmon command line, `sysinfo mem` command. Now all of them are right.
Change-Id: I6eaf42f3df83a2603decf32cfea131a84f773374
*. fix boot error when DEBUG_DDR set, this is caused by early missing label
*. fix lock_scache without return;
Change-Id: I1d66d5f5c89c4e200623698ac3ef8d683868a6f0
Target: 3c780e
In this commit, when we pass emap entry with mem_size < 1MB, we set bit31 to 1
in mem_size to indicate the value in bit30~bit0 is Byte in unit, not MByte
the original 3c780e board has a board design flaw, and can not restart.
The second one fixed it with a dedicated chip generating resetting pulse connected
to GPIO10
Tested On 3B1500780e, 3a780e, 3aserver, both in pmon and kernel;
Original code only support boot form core0 and core4, now the
support for boot from core1 and other cores are supported. If you
need to boot from core'x', just change code in start.S as following:
1. every piece code starting with "#ifdef NODE1_BOOT"
2. code at "dli t0, CORE0_BUF0; #buf of cpu0 core0
li a1, SYSTEM_INIT_OK; sw a1, 0x0(t0)"
This pass test with bios boot from core0/core1 and core4, other mode
hasn't been test. By the way, kernel need to be changed if bios isn't
boot from core0.
Target:Bonito3c780e
Before if the pci device is not a multi-function device,it will still
initialize as a multi-function,Now fix it.
Target:Bonito3a780e Bonito3aserver Bonito3b780e Bonito3bserver
Bonito3c780e Bonito3cserver
Before: when power on some boards may stuck in leveling, we must press reset to make it ok. This patch do the reset process of MC by software.
Target: Bonito3c780e and Bonito3cserver
Original HT post write window size is too large, which causes usb
fail to work sometimes, now the window size is narrowed just for 128M
standing by. However, if the video memory is enlarged or UMA mode is
used, this windows need change again.
Thanks wanghuandong@loongson.cn
Target:Bonito3c780e
This patch fixed bugs as below:
1. Add beep if no memory found on node0 as bugzilla;
2. Change "em0" to "eth0" for command "devls" as bugzilla #639 described;
3. Display correct memory frequency as;
4. Display right memory size after "Del" key is pressed as bugzilla
#651 bug descirbed.
Target:Bonito3c780e
Original LS3C SPI driver code can't support fl_program() function, now
the function is ok, so the command "main" which will call fl_program()
is ok now.
Target:Bonito3c780e
1, fix the type 16 of Physical Memory Array and the type 17 of Memory Device.
2, fix the board name of Bonito3b1500 as "Loongson-3B-780E-1w-V0.9-demo".
3, fix the MAC address of uuid.
It pass test by dmidecode, now it is OK.
Target: Bonito3c780e
Original code only support boot from LPC, now boot from SPI flash
is OK. Original code only support some spi command such as "spiid",
"spiprogram" and "spierase", now 4K-erase and othe sector size is
support. Original spi driver code can't save enviroment variable,
Now enviroment variable can be saved, and command such as "set" and
"unset" are both OK. By the way, now more SPI flash types are supported,
user just add flash type in "pmon/dev/flashdev.c".
Target:Bonito3c780e
Xiaofu Meng
Huang Pei
Chen Xinke
wanghongmei
Chenming
Huang Shuai
Huang Pei
wanghonghu
Xiaqichao
Zhang Lihong
Wang Huandong
meiwenbin