The last PCIE auto-configure patch also fixes unexpected PCIE controller interrupt,
so it should not be ignored.
Change-Id: I619661511ad3cf2e22f6de7fc30c26b315ce0b3c
1. Do not override SATA PHY TX parameters by PHY control interface.
2. Add some debug info to ahci driver.
Change-Id: I5e000aed5cd914bf065211eea1328ac9b006dd4a
1. Now cmd "g" can add boot args to kernel.
2. Update FDT file coherent flag when it is a new ls2k.
3. Add cmd "erase_dtb" to erase dtb in flash, when useless dtb in it, kernel can boot by internal dtb.
4. Update dts file according kernel code which commit is 17eda7713d573df7af663e352dbd928650826dd8
5. You must use this code when kernel's commit is later than d7cbae624d10fd73825ae62cf250aa641a4f9d4d
Target:LS2K
Change-Id: I1a361efb9e880ea1ee1c8842ba934bc5b8a715c8
1. Add some code for new ls2k work well.
2. Enable coherent mode when it a new ls2k.
3. Make ls2k core1 wait smp in cache and in ram to support spi io modei, otherwise cause cmd (load -rf ...) error.
Change-Id: I169af27b17fb5d55b590f20c9a9d4a019d27cc81
1. The last commit(ac2f3ae6577602a870994c4e649c17f6db0560c3) modify the default PIX1 clock freqeuency
and cause the DVO1 display fail which proves the DC driver has bugs in PIX clock configure.
Currently, we modify the PIX1 clock freq to support 800x600 as default setting and keep the DC driver
from touching it. I will fix it later.
2. modify the HT bus back to HT3.0 mode and enable the soft freq configure which has been proven safe.
Change-Id: Ia4f0b081897732e3abb093b0a6893ecbfef7ab0d
1. Disable LPC CTRL/MEM/MMIO-BAR and set them to fix address.
CTRL: 0x10002000~0x10002fff;
MEM: 0x12000000~0x13ffffff;
IO: 0x18000000~0x1801ffff;
As the kernel need also be modified to reserve the low 128KB IO space and skip LPC BAR, so we disable board LPC now.
The GPU emu code is also modified.
2. Fix GPU/DC class code.
3. Disable 3A HT dw_write to support mask write and change the PIX pll default setting.
4. Fix WatchDog control defination.
5. Disable HT freq soft configure to fix possible HT link fail. And add check of HT pll lock.
Change-Id: I1ac3eaacc1fcda52b8ae1a0dbbdc0306833da7dc
1. Current code makes a mistake on PCIE_G0/G1/H PHY cfg address, which will
cause trouble if these three PORTs are not simultaneously enabled or disabled.
2. Modify the setup ht link process to wait HT link status infinately.
The start.S only print out the WARNING info(if any) but not stall the cpu.
Change-Id: Ic71b6e3db4c67063612e54a2ebdac362bec94438
The device will fixup the mps and mrrs size with the
minimal mps of the device and the bridge which belongs to.
The bridges should not fixup up mps and mrrs with its mrrs.
Change-Id: I01a90c6c7f69ac13bcea8efaf708afe106cdf7ce
1. change the HT CRC error reset to infinite loop to fix boot stuck.
2. modify ls7a_config.h to make change HT GEN 1/3 easy.
Change-Id: Ifc0e003d73a4203284947a843ac67126fad71dc5
Chen Xinke
Huang Shuai
zhangbaoqi
Xuefeng Li
田延辉
QiaoChong
xuwenrui
yijun