Target: Bonito3a84w
1. add debug HT RX signals in loongson3_HT_init.S (disabled)
2. change clock frequency to 800/533
3. change the DDR3 params and pass the memory test
4. fix the conf files (AUTO_DDR_CONFIG not supported yet)
5. fix the command files about kernel parameters
6. fix the i2c read by GPIO
Change-Id: I6ceba17f5f149e16615caec2fb9e0726d2840b3e
All cores race spi bus when pmon bootup. In the case core0 fetch scache initialization instruction is very slowly.
Change-Id: I511aaa5ba5dc5337fbb8ef9c7396311814670f49
Target:3c780e
Currently I only update the Bonito3a780e branch, if you want use it in other branches,
please port the code yourself.
Change-Id: I9e4374e7f8de8ab05aa28733e46841778899c937
previous patch enable uncached accelerated when initializing
ecc ram, which reducing the pmon startup time, enable ecc by default
Change-Id: I64a1b4c3370024c81ec35164904ae30a24c63f89
3cserver, 3c780 and 3aserver
*. pcitlb.S mapped 33 instead of 32 tlb entry, the 33th of which mapped
cpu address 0x0 ~ 0x2000000 to physical address 0x8000 0000 ~ 0x8200 0000.
This COVERS NULL reference
*. ehci device was not enabled, so did not get bar initialized
during PCI bus enumeration
*. value in BAR0 is PCI address space, when need CPU address
tranformation
Change-Id: I576534bf61c7cd374dc2917454b8818e793851a6
When the pciscan cammand was called the usb-ohci HcInterruptStatus register WDH
bit would be set,but the code do not clear it.
Change-Id: I3f83895ebac16ee64b5dd3341385d46080b2a6c9
1.Pmon can boot from SPI flash SST25VF032B.
2.The NVRAM_OFFS is defined as 0x7f000,
the gzrom.bin size should less than 0x7f000.
3.If add the nand flash function, the gzrom.bin
size will be out of 0x7f000.
4.The network card mac addr should be saved
into SPI flash, and acquired from SPI flash.
Change-Id: Id1f3e642a750ddeeb23f3b726e3f67a1ac855340
Target:LS2G + 1A + DDR3
1.Support uart, gmac on 2G, PS2, usb-ohci,
Sata, Vga, rtc and Pci net card devices.
2.The function of gmac on 2G needs modification
about PCB board.
3.The function of Sata needs modification
about Sata clock chip.
4.The series of 2G1A board include:
2G3+1A+DDR2, 2G5+1A+DDR2, 2G5+1A+DDR3.
The last one, PS2 is on 2G, the others are on 1A.
5.Modify Targets/Bonito2g1a/conf/Bonito.2g1a
Modify Targets/Bonito2g5ddr2_1a/conf/Bonito.2g5ddr2_1a
Modify pmon/dev/kbd.c and pmon/dev/kbd.h because of
the PS2 difference.
Target: LS2G5 + 1A + DDR3
Change-Id: I66f1e78e5672dd706331746c64c4db45371dfc00
1.Nandflash can be erased, read, written.
2.Could save kernel into nandflash.
3.Could load kernel form nandflash.
Target:2G5+1A+DDR2
Change-Id: Ic102439551c7cd90bba574aab477d8a502ff458c
ddr frequency for 2GQ/~3A5/~3B4.
2. Add example code to specify wrlvl_dq_dly separately when enable ARB_LEVEL in 3a780e branch.
3. Modify the PMON print MC parameter format to print the address.
Change-Id: Ic240f2f9ddb0272883aba393d687b3e47abe51e7
Use uncache-accelerated mem access to initialize the ECC Mem. This works
on 3a8780e, 3a82h, 3c780e, 3cserver for now
Change-Id: I0a0e62dfecb0a49d3a3faa5cd17849bf98fd49f2
2. Modify a offset value for ARB_level.
3. remove unneeded LOONGSON_3A3 from 3cserver and just SRS RDIMM param
Change-Id: I2220a81c9b91e3e9dfe481240f694057d9852e03
*. use a read only regitser on 3b7 (read-write on 3b5) to
separate 3b5 from 3b7, and register k0 to 0 to indicate 3b7, not 0
to indication 3b5
*. pmon built for 3b7 can run on 3b5 board with bootcore
id to 1, while the same pmon binary runs on 3b7 board with bootcore
id to 0 with coresponding reserve core mask changed;
*. restore bootcore_id and reserved core mask to be compatible
with 3b5
*. power down all pll for 3b6 and 3b7
*. fix reboot and poweroff
*. fix glitch of ddr by define DDR_DLL_BYPASS
*. add CHANGE_VOLT to modify cpu core volt, not enabled by default
Change-Id: I97f087d4c31e8d694d4de1fa1f7d3b11f96166a6
lixuefeng
zhangbaoqi
Wang Huandong
Huang Shuai
Xiaofu Meng
mengtianfang
Zhigang Liang
Huang Pei
Chen Xinke