1.Pmon can boot from SPI flash SST25VF032B.
2.The NVRAM_OFFS is defined as 0x7f000,
the gzrom.bin size should less than 0x7f000.
3.If add the nand flash function, the gzrom.bin
size will be out of 0x7f000.
4.The network card mac addr should be saved
into SPI flash, and acquired from SPI flash.
Change-Id: Id1f3e642a750ddeeb23f3b726e3f67a1ac855340
Target:LS2G + 1A + DDR3
1.Support uart, gmac on 2G, PS2, usb-ohci,
Sata, Vga, rtc and Pci net card devices.
2.The function of gmac on 2G needs modification
about PCB board.
3.The function of Sata needs modification
about Sata clock chip.
4.The series of 2G1A board include:
2G3+1A+DDR2, 2G5+1A+DDR2, 2G5+1A+DDR3.
The last one, PS2 is on 2G, the others are on 1A.
5.Modify Targets/Bonito2g1a/conf/Bonito.2g1a
Modify Targets/Bonito2g5ddr2_1a/conf/Bonito.2g5ddr2_1a
Modify pmon/dev/kbd.c and pmon/dev/kbd.h because of
the PS2 difference.
Target: LS2G5 + 1A + DDR3
Change-Id: I66f1e78e5672dd706331746c64c4db45371dfc00
1.Nandflash can be erased, read, written.
2.Could save kernel into nandflash.
3.Could load kernel form nandflash.
Target:2G5+1A+DDR2
Change-Id: Ic102439551c7cd90bba574aab477d8a502ff458c
ddr frequency for 2GQ/~3A5/~3B4.
2. Add example code to specify wrlvl_dq_dly separately when enable ARB_LEVEL in 3a780e branch.
3. Modify the PMON print MC parameter format to print the address.
Change-Id: Ic240f2f9ddb0272883aba393d687b3e47abe51e7
Use uncache-accelerated mem access to initialize the ECC Mem. This works
on 3a8780e, 3a82h, 3c780e, 3cserver for now
Change-Id: I0a0e62dfecb0a49d3a3faa5cd17849bf98fd49f2
2. Modify a offset value for ARB_level.
3. remove unneeded LOONGSON_3A3 from 3cserver and just SRS RDIMM param
Change-Id: I2220a81c9b91e3e9dfe481240f694057d9852e03
*. use a read only regitser on 3b7 (read-write on 3b5) to
separate 3b5 from 3b7, and register k0 to 0 to indicate 3b7, not 0
to indication 3b5
*. pmon built for 3b7 can run on 3b5 board with bootcore
id to 1, while the same pmon binary runs on 3b7 board with bootcore
id to 0 with coresponding reserve core mask changed;
*. restore bootcore_id and reserved core mask to be compatible
with 3b5
*. power down all pll for 3b6 and 3b7
*. fix reboot and poweroff
*. fix glitch of ddr by define DDR_DLL_BYPASS
*. add CHANGE_VOLT to modify cpu core volt, not enabled by default
Change-Id: I97f087d4c31e8d694d4de1fa1f7d3b11f96166a6
2. change the MSB of addr from 16 to 15 to accommadate old 3A780e board, so we can only use 4GB memory space
Change-Id: I32bfcff3960976b90149f88170e2319c72d2c708
1. put the Memory controller/chip-specific code into separate files.
2. Clean up the Bonito directory of some branch.
Change-Id: Idf6a4cab4fa1b9af3b819756d69da036f7cfac4a
For the same MC, extract the public code for configure MC parameters to lsmcd3_config_param.S.
For different chips, use different mc_init file.
~3A5/2GQ: ddr_config.S
~3B4 : 3B_ddr_config.S
2G : 2G_ddr_config.S
2. move code of configure MC frequency by software for ~3A5 to subrutine.
3. Modify code to support auto arb_level when change the DDR frequency by software configuration.
Change-Id: I9a1d2b08aa4f282523dfb3b62d17e2c0291b6a17
1.Add zloader.2g5ddr2_1a and Target/Bonito2g5ddr2
2.Port the new MC initialization code for 2j5.(ARB_LEVEL cannot pass compiling now).
3.Modify the start.S for the difference between 2g3 and 2g5:
* The jr instructions can only use the ra register
* Hardware initialise scache
* Shut down the store fill buffer for scache coherent
Change-Id: I7d2946ea02ed95763688202d750e9644bae14807
Target:2G5+1A+DDR2
1.
Targets/Bonito3a2h/Bonito/loongson3_HT_init_2h.S
Targets/Bonito3a82h/Bonito/loongson3_HT_init_2h.S
use window 5(no use before) for pcie graphic card in this patch
2.
pmon/cmds/pcicmds.c
sys/dev/pci/pciconf.c
sys/dev/pci/pcireg.h
sys/kern/subr_autoconf.c
sys/linux/io.h
x86emu/int10/generic.c
x86emu/int10/helper_exec.c
x86emu/int10/xf86int10.c
these file are basic code that modified in this path
3.
Targets/Bonito3a2h/Bonito/loongson3_HT_init_2h.S
Targets/Bonito3a2h/Bonito/tgt_machdep.c
Targets/Bonito3a2h/conf/Bonito.3a2h
Targets/Bonito3a2h/pci/ls2h_pci.c
Targets/Bonito3a2h/pci/pci_machdep.c
Targets/Bonito3a82h/Bonito/loongson3_HT_init_2h.S
Targets/Bonito3a82h/Bonito/tgt_machdep.c
Targets/Bonito3a82h/conf/Bonito.3a82h
Targets/Bonito3a82h/pci/ls2h_pci.c
Targets/Bonito3a82h/pci/pci_machdep.c
these files have only relate to 3a2h and 3a82h
Change-Id: I4a182bcbb8ca83f3fd34028145d362e7d2e683f0
has some errors(mostly at 35bit) at 600MHz, only testd MC0
fix board info for 3a2000 and replace cpu freq with bogoMIPS
Change-Id: I2d937ebb643eff85a52f75c62639f643050fe52f
origin commit msg is:
Change parameter to optimise 667MHz DDR performance
(but this version may cause error, change tCCD to 0x6 can fix this error.
add MC1 DDR, 667MHz still has error, this version CPU 850MHz, DDR 600MHz,
SPEC ref pass)
Change-Id: I71e6a7d7271008509120293bc26d37bfd954b7f2
mengtianfang
Huang Pei
Chen Xinke
Huang Shuai
Zhigang Liang
lixuefeng