1. increase SATA/USB cntl freq to improve sata read performance.
2. reduce GPU/GMEM freq to 400M/533M for mass product.
3. enhance pcie signal quality.
Change-Id: I77abde0636e7b694dd41167d859db4b981b8fe03
1. signal test support for usbtest and satatest cmd.
2. ls7a_dbg support phy_cfg cmd. notice that: make sure the phy to be configured is not powerdown.
Change-Id: Ib86ba06b5554c87cb92bbd6c12e1f96d47683fa7
Notice that: 7A only support use inner or outer ref clk for all PCIE ports.
If you want to use outer ref clk for some ports, you must disable others by code..
Change-Id: Ie54ee937bd9321f817315da725f3f0ef47cac32d
1. Fix PCIE PHY voltage configure which can fix some PCIE unstable problem.
2. Fix x8 PCIE powerdown bug.
3. Add option to NOT powerdown PCIE for debug.
Change-Id: I0223885259d0eab4138e322e83d0d47f5f066822
cmd "make dtb" can create dtb file: Bonito3a3000_7a.dtb, and link with gzrom.bin to create gzrom-dtb.bin
rename Targets/LS2K/conf/ls2k.dts to Targets/LS2K/conf/LS2K.dts
Change-Id: I8ba7dcd6b0e8cc875324666d5774cfd8fa9a10f6
Our PCIE controller return 0 instead of -1 for non-existent PCIE device, so we
should add != 0 condition for null device.
And we also translate 0 to -1 for null device ID although PMON does not care.
Change-Id: I5d1d3f458ec3d0a54b02ba36e221b87f77b7b3f5
ls2k map_gpu printf change to tgt_printf.
Because pci mem has been chanaged, can not call any driver.
printf will call all poll function, which will cause sys halt.
Change-Id: Ia956fb1c5257e19ca8f29dabeda026330d088322
Signed-off-by: QiaoChong <qiaochong@loongson.cn>
Check the mac addr in dtb & eeprom after boot, or after load_dtb;
If mem size in dtb is larger than max mem size, abort cmd "g";
Change-Id: I7b122658199915493a79cc99812485f43dc08c35
The current version uses PCIE_*_PRSNTnX to decide which PCIE Port will be initialized,
but this not work when you put some PCIE device card into a narrower PCIE socket(like a x16 video card
in a x8 socket), because some of these cards only connect the farest PRSNTn PIN to gnd, and causes
our mother board cannot detect the device.
In this version, we use link state of each PCIE port to decide whether to enable it.
So the PCIE_*_PRSNTn0 PIN is not cared any more as declaimed in early datasheet.
As long as PCIE_*_PRSNTn1/2/3 PINs are correctly dealed on mother board, you need do nothing with the BIOS.
But you need to modify the BIOS configure code in one situation where:
you split a PCIE interface, and route Port1/2/3 to a socket, and put a wider device card into it(which should be rare).
Because in this situation, the PRSNTn1/2/3 PIN is not pull-down which cause the LS7A1000 PCIE works in solo Port
mode, so the device will never be detected.
Change-Id: I7aeafea849c799a4fa0a81ce023bd8144c922eda
The last PCIE auto-configure patch also fixes unexpected PCIE controller interrupt,
so it should not be ignored.
Change-Id: I619661511ad3cf2e22f6de7fc30c26b315ce0b3c
1. Do not override SATA PHY TX parameters by PHY control interface.
2. Add some debug info to ahci driver.
Change-Id: I5e000aed5cd914bf065211eea1328ac9b006dd4a
wuze
Chen Xinke
zhangbaoqi
WANG Yulong
xuwenrui
QiaoChong
baoqingyuan
Huang Shuai